FR2572212B1 - Procede d'ecriture pour matrices de cellules de memoire permanente de type " merged " (ou fusionne) - Google Patents

Procede d'ecriture pour matrices de cellules de memoire permanente de type " merged " (ou fusionne)

Info

Publication number
FR2572212B1
FR2572212B1 FR858515758A FR8515758A FR2572212B1 FR 2572212 B1 FR2572212 B1 FR 2572212B1 FR 858515758 A FR858515758 A FR 858515758A FR 8515758 A FR8515758 A FR 8515758A FR 2572212 B1 FR2572212 B1 FR 2572212B1
Authority
FR
France
Prior art keywords
merged
memory cell
writing method
permanent memory
cell matrices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR858515758A
Other languages
English (en)
Other versions
FR2572212A1 (fr
Inventor
Andrea Ravaglia
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
SGS Microelettronica SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Microelettronica SpA filed Critical SGS Microelettronica SpA
Publication of FR2572212A1 publication Critical patent/FR2572212A1/fr
Application granted granted Critical
Publication of FR2572212B1 publication Critical patent/FR2572212B1/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)
FR858515758A 1984-10-23 1985-10-23 Procede d'ecriture pour matrices de cellules de memoire permanente de type " merged " (ou fusionne) Expired FR2572212B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8423281A IT1213228B (it) 1984-10-23 1984-10-23 Metodo di scrittura per matrice di celle di memoria non volatile di tipo merged.

Publications (2)

Publication Number Publication Date
FR2572212A1 FR2572212A1 (fr) 1986-04-25
FR2572212B1 true FR2572212B1 (fr) 1989-05-19

Family

ID=11205614

Family Applications (1)

Application Number Title Priority Date Filing Date
FR858515758A Expired FR2572212B1 (fr) 1984-10-23 1985-10-23 Procede d'ecriture pour matrices de cellules de memoire permanente de type " merged " (ou fusionne)

Country Status (6)

Country Link
JP (1) JPS6199997A (fr)
DE (1) DE3537046A1 (fr)
FR (1) FR2572212B1 (fr)
GB (1) GB2166019B (fr)
IT (1) IT1213228B (fr)
NL (1) NL8502731A (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4783766A (en) * 1986-05-30 1988-11-08 Seeq Technology, Inc. Block electrically erasable EEPROM
JPS6439694A (en) * 1987-08-05 1989-02-09 Mitsubishi Electric Corp Non-volatile semiconductor memory device
JPH0770233B2 (ja) * 1987-07-15 1995-07-31 三菱電機株式会社 不揮発性半導体記憶装置の書込および消去方法
JPH01289170A (ja) * 1988-05-16 1989-11-21 Toshiba Corp 不揮発性半導体記憶装置
JP2732070B2 (ja) * 1988-07-12 1998-03-25 三菱電機株式会社 不揮発性半導体記憶装置の書込み方法
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4377857A (en) * 1980-11-18 1983-03-22 Fairchild Camera & Instrument Electrically erasable programmable read-only memory
IE55327B1 (en) * 1981-12-29 1990-08-15 Fujitsu Ltd Nonvolatile semiconductor memory circuit

Also Published As

Publication number Publication date
FR2572212A1 (fr) 1986-04-25
JPS6199997A (ja) 1986-05-19
GB2166019B (en) 1988-06-02
IT8423281A0 (it) 1984-10-23
GB8524039D0 (en) 1985-11-06
NL8502731A (nl) 1986-05-16
IT1213228B (it) 1989-12-14
DE3537046A1 (de) 1986-04-24
GB2166019A (en) 1986-04-23

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Legal Events

Date Code Title Description
D6 Patent endorsed licences of rights
ST Notification of lapse