FR2514562A1 - Multilayer hybrid capacitor circuit and internal connections - has dielectric block with interconnections via pierced metallised holes to provide internal connection between layers - Google Patents

Multilayer hybrid capacitor circuit and internal connections - has dielectric block with interconnections via pierced metallised holes to provide internal connection between layers Download PDF

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FR2514562A1
FR2514562A1 FR8119076A FR8119076A FR2514562A1 FR 2514562 A1 FR2514562 A1 FR 2514562A1 FR 8119076 A FR8119076 A FR 8119076A FR 8119076 A FR8119076 A FR 8119076A FR 2514562 A1 FR2514562 A1 FR 2514562A1
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dielectric block
layers
capacitors
sheets
circuit
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FR2514562B1 (en
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Christian Val
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Thales SA
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Thomson CSF SA
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    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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Abstract

The circuit is comprised of a dielectric block having two zones and supporting active or positive components (6). The lower zone (A) has a stack of thin alumina layer (1), 15 to 50 microns thick, with the interfaces coated with metal (2) to form one or more capacitors. The upper zone (B) has a stack of thicker alumina layers (2), 300 to 600 microns thick, whose interfaces have metal coatings (8) to form interconnecting layers. Electrical connections between the different layers of dielectric (capacitors and interconnecting layers) and the other components are made internally via metallised holes (3) pierced in the dielectric block before heat treatment and layer interconnection. A radiator (4) for heat dissipation is fixed to one face of the dielectric block. The device is partic. intended for voltage multiplying circuits which use diode-capacitor couples, the diodes being assembled in a semiconductor substrate interconnected with the dielectric block.

Description

CIRCUIT HYBRIDE MULTICOUCHE A CONDENSATEURS
ET LIAISONS INTERNES
L'invention concerne la réalisation à partir d'un même substrat d'une fonction complète comprenant des condensateurs, des réseaux multicouches d'interconnexions et un ou plusieurs circuits intégrés.MULTI-LAYER CONDENSER HYBRID CIRCUIT
AND INTERNAL LINKS
The invention relates to the realization, from the same substrate, of a complete function comprising capacitors, multilayer networks of interconnections and one or more integrated circuits.

Actuellement on associe les composants actifs et passifs d'un système électronique par câblage et/ou brasure tendre sur un substrat isolant. Ce mode de réalisation outre un encombrement important, introduit d'autres inconvénients non négligeables qui sont notamment les résistances de fuite, les capacités parasites, les problèmes causés par l'humidité ambiante et les poussières, les perturbations provoquées par les circuits électriques se trouvant à proximité. Dans tous les cas, la réduction de la taille des composants et de leurs connexions ne peut qu'atténuer les effets parasites et augmenter la fiabilité des systèmes. Currently, the active and passive components of an electronic system are combined by wiring and / or soft solder on an insulating substrate. This embodiment, in addition to a large bulk, introduces other non-negligible drawbacks which are in particular the leakage resistances, the parasitic capacitances, the problems caused by ambient humidity and dust, the disturbances caused by the electrical circuits being proximity. In all cases, reducing the size of the components and their connections can only mitigate spurious effects and increase the reliability of the systems.

Il est particulièrement intéressant d'intégrer les fonctions comprenant des condensateurs. En effet, dans les circuits réalisés selon les techniques classiques, ces éléments sont assez encombrants et les systèmes comprenant un certain nombre de condensateurs et de composants actifs tels que des diodes qui elles sont facilement intégrables, voient la longueur de leurs connexions accroître inutilement ainsi que le nombre de croisements des liaisons. Pour remédier à ces inconvénients on peut utiliser plusieurs technologies:
- la technologie d'interconnexion par multicouches alumine co-cuit, c'est ce qui est utilisé pour réaliser les "DIL" (Dual In Line) céramiques, les "chip-carriers", les multicouches.It is particularly interesting to integrate the functions comprising capacitors. In fact, in the circuits produced according to conventional techniques, these elements are quite bulky and the systems comprising a certain number of capacitors and active components such as diodes which are easily integrated, see the length of their connections unnecessarily increase as well as the number of link crossings. To overcome these drawbacks, several technologies can be used:
- interconnection technology by co-fired alumina multilayers, this is what is used to make ceramic "DIL" (Dual In Line), "chip-carriers", multilayers.

- la technologie de réalisation des condensateurs multicouches généralement à base de feuilles minces (10-20 microns) de céramique diélectrique (titanate de baryum, de strontium, etc.)
L'association de ces deux technologies en vue de réaliser à la fois des condensateurs multiples, interconnectés ou non entre eux, avec d'autres composants, constitue un progrès important dans l'intégration et la technique de connexion. Dans le même ordre d'idée, la demanderesse a déposé une demande de brevet le 2 septembre 1980 sous le numéro d'enregistrement national 80 18927 et intitulée "Micro-boîtier céramique d'encapsulation de circuit électronique". Cette demande concerne un "chip-carrier" à découplage, mais l'interconnexion ne fait pas appel à la technique multicouches.- the technology for producing multilayer capacitors generally based on thin sheets (10-20 microns) of dielectric ceramic (barium titanium, strontium, etc.)
The combination of these two technologies in order to produce both multiple capacitors, interconnected or not, with other components, constitutes an important advance in integration and connection technique. In the same vein, the applicant filed a patent application on September 2, 1980 under the national registration number 80 18927 and entitled "Ceramic micro-encapsulation of electronic circuit encapsulation". This request concerns a decoupling chip-carrier, but the interconnection does not require the multilayer technique.

Dans le cas présent, on combine les deux technologies.In this case, we combine the two technologies.

Dans les procédés selon l'art connu, les liaisons entre le condensateur intégré dans le substrat et les composants ou circuits déposés sur ce substrat se faisaient sur les côtés de la pastille. Le procédé selon l'invention permet par l'utilisation de trous métallisés et par un procédé de réalisation particulier, de réunir plusieurs condensateurs au sein d'un bloc diélectrique et de connecter une ou plusieurs électrodes avec d'autres éléments (résistances, selfs, circuits actifs, etc.) sans repasser par une découpe unitaire ou par des électrodes latérales. In the methods according to the known art, the connections between the capacitor integrated in the substrate and the components or circuits deposited on this substrate were made on the sides of the pellet. The method according to the invention makes it possible, by the use of metallized holes and by a particular production method, to bring together several capacitors within a dielectric block and to connect one or more electrodes with other elements (resistors, inductors, active circuits, etc.) without passing through a unit cutout or by side electrodes.

L'invention concerne donc un circuit monolithique caractérisé en ce que au moins deux empilages de feuillets de céramique superposés forment un bloc diélectrique supportant des composants actifs et/ou passifs, les interfaces des feuillets d'un desdits empilages comportant des métallisations pour former au moins un condensateur, les feuillets de l'autre ou des autres couches étant d'épaisseur sensiblement plus grande et comportant des métallisations pour former des couches d'interconnexion, les liaisons électriques reliant le ou lesdits condensateurs auxdits composants étant réalisées par l'intermédiaire de trous métallisés percés dans le bloc diélectrique avant cuisson et des feuillets d'interconnexion. The invention therefore relates to a monolithic circuit characterized in that at least two stacks of superimposed ceramic sheets form a dielectric block supporting active and / or passive components, the interfaces of the sheets of one of said stacks comprising metallizations to form at least a capacitor, the sheets of the other or of the other layers being of substantially greater thickness and comprising metallizations for forming interconnection layers, the electrical connections connecting the said capacitor (s) to the said components being produced by means of holes metallized drilled in the dielectric block before firing and interconnection sheets.

L'invention concerne plus particulièrement un circuit multiplicateur de tension. Dans ce type de circuit, on utilise conjointement des diodes et des condensateurs en nombre relativement important si le nombre multiplicateur est élevé. La technologie selon l'invention se prête très bien à ce cas particulier et permet d'obtenir des circuits délivrant plusieurs milliers de volts pour des dimensions très réduites. The invention relates more particularly to a voltage multiplier circuit. In this type of circuit, diodes and capacitors are used in relatively large numbers if the multiplier number is high. The technology according to the invention lends itself very well to this particular case and makes it possible to obtain circuits delivering several thousand volts for very small dimensions.

L'invention sera mieux comprise au moyen de la description ci-après et des figures annexées parmi lesquelles:
- la figure 1 est une vue en coupe d'un circuit selon l'invention,
- la figure 2 est un schéma électrique d'un circuit multiplicateur de tension,
- la figure 3 est un schéma montrant la disposition des éléments du circuit de la figure 2.The invention will be better understood by means of the description below and the appended figures among which:
FIG. 1 is a sectional view of a circuit according to the invention,
FIG. 2 is an electrical diagram of a voltage multiplier circuit,
FIG. 3 is a diagram showing the arrangement of the elements of the circuit of FIG. 2.

- la figure 4 est une vue en coupe d'une partie d'un bloc diélectrique suivant l'invention. - Figure 4 is a sectional view of part of a dielectric block according to the invention.

La figure 1 est une vue en coupe d'un circuit selon l'invention. Dans cet exemple, on a choisi comme diélectrique de l'alumine. C'est un matériau bien éprouvé et compatible mécaniquement avec le silicium qui pourra être à la base de la fabrication d'éléments rapportés. L'alumine permet par ailleurs de réaliser des multicouches à faible couplage parasite car la constante diélectrique est faible. D'autres matériaux isolants peuvent bien sur être utilisés pour des applications particulières. Figure 1 is a sectional view of a circuit according to the invention. In this example, alumina was chosen as the dielectric. It is a well proven material and mechanically compatible with silicon which could be the basis for the production of inserts. Alumina also makes it possible to produce multilayers with low parasitic coupling because the dielectric constant is low. Other insulating materials can of course be used for particular applications.

La figure 1 permet de mieux imaginer la structure du module. En partant du bas du bloc diélectrique, on rencontre une première zone (zone A) dite "zone multicouche fine" permettant de réaliser les condensateurs. Figure 1 helps to better imagine the structure of the module. Starting from the bottom of the dielectric block, there is a first zone (zone A) called "thin multilayer zone" allowing the capacitors to be produced.

Celle-ci est constituée de feuilles I en alumine d'épaisseur faible, par exemple de 15 à 50 microns selon la capacité spécifique nécessaire. Sur chaque feuille 1 non cuite sont déposées par sérigraphie ou par d'autres techniques, des électrodes 2 qui définiront les valeurs des condensateurs.This consists of alumina sheets I of small thickness, for example from 15 to 50 microns depending on the specific capacity required. On each sheet 1 uncooked are deposited by screen printing or by other techniques, electrodes 2 which will define the values of the capacitors.

Les électrodes sont alternées et raccordées (les électrodes paires ensemble et les impaires ensemble) de façon à associer les condensateurs élémentaires en parallèle selon l'art connu des fabricants de condensateurs céramiques multicouches. Une différence importante avec cette dernière technique consiste à interconnecter les électrodes non pas par l'extérieur (sur les faces latérales du substrat en alumine) mais à l'intérieur du bloc diélectrique par l'intermédiaire de trous métallisés 3. Cette technique permet de réaliser plusieurs condensateurs dans le même substrat.L'ordre de grandeur de la capacité par couche d'alumine est de 180 pF pour une couche de 25 microns 2 d'épaisseur et pour urw surface d'électrode de 45 mm
Les métallisations des couches d'alumine peuvent être réalisées en tungstène ou en molybdène ou tout autre métal qui supporte correctement la température de cuisson.The electrodes are alternated and connected (the even electrodes together and the odd ones together) so as to associate the elementary capacitors in parallel according to the known art of the manufacturers of multilayer ceramic capacitors. An important difference with this latter technique consists in interconnecting the electrodes not from the outside (on the lateral faces of the alumina substrate) but inside the dielectric block by means of metallized holes 3. This technique makes it possible to produce several capacitors in the same substrate. The order of magnitude of the capacity per layer of alumina is 180 pF for a layer 25 microns 2 thick and for urw electrode surface of 45 mm
The metallizations of the alumina layers can be made of tungsten or molybdenum or any other metal which correctly withstands the firing temperature.

Au-dessus de la zone multicouche fine se trouve une deuxième zone (zone B) dite "zone multicouche d'interconnexion". Elle est formée de couches d'alumine 5 dont l'épaisseur peut aller de 300 à 600 microns et sur lesquelles on a déposé, par exemple par sérigraphie, des conducteurs 8 de même nature que les électrodes de la première zone multicouche. Ces conducteurs ont pour rôle d'assurer les liaisons électriques entre les condensateurs formés dans la première zone multicouche et les éléments discrets ou intégrés tels que 6 déposés sur le bloc diélectrique. L'épaisseur des couches d'interconnexion est plus grande que celle des couches de la première zone parce que là on recherche une très faible capacité entre les plans. Above the thin multilayer zone is a second zone (zone B) called "multilayer interconnection zone". It is formed of alumina layers 5 whose thickness can range from 300 to 600 microns and on which are deposited, for example by screen printing, conductors 8 of the same kind as the electrodes of the first multilayer zone. These conductors have the role of ensuring the electrical connections between the capacitors formed in the first multilayer zone and the discrete or integrated elements such as 6 deposited on the dielectric block. The thickness of the interconnection layers is greater than that of the layers of the first zone because there we are looking for a very low capacity between the planes.

La grande originalité que présente l'invention est que les liaisons entre les différentes couches du diélectrique (condensateurs, couches d'interconnexion) et les éléments rapportés sont réalisées par des trous métallisés. Les trous sont effectués dans les feuilles en alumine avant cuisson. Jusqu'ici, l'utilisation de trous métallisés ne concernait que la technologie des substrats multicouches (circuits imprimés multicouches). Le perçage des trous réalisé avant superposition des différentes couches et avant cuisson ne pose aucun problème particulier. The great originality of the invention is that the connections between the different layers of the dielectric (capacitors, interconnection layers) and the added elements are made by metallized holes. The holes are made in the alumina sheets before cooking. Until now, the use of metallized holes has only concerned the technology of multilayer substrates (multilayer printed circuits). The drilling of the holes made before superimposing the different layers and before baking poses no particular problem.

Le bloc diélectrique peut comprendre 2, 3 n couches dtintercon- nexion. Le nombre de couches est lié à la densité d'interconnexions visée, aux capacités de couplages imposées, à la dissipation thermique nécessaire. The dielectric block can comprise 2, 3 n interconnection layers. The number of layers is linked to the targeted interconnection density, to the imposed coupling capacities, to the necessary heat dissipation.

Les résistances peuvent être déposées sur les surfaces externes du substrat ou sur les faces internes si les températures de frittage du matériau isolant sont compatibles avec les températures de mise en oeuvre des matériaux résistifs. The resistors can be deposited on the external surfaces of the substrate or on the internal faces if the sintering temperatures of the insulating material are compatible with the processing temperatures of the resistive materials.

Les éléments actifs peuvent être rapportés sur le verso ou le recto, ou les deux à la fois, du bloc diélectrique ainsi constitué. Il peut également être prévu deux couches d'interconnexions, la zone formant les condensateurs étant insérée entre ces deux couches. Les éléments actifs semi-conducteurs seront connectés selon les technologies habituelles: sous forme de boîtiers (plastique, céramique, métallique) ou sous forme de pastilles nues. Le câblage des pastilles nues peut se faire par câblage fil à fil, par les technologies appelées "flip-chip", "beam-lead" et TAB (transfert automatique sur bande). The active elements can be attached to the back or the front, or both at the same time, of the dielectric block thus formed. Two interconnection layers can also be provided, the area forming the capacitors being inserted between these two layers. The semiconductor active elements will be connected according to the usual technologies: in the form of cases (plastic, ceramic, metallic) or in the form of bare pellets. The wiring of the bare pads can be done by wire to wire wiring, by technologies called "flip-chip", "beam-lead" and TAB (automatic transfer to tape).

Dans ces derniers cas la protection mécanique des pastilles nues peut être réalisée par une résine type silicone ou époxy ou bien par un capot céramique 7 (en alumine par exemple) collé ou brasé sur le bloc diélectrique.  In these latter cases, the mechanical protection of the bare pellets can be achieved by a silicone or epoxy type resin or else by a ceramic cover 7 (made of alumina for example) bonded or brazed to the dielectric block.

Un radiateur 4 peut être fixer sur l'une des faces du bloc afin d'assurer une dissipation thermique. A radiator 4 can be attached to one of the faces of the block in order to ensure heat dissipation.

Les connexions de sortie peuvent être constituées par des connexions rigides (type "lead frame") mais on peut avantageusement associer l'astuce des boîtiers "chip carrier" consistant à utiliser des demi-trous métallisés. The output connections can be constituted by rigid connections ("lead frame" type) but one can advantageously associate the trick of "chip carrier" boxes consisting in using metallized half-holes.

Cette technologie est familière aux fabricants de microboîtiers en alumine du type "DIL" et "chip-carrier"; par ailleurs elle constitue une utilisation maximale du multicouche d'interconnexion.This technology is familiar to manufacturers of "DIL" and "chip-carrier" alumina micro-housings; moreover, it constitutes maximum use of the interconnection multilayer.

La technologie révélée par l'invention se montre particulièrement avantageuse dans les circuits comportant plusieurs condensateurs. Un cas particulièrement intéressant est le multiplicateur de tension qui utilise des couples diode-condensateur. The technology revealed by the invention is particularly advantageous in circuits comprising several capacitors. A particularly interesting case is the voltage multiplier which uses diode-capacitor pairs.

Il existe plusieurs configurations de circuits multiplicateurs de tension. There are several configurations of voltage multiplier circuits.

La figure 2 montre le schéma électrique d'un circuit multiplicateur par huit et composé de 8 diodes D et de 8 condensateurs C. Pour un signal d'entrée alternatif et sinusoïdal ul = U1 sin wt, la tension de sortie du dispositif sera u2 = 8 ul. On voit que dans ce circuit, les condensateurs sont amenés à supporter des tensions élevées qui sont le double de la valeur maximale de la tension d'entrée, soit 2U1. Les diodes doivent également pouvoir supporter en inverse les mêmes valeurs de tension.Figure 2 shows the electrical diagram of a circuit multiplier by eight and composed of 8 diodes D and 8 capacitors C. For an alternating and sinusoidal input signal ul = U1 sin wt, the output voltage of the device will be u2 = 8 ul. We see that in this circuit, the capacitors are made to withstand high voltages which are twice the maximum value of the input voltage, ie 2U1. The diodes must also be able to withstand the same voltage values in reverse.

Il est particulièrement avantageux d'utiliser dans la réalisation des condensateurs, un diélectrique alumine car ceux-ci tiennent mieux les hautes tensions. Dans le circuit multiplicateur choisi plus haut, les 8 condensateurs ont la même valeur ; ce cas est idéal et relativement simple. It is particularly advantageous to use, in the production of the capacitors, an alumina dielectric because they better withstand high voltages. In the multiplier circuit chosen above, the 8 capacitors have the same value; this case is ideal and relatively simple.

Il entre également dans le cadre de l'invention de disposer de condensateurs réalisés dans le substrat et qui ont des valeurs différentes. On peut par exemple garder le même nombre de couches diélectriques pour tous les condensateurs et jouer sur la surface ou le nombre de leurs électrodes pour disposer de capacités de valeurs diverses. Dans le cas des circuits multiplicateurs de tension, on peut être amené, pour des raisons qui dépendent principalement de la charge du circuit, à disposer de condensateurs de valeurs plus élevées lorsqu'ils sont plus proches de la source délivrant la tension ul.  It is also within the scope of the invention to have capacitors produced in the substrate and which have different values. One can for example keep the same number of dielectric layers for all the capacitors and play on the surface or the number of their electrodes to have capacities of various values. In the case of voltage multiplier circuits, it may be necessary, for reasons which mainly depend on the load of the circuit, to have capacitors of higher values when they are closer to the source delivering the voltage ul.

Les 32 liaisons (condensateurs, diodes) seront internes et se feront par l'intermédiaire de trous métallisés. Les 8 diodes peuvent être discrètes ou rassemblées en un circuit intégré de 8 diodes avec plots classiques ou avec bossages "flip-chip". The 32 connections (capacitors, diodes) will be internal and will be made through metallized holes. The 8 diodes can be discrete or assembled in an integrated circuit of 8 diodes with conventional pads or with "flip-chip" bosses.

La figure 3 est un schéma explicatif d'une disposition possible des éléments du circuit dont le schéma électrique a été donné à la figure 2. FIG. 3 is an explanatory diagram of a possible arrangement of the elements of the circuit whose electrical diagram has been given in FIG. 2.

La figure 3 est une vue de dessus d'un bloc diélectrique 9 composé d'une superposition de feuillets de matériau céramique, de l'alumine par exemple. Comme décrit plus haut, ce bloc se compose de deux zones. Une première zone de feuillets forme les 8 condensateurs prévus dans le circuit multiplicateur. Les électrodes délimitant ces condensateurs sont représentées en traits pointillés; les électrodes 10 sont par exemple les électrodes paires et les électrodes Il les impaires. Sur la première zone de feuillets vient s'ajouter une seconde zone de feuillets d'interconnexion du genre de ceux décrits plus haut. Sur chacun de ces feuillets on a déposé des conducteurs qui serviront à relier les condensateurs conçus dans la première zone aux éléments rapportés sur le bloc diélectrique.Des trous métallisés 12 relient entre elles les différentes électrodes, paires ou impaires, de chaque condensateur. Ces trous servent également à relier les condensateurs aux conducteurs placés sur les couches d'interconnexion. D'autres trous métallisés 13 sont réalisés afin de relier, toujours par l'intermédiaire des couches d'interconnexion, les diodes aux condensateurs. Dans l'exemple de la figure 3, les diodes ont été intégrées dans un circuit 15 du type "chipcarrier" et reliées par des fils 14 aux trous 13. Sur la couche supérieure du bloc diélectrique, on a déposé une métallisation 16 sur laquelle viendra se fixer par brasure tendre un capot.Ce capot peut être métallique (par exemple en ferro-nickel qui a un coefficient de dilatation du même ordre de grandeur que celui de l'alumine) ou en céramique avec une métallisation (par exemple en alliage argent-palladium) au niveau du contact avec la métallisation 16 afin de permettre la soudure avec celle-ci. Le capot peut encore être fixé par collage en utilisant une colle époxy. Figure 3 is a top view of a dielectric block 9 composed of a superposition of sheets of ceramic material, alumina for example. As described above, this block consists of two areas. A first zone of sheets forms the 8 capacitors provided in the multiplier circuit. The electrodes delimiting these capacitors are shown in dotted lines; the electrodes 10 are for example the even electrodes and the odd electrodes II. On the first area of sheets is added a second area of interconnection sheets of the kind described above. On each of these sheets, conductors have been deposited which will serve to connect the capacitors designed in the first zone to the elements attached to the dielectric block. Metallized holes 12 connect the different electrodes, even or odd, of each capacitor. These holes also serve to connect the capacitors to the conductors placed on the interconnection layers. Other metallized holes 13 are made in order to connect, still via the interconnection layers, the diodes to the capacitors. In the example of FIG. 3, the diodes have been integrated into a circuit 15 of the "chipcarrier" type and connected by wires 14 to the holes 13. On the upper layer of the dielectric block, a metallization 16 has been deposited on which will come attach by soft soldering a cover. This cover can be metallic (for example ferro-nickel which has a coefficient of expansion of the same order of magnitude as that of alumina) or ceramic with metallization (for example silver alloy -palladium) at the contact with the metallization 16 in order to allow the soldering with the latter. The cover can also be fixed by gluing using an epoxy adhesive.

Il entre également dans le cadre de l'invention de prévoir un évidement dans la partie supérieure du bloc diélectrique afin d'y introduire les éléments rapportés et de prévoir un capot plus plat. Cette disposition est montrée à la figure 4. Cette figure est une vue en coupe du bloc diélectrique dont on ne voit que là partie supérieure formée des couches d'interconnexion 17. Les deux dernières couches ont été évidées afin de disposer un circuit 18 et ses liaisons 19. Cet évidement permet de disposer d'un capot 20 plus plat que celui utilisé dans l'exemple précédent. It is also within the scope of the invention to provide a recess in the upper part of the dielectric block in order to introduce the added elements therein and to provide a flatter cover. This arrangement is shown in Figure 4. This figure is a sectional view of the dielectric block of which we can only see the upper part formed by the interconnection layers 17. The last two layers have been hollowed out in order to have a circuit 18 and its connections 19. This recess makes it possible to have a cover 20 that is flatter than that used in the previous example.

L'association de plusieurs technologies: la technologie des condensateurs céramique multicouches, la technologie des substrats multicouches et celle des boîtiers du type "chip-carrier", permet d'intégrer plus de composants pour un même volume. Cette nouvelle technique conduit par ailleurs aux améliorations suivantes:
- réduction des longueurs d'interconnexion,
- fiabilité du module supérieure aux circuits hybrides à éléments rapportés,
- traitement collectif sur grands substrats (feuilles de 120 à 150 mm de côté) qui sont pré-découpés. The combination of several technologies: the technology of multilayer ceramic capacitors, the technology of multilayer substrates and that of "chip-carrier" type housings, allows more components to be integrated for the same volume. This new technique also leads to the following improvements:
- reduction in interconnection lengths,
- module reliability superior to hybrid circuits with added elements,
- collective treatment on large substrates (sheets 120 to 150 mm side) which are pre-cut.

Claims (5)

REVENDICATIONS 1. Circuit monolithique caractérisé en ce que au moins deux empilages de feuillets de céramique superposés forment un bloc diélectrique supportant des composants actifs et/ou passifs (6), les interfaces des feuillets (1) d'un desdits empilages comportant des- métallisations (2) pour former au moins un condensateur, les feuillets (5) de l'autre ou des autres couches étant d'épaisseur sensiblement plus grande et comportant des métallisations (8) pour former des couches d'interconnexion, les liaisons électriques reliant le ou lesdits condensateurs auxdits composants étant réalisées par l'intermédiaire de trous métallisés (3) percés dans le bloc diélectrique avant cuisson et des feuillets d'interconnexion. 1. Monolithic circuit characterized in that at least two stacks of superimposed ceramic sheets form a dielectric block supporting active and / or passive components (6), the interfaces of the sheets (1) of one of said stacks comprising metallizations ( 2) to form at least one capacitor, the sheets (5) of the other or other layers being of substantially greater thickness and comprising metallizations (8) to form interconnection layers, the electrical connections connecting the or said capacitors to said components being produced by means of metallized holes (3) drilled in the dielectric block before firing and interconnection sheets. 2. Circuit selon la revendication 1, caractérisé en ce que lesdits feuillets de céramique sont réalisés en alumine. 2. Circuit according to claim 1, characterized in that said ceramic sheets are made of alumina. 3. Circuit selon l'une des revendications 1 ou 2, caractérisé en ce que au moins un élément dissipateur de chaleur (4) est disposé sur le bloc diélectrique. 3. Circuit according to one of claims 1 or 2, characterized in that at least one heat sink element (4) is arranged on the dielectric block. 4. Circuit selon l'une quelconque des revendications 1 à 3, caractérisé en ce que les connexions de sortie sont constituées par des métallisations périphériques. 4. Circuit according to any one of claims 1 to 3, characterized in that the output connections are constituted by peripheral metallizations. 5. Circuit selon l'une quelconque des revendications 1 à 4, caractérisé en ce que le circuit est un dispositif multiplicateur de tension à diodes et condensateurs; lesdites diodes étant réunies dans un substrat semiconducteur interconnecté avec ledit bloc.  5. Circuit according to any one of claims 1 to 4, characterized in that the circuit is a voltage multiplier device with diodes and capacitors; said diodes being combined in a semiconductor substrate interconnected with said block.
FR8119076A 1981-10-09 1981-10-09 MULTI-LAYER HYBRID CIRCUIT WITH CAPACITORS AND INTERNAL CONNECTIONS Expired FR2514562B1 (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2587844A1 (en) * 1985-09-20 1987-03-27 Thomson Csf HYPERFREQUENCY CIRCUIT WITH LOW CAPACITY PARASITES
EP0379404A2 (en) * 1989-01-14 1990-07-25 TDK Corporation A multilayer hybrid circuit
EP0451500A2 (en) * 1990-04-09 1991-10-16 International Business Machines Corporation Printed circuit boards and cards having buried thin film capacitors and processing techniques for fabricating said boards and cards
US8359740B2 (en) 2008-12-19 2013-01-29 3D Plus Process for the wafer-scale fabrication of electronic modules for surface mounting

Citations (1)

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Publication number Priority date Publication date Assignee Title
GB1245710A (en) * 1968-12-25 1971-09-08 Hitachi Ltd Case for containing a semiconductor element

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1245710A (en) * 1968-12-25 1971-09-08 Hitachi Ltd Case for containing a semiconductor element

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* Cited by examiner, † Cited by third party
Title
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EXBK/81 *

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2587844A1 (en) * 1985-09-20 1987-03-27 Thomson Csf HYPERFREQUENCY CIRCUIT WITH LOW CAPACITY PARASITES
EP0216699A1 (en) * 1985-09-20 1987-04-01 Thomson-Csf Hyperfrequency circuit with a low parasitic capacitance
US4792773A (en) * 1985-09-20 1988-12-20 Thomson-Csf Ultra high frequency circuit with low parasite capacities
EP0379404A2 (en) * 1989-01-14 1990-07-25 TDK Corporation A multilayer hybrid circuit
EP0379404A3 (en) * 1989-01-14 1993-03-31 TDK Corporation A multilayer hybrid circuit
EP0451500A2 (en) * 1990-04-09 1991-10-16 International Business Machines Corporation Printed circuit boards and cards having buried thin film capacitors and processing techniques for fabricating said boards and cards
EP0451500A3 (en) * 1990-04-09 1995-02-08 Ibm
US8359740B2 (en) 2008-12-19 2013-01-29 3D Plus Process for the wafer-scale fabrication of electronic modules for surface mounting

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