FR2482818A1 - MULTI-LAYER CERAMIC INTEGRATED CIRCUIT AND ITS MANUFACTURING METHOD - Google Patents

MULTI-LAYER CERAMIC INTEGRATED CIRCUIT AND ITS MANUFACTURING METHOD Download PDF

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Publication number
FR2482818A1
FR2482818A1 FR8108451A FR8108451A FR2482818A1 FR 2482818 A1 FR2482818 A1 FR 2482818A1 FR 8108451 A FR8108451 A FR 8108451A FR 8108451 A FR8108451 A FR 8108451A FR 2482818 A1 FR2482818 A1 FR 2482818A1
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Prior art keywords
chips
layers
conductive
blades
ceramic package
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FR8108451A
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French (fr)
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FR2482818B1 (en
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Shawki S Ibrahim
James E Elsner
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CTS Corp
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CTS Corp
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    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
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  • Production Of Multi-Layered Print Wiring Board (AREA)
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Abstract

UN CIRCUIT INTEGRE, DESTINE A ETRE FIXE SUR UNE CARTE DE CIRCUITS IMPRIMES 24, COMPREND PLUSIEURS COUCHES SUPERPOSEES 12, 14, 18 ET AU MOINS UN CHIPS 40 MONTE SUR LA COUCHE INTERMEDIAIRE 14, A L'INTERIEUR D'UNE OUVERTURE DE LA COUCHE SUPERIEURE 18. DES FILS 42 RELIENT LE CHIPS 40 A DES BORNES 46 ALTERNEES SUR CERTAINES DES COUCHES 12, 14, 18. CES BORNES 46 SONT RELIEES A DES MOTIFS CONDUCTEURS IMPRIMES SUR CES COUCHES 12, 14, 18 ET RELIES DE COUCHE A COUCHE PAR DES CONNEXIONS EN BORDURE 34 OU EN TUNNEL 32.AN INTEGRATED CIRCUIT, INTENDED TO BE FIXED ON A BOARD OF PRINTED CIRCUITS 24, INCLUDES SEVERAL LAYERS LAYERED 12, 14, 18 AND AT LEAST ONE CHIPS 40 MOUNTED ON THE INTERMEDIATE LAYER 14, WITHIN AN OPENING OF THE TOP LAYER 18. WIRES 42 CONNECT THE CHIPS 40 TO TERMINALS 46 ALTERNATE ON SOME OF THE LAYERS 12, 14, 18. THESE TERMINALS 46 ARE CONNECTED TO CONDUCTIVE PATTERNS PRINTED ON THESE LAYERS 12, 14, 18 AND CONNECTED FROM LAYER TO LAYER EDGE 34 OR TUNNEL 32 CONNECTIONS.

Description

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I En incorporant à des paquets ou empilages'1, I By incorporating into packages or stacks'1,

des chips ou groupes de chips à interconnexions, les liai- chips or groups of chips with interconnections, the links

sons à fi.1 provenant des chips ou groupes de chips, en particulier lorsqu'il y a une forte densité de composants ou lorsque les plages de liaison portées par les chips  sounds at fi. 1 coming from chips or groups of chips, especially when there is a high density of components or when the bonding areas carried by the chips

sont très rapprochées les unes des autres, sont excessive-  are very close to each other, are excessive-

ment encombrées si bien qu'il existe un réel danger pour que les liaisons à fil viennent en contact trop près les unes des autres et présentent de sérieuses difficultés pour maintenir l'écartement requis entre fils et  congested so that there is a real danger that the wire connections come into contact too close to each other and present serious difficulties in maintaining the required spacing between wires and

plages de liaison. Ceci est dû au fait que les motifs con- bonding ranges. This is because the patterns con-

ducteurs convergent vers les chips à partir des motifs ductors converge on the chips from the patterns

métallisés imprimés qui sont prévus sur la plaquette cé- printed metallics which are provided on the plate

ramique unique. Il en résulte un encombrement excessif des conducteurs ou liaisons à fil. Cependant, dans la fabrication des circuits à chips multiples, la tendance actuelle est d'aboutir à une densité de composants encore plus grande, les motifs conducteurs du paquet céramique  unique branch. This results in excessive congestion of conductors or wire connections. However, in the manufacture of circuits with multiple chips, the current trend is to lead to an even higher density of components, the conductive patterns of the ceramic package.

devant être reliés par fils aux chips du groupe de chips. to be connected by wire to the chips of the group of chips.

Par conséquent, la tendance actuelle de la technologie,qui est d'atteindre une densité toujours plus grande de composants,soulève de délicats problèmes qui n'ont pas encore trouvé de solutions et qui sont de réaliser les bornes de sortie nécessaires, sur des circuits intégrés à haute intégration ou intégration à grande échelle(désignés souvent par les techniciens français par les initiales LSI de l'appellation en langue anglaise de la catégorie de ces circuits, c'est-à-dire Large Scale Integration), pour relier par fils les composants aux motifs conducteurs métallisés tout en maintenant,entre les liaisons à fil des broches, un écart standard, imposé par l'industrie, qui est de 0,25 mm. Consequently, the current trend in technology, which is to achieve an ever greater density of components, raises delicate problems which have not yet found solutions and which are to produce the necessary output terminals, on circuits. high-integration or large-scale integration (often designated by French technicians by the initials LSI in the English language designation of the category of these circuits, i.e. Large Scale Integration), to connect by wires components with metallic conductive patterns while maintaining, between the wire connections of the pins, a standard deviation, imposed by the industry, which is 0.25 mm.

L'un des buts principaux de la présente in-  One of the main purposes of this in-

vention est de réaliser un support de chips multicouche, à forte densité de composants, dans lequel des fils de liaison sont reliés à un seul chips ou à des chips reliés entre eux dans un groupe de chips, les liaisons à fils étant disposées pour constituer des bornes de sortie en l  vention is to provide a multilayer chip carrier, with a high density of components, in which connecting wires are connected to a single chip or to chips linked together in a group of chips, the wire connections being arranged to constitute output terminals in l

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des couches ou niveaux qui diffèrent de façon alternée dans le paquet céramique, ce qui attribue un plus grand  layers or levels which alternate alternately in the ceramic package, which gives a greater

espacement aux diverses liaisons à fil et plages de liai-  spacing at various wire connections and ranges of link

son à fil.his thread.

L'invention a également pour but de fournir un groupe de chips interconnectés, disposé dans une cavité d'un paquet céramique multicouche, dans lequel les liaisons à fil sont fixées successivement, par une extrémité, au groupe de chips et, par l'autre extrémité, à des niveaux . 0 différents du paquet céramique multicouche. Les niveaux Another object of the invention is to provide a group of interconnected chips, placed in a cavity of a multilayer ceramic package, in which the wire connections are successively fixed, at one end, to the group of chips and, at the other end, at levels. 0 different from the multilayer ceramic package. Levels

respectifs du paquet céramique sont individuellement mé-  of the ceramic package are individually mixed

tallisés pour former un motif conducteur particulier ?t de tels motifs sont connectés par l'intermédiaire de l'une metallized to form a particular conductive pattern and such patterns are connected via one

au moins des deux connexions métallisées sous forme d'ou- at least two metallic connections in the form of

vertures de "tunnels" percés d'une couche à l'autre et de  vertices of "tunnels" drilled from one layer to another and of

zones métallisées en bordure de façon à connecter les mo-  metallized areas at the edge so as to connect the mo-

tifs conducteurs respectifs qui aboutissent en fin de comp-  respective conductive elements which end at the end of the

te à une série de plages conductrices à la face inférieure  te to a series of conductive pads on the underside

du paquet céramique.of the ceramic package.

L'invention a encore pour but d'accroître la densité d'un groupe de chips, pour circuits intégrés à haute intégration, tout en assurant les bornes nécessaires aux liaisons à fil qui aboutissent à un tel groupe et tout en maintenant l'écartement requis de 0,25 mm et la largeur requise de 0,25 mm pour les plages métallisées destinées Another object of the invention is to increase the density of a group of chips, for highly integrated integrated circuits, while ensuring the necessary terminals for the wire links which lead to such a group and while maintaining the required spacing. 0.25 mm and the required width of 0.25 mm for the metallic areas intended

aux liaisons à fil.to wire connections.

De façon générale, l'invention a pour but de fournir un paquet céramique multicouche ayant plusieurs> couches étagées dont chacune possède un motif conducteur particulier, les motifs des différentes couches étant reliés entre eux par l'intermédiaire de trous ou tunnels métallisés  In general, the invention aims to provide a multilayer ceramic package having several> layered layers, each of which has a particular conductive pattern, the patterns of the different layers being interconnected by means of metallized holes or tunnels.

et/ou de zones métallisées en bordure. Diverses bornes,pro-  and / or metallized areas on the edge. Various terminals, pro-

venant d'un groupe de chips interconnectés qui est placé dans une cavité centrale, sont reliées par des liaisons à  coming from a group of interconnected chips which is placed in a central cavity, are connected by links to

fil à ces motifs, tout en maintenant des écartements ap- thread to these patterns, while maintaining spacings ap-

propriés les unes par rapport aux autres. properties relative to each other.

D'autres caractéristiques et buts de la pré-  Other features and goals of the pre-

sente invention apparaîtront à la lecture du complément de sente invention will appear on reading the complement of

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description qui suit et qui fait référence aux dessins  description which follows and which refers to the drawings

annexés, lesquels illustrent à titre d'exemple, sans au-  attached, which illustrate by way of example, without

cun caractère restrictif, un mode de réalisation particu-  cun restrictive, a particular embodiment

lier de l'invention.link of the invention.

éclatée La figure 1 illustre, par une vue en perspec-  exploded view Figure 1 illustrates, in a perspective view

tive/,le paquet céramique multicouche avec,à sa partie in- tive /, the multilayer ceramic package with, in its part

férieure, une carte à circuits imprimés et, à son extrémité supérieure, une combinaison de cadre et de couvercle qui,  a printed circuit board and, at its upper end, a combination of frame and cover which,

dans le paquet céramique, vient obturer une cavité inté-  in the ceramic package, closes an internal cavity

rieure destinée à recevoir un groupe de chips.  for receiving a group of crisps.

La figure 2 montre, par une vue en perspective à plus grande échelle, le paquet céramique multicouche dont  FIG. 2 shows, in a perspective view on a larger scale, the multilayer ceramic package of which

le cadre et le couvercle ont été enlevés. the frame and cover have been removed.

La figure 3 est une coupe, selon la ligne 3-3 de  Figure 3 is a section along line 3-3 of

de la figure 2, montrant les bordures métallisées, les tun-  in Figure 2, showing the metallic borders, the tun-

nels métallisés et les connexions par liaisons à fil et par motifs métallisés entre le groupe de chips et les divers metallized nels and connections by wire links and metallized patterns between the group of chips and the various

niveaux du paquet céramique multicouche.  levels of the multilayer ceramic package.

La figure 4 montre la face inférieure de la couche de base du paquet céramique qui est à monter sur  Figure 4 shows the underside of the base layer of the ceramic package which is to be mounted on

la carte métallisée.the metallic card.

La figure 4a montre la face supérieure de la couche de base du paquet céramique, c'est-à-dire la face  Figure 4a shows the upper side of the base layer of the ceramic package, i.e. the side

opposée à celle qui est visible à'la figure 4.  opposite to that which is visible in FIG. 4.

La figure 5 montre, en perspective à plus grande échelle, les fils reliant, par leurs extrémités respectives, le groupe de chips aux couches appropriées du paquet céramique, avec une liaison en boule à l'une des extrémités de ces fils et une liaison en coin à l'autre  Figure 5 shows, in perspective on a larger scale, the wires connecting, by their respective ends, the group of chips to the appropriate layers of the ceramic package, with a ball connection at one end of these wires and a connection in corner to corner

extrémité.end.

Si l'on se reporte à la figure 1, on y a If we refer to Figure 1, there are

désigné par 10 dans son ensemble un paquet céramique mul-  designated by 10 as a whole a multi-ceramic package

ticouche qui comprend plusieurs couches ou lames de subs- ticouche which comprises several layers or strips of

trat céramique, savoir une couche de base 12, une couche intermédiaire 14 sur laquelle est monté un groupe d e chips reliés entre eux 16, une couche supérieure ajourée 18,. une ceramic trat, namely a base layer 12, an intermediate layer 14 on which is mounted a group of connected chips 16, an openwork upper layer 18,. a

couche-cadre 20 et une couche-couvercle 22. Le paquet céra- frame layer 20 and a cover layer 22. The packet will

mique multicouche 10 est monté en bloc sur une carte métal- multilayer mique 10 is assembled in block on a metal card-

lisée 24.read 24.

La couche de base 12, la couche intermédiaire 14 et la couche supérieure 18 possèdent chacune un motif conducteur imprimé qui est indiqué en 26 sur la couche de base 12, en 28 sur la couche intermédiaire 14 et en 30 sur la couche supérieure 18. Le motif particulier de ces zones métallisées conductrices ne fait pas partie de la présente invention. Cependant, il est envisagé de former sur les substrats céramiques, avantcuisson ou frittage de ceux-ci  The base layer 12, the intermediate layer 14 and the upper layer 18 each have a printed conductive pattern which is indicated at 26 on the base layer 12, at 28 on the intermediate layer 14 and at 30 on the upper layer 18. The particular pattern of these conductive metallized areas is not part of the present invention. However, it is envisaged to form on the ceramic substrates, pre-firing or sintering thereof

et assemblage, les motifs conducteurs qui sont alors adap- and assembly, the conductive patterns which are then adapted

tés mutuellement et reliés électriquement par des conne- mutually and electrically connected by connectors

xions aboutissant finalement à des plages 33 sur la face inférieure 31 (figure 4) de la couche de base 12 afin xions finally leading to areas 33 on the underside 31 (FIG. 4) of the base layer 12 so

de coopérer avec la carte métallisée 24.  to cooperate with the metallic card 24.

Entre couches voisines, les motifs conducteurs cas  Between neighboring layers, the case conductive patterns

sont reliés les uns aux autres, dans certains/,par l'inter- are connected to each other, in some /, through the

médiaire de "tunnels" 32 (figures 3 et 4a) qui sont formés de trous verticaux, traversant de part en part l'une-des  median of "tunnels" 32 (FIGS. 3 and 4a) which are formed by vertical holes, crossing right through one of the

couches 12, 14 et 18 et remplis de métal ou alliage métal-  layers 12, 14 and 18 and filled with metal or metal alloy-

lique. Dans d'autres cas, les motifs des différentes cou-  lique. In other cases, the patterns of the different colors

ches sont reliés entre eux par l'intermédiaire de zones  ches are connected to each other through zones

métallisées en bordure 34 (figures 3 et 4a). metallized at the edge 34 (Figures 3 and 4a).

Le groupe de chips 16 est constitué de chips pour circuits intégrés à haute intégration, convenablement reliés entre eux. Ces chips sont reliés par des circuits imprimés par métallisation sur la surface en regard de la  The chip group 16 is made up of chips for highly integrated circuits, suitably connected together. These chips are connected by printed circuits by metallization on the surface facing the

couche intermédiaire 14, ces circuits imprimés étant dési-  intermediate layer 14, these printed circuits being

gnés par 36 à la figure 1.indicated by 36 in Figure 1.

Pour établir des liaisons à fil entre chips et afin d'éliminer la nécessité de les faire passer d'abord  To establish wire connections between chips and to eliminate the need to pass them first

d'un chips vers l'extérieur jusqu'à la périphérie du pa-  a crisps outwards to the periphery of the pa-

quet 10, puis en sens inverse jusqu'à un autre chips, il peut y avoir une liaison à fil d'un chips à l'autre par l'intermédiaire de plages de raccordement 38 (figures 1 et 2) disposées entre les chips 40 et séparant ceux-ci. De quet 10, then in the opposite direction to another chip, there may be a wire connection from one chips to the other via connection pads 38 (FIGS. 1 and 2) disposed between the chips 40 and separating these. Of

telles liaisons à fil court sont désignées dans leur en-  such short wire connections are designated in their

semble par 42 aux figures 2 et 3. Il existe ainsi les interconnexions nécessaires pour constituer un groupe de chips à interconnexions de forte densité qui possède appears by 42 in FIGS. 2 and 3. There thus exist the interconnections necessary to constitute a group of chips with high density interconnections which has

des bornes de sortie vers les motifs conducteurs des dif-  output terminals to the conductive patterns of the diff

férentes couches appartenant au paquet céramique multi- different layers belonging to the multi-ceramic package

couche. En raison de la forte densité de composants qui vient d'être évoquée, il est difficile de maintenir l'écartement de 0,25 mm qui est nécessaire pour les motifs conducteurs. Conformément à l'invention, ceci est résolu layer. Due to the high density of components which has just been mentioned, it is difficult to maintain the 0.25 mm spacing which is necessary for the conductive patterns. According to the invention, this is resolved

de la manière illustrée aux figures 2 et 3. Comme le mon-  as illustrated in Figures 2 and 3. As shown in Figure

trent ces figures, les liaisons à fil 42 convergent sur le groupe de chips 16 en étant reliées, par l'une de leurs extrémités,à l'aide d'une liaison en boule 44 (figure 5) à l'un des chips 40 et, par l'autre de leurs extrémités, à l'aide d'une liaison en coin 46 à un motif conducteur de l'une ou l'autre de la couche intermédiaire 14 et de la couche-cadre 18. Malgré la forte densité des composants ou chips LSI et des liaisons à fil, on maintient néanmoins In these figures, the wire connections 42 converge on the group of chips 16 while being connected, by one of their ends, using a ball connection 44 (FIG. 5) to one of the chips 40 and, by the other of their ends, using a wedge connection 46 to a conductive pattern of one or the other of the intermediate layer 14 and of the framework layer 18. Despite the high density LSI components or chips and wire links, we nevertheless maintain

l'écartement de 0,25 mm sur les motifs conducteurs en al- 0.25 mm spacing on the conductive patterns in al-

ternant les couches 14 et 18.tarnishing layers 14 and 18.

Bien entendu, il est possible de faire alter-  Of course, it is possible to alternate

ner plus de deux couches; c'est ainsi que l'on peut envi-  more than two layers; that's how we can envi-

sager trois ou quatre couches, ou même davantage, pour éta-  sager three or four layers, or even more, to lay

blir les liaisons alternés à fil. L'idée générale est tou-  blir the alternate wire connections. The general idea is always

tefois qu'en établissant les liaisons à fil entre le groupe  However, by establishing wire connections between the group

de chips à forte densité, placé au centre, et divers ni- high density crisps, placed in the center, and various

veaux alternés des couches métallisées, on peut augmenter le nombre des liaisons à fil et obtenir la densité voulue des composants placés au centre sans compromettre en rien alternating calves of metallized layers, we can increase the number of wire connections and obtain the desired density of the components placed in the center without compromising in any way

l'écartement nécessaire de 0,25 mm pour les motifs conduc- 0.25 mm spacing required for conductive patterns

teurs.teurs.

Les liaisons à fil, réalisées entre le groupe central et les motifs conducteurs situés aux différents niveaux, assurent des connexions appropriées de couche à couche de la façon décrite, par l'intermédiaire soit des tunnels métallisés 32, soit des métallisations en bordure 34 (figures 3 et 4a); toutes ces zones métallisées 32, 34 aboutissent en fin de compte à la couche de base 12 et aux plages conductrices inférieures 33 qui sont à leur tour reliées à des endroits appropriés d'une carte métallisée The wire connections, made between the central group and the conductive patterns located at the different levels, ensure appropriate layer-to-layer connections in the manner described, either through metallized tunnels 32 or metallization at the edge 34 (figures 3 and 4a); all of these metallized zones 32, 34 ultimately lead to the base layer 12 and to the lower conductive pads 33 which are in turn connected to suitable locations on a metallized card

sous-jacente 24. De façon typique, les couches ou plaquet- underlying 24. Typically, the layers or pad-

tes peuvent être faites de silicate d'aluminium ou d'au-  your can be made of aluminum silicate or other

tres constituants de substrat inertes qui, comme indiqué ci-dessus, n'ont pas encore été cuits au moment o l'on forme sur ceux-ci les métallisations, tunnels 32 et zones  very inert substrate constituents which, as indicated above, have not yet been baked at the time when the metallizations, tunnels 32 and zones are formed thereon

métallisées en bordure 34.metallic border 34.

On place la couche-couvercle 22 au-dessus des 26 28 ou JO  The cover layer 22 is placed above the 26 28 or OJ

couches 12, 14, 18 portant un motif conducteur/,de la cou- layers 12, 14, 18 carrying a conductive pattern /, of the

che-cadre 20 et/groupe de chips 16, une fois que ce groupe est fixé et que les liaisons à fil 42 ont été établies avec le groupe de chips placé au centre. On procède ensuite à la cuisson ou frittage (scellement) de la totalité de l'empilage ou paquet et on monte le produit final sur la carte métallisée 24. Les diverses couches ayant été faites chacune par compression de particules céramiques, on soumet ces couches à une cuisson simultanée de façon à fritter  che-frame 20 and / group of chips 16, once this group is fixed and that the wire connections 42 have been established with the group of chips placed in the center. Next, the entire stack or package is cooked or sintered (sealed) and the final product is mounted on the metallized card 24. The various layers having each been made by compression of ceramic particles, these layers are subjected to simultaneous cooking so as to sinter

les particules et à lier les diverses couches ensemble. the particles and to bind the various layers together.

A cet effet, on commence par monter le groupe de chips 16 sur la couche intermédiaire 14 et par relier To this end, we start by mounting the group of chips 16 on the intermediate layer 14 and connecting

entre eux les diverses chips 40 de ce groupe 16 par l'in-  between them the various chips 40 of this group 16 by the

termédiaire des plages conductrices prévues sur la face supérieure de la couche intermédiaire 14, et sur d'autres intermediate of the conductive pads provided on the upper face of the intermediate layer 14, and on other

couches en fonction des besoins.layers as needed.

Le groupe de chips 16 possède des liaisons  Chip group 16 has links

à fil 42 avec les motifs conducteurs réalisés par métal-  42 with conductive patterns made by metal-

lisation des substrats céramiques, ces liaisons étant ob-  ceramic substrates, these bonds being ob-

tenues en fixant les extrémités des fils de liaison de telle sorte que les liaisons à fil voisines passent du  held by fixing the ends of the connecting wires so that the neighboring wire connections pass from the

groupe de chips 16 à des niveaux alternés du paquet céra-  group of chips 16 at alternate levels of the cereal package

mique multicouche.multilayer mique.

On monte ensuite en bloc le paquet sur la We then mount the package as a whole on the

carte métallisée 24 de façon telle que les plages conduc- metallic card 24 in such a way that the conductive areas

trices 33 situées à la surface extérieure du paquet soient montées sur les diverses bornes de la carte métallisée  33 located on the outer surface of the package are mounted on the various terminals of the metallic card

qui possède une architecture et une composition prédéter-  which has a predeter architecture and composition

mi-nées de circuit imprimé.printed circuit boards.

Il doit être bien entendu que n'importe quel  It should be understood that any

24BUZ1924BUZ19

motif ou dessin conducteur peut être appliqué à l'aide de  conductive pattern or design can be applied using

masques ou par sérigraphie à la surface des diverses cou-  masks or by screen printing on the surface of the various layers

ches du paquet céramique multicouche et que les motifs con-  of the multilayer ceramic package and that the patterns

ducteurs en tant que tels, c'est-à-dire l'architecture par-  ductors as such, that is to say architecture

ticulière ou le motif en lui-même, ne font pas partie de particular or the motif itself, are not part of

la présente invention.the present invention.

Il convient en outre de souligner que,selon l'invention,l'écartement de 0, 25 mm peut être obtenu grâce au fait que l'on relie d'abord à un premier niveau l'un des fils provenant du groupe de chips et que l'on alterne ensuite les liaisons à fil avec un deuxième niveau, un troisième niveau, u nquatrième niveau etc..., ce qui fournit le moyen de maintenir les motifs conducteurs à un écartement It should also be emphasized that, according to the invention, the spacing of 0.25 mm can be obtained by virtue of the fact that one of the wires coming from the group of chips is first connected to a first level. that we then alternate the wire connections with a second level, a third level, a fourth level etc ..., which provides the means of maintaining the conductive patterns at a spacing

de 0,25 mm malgré l'augmentation de la densité des compo- 0.25 mm despite the increased density of the components

sants et malgré la convergence de tels fils vers le centre.  healthy and despite the convergence of such threads towards the center.

Bien évidemment, si l'écartement de 0,25 mm n'est pas con- Obviously, if the 0.25 mm gap is not con-

servé en tant que norme industrielle, il est aussi possible d'obtenir une densité de composants encore plus élevée, si l'on s'accorde sur un écartement de moins de 0,25 mm et/ou sur une largeur de plages conductrices inférieure used as an industry standard, it is also possible to obtain an even higher density of components, if we agree on a spacing of less than 0.25 mm and / or on a width of less conductive pads

à 0,25 mm.at 0.25 mm.

Dans tous les cas, l'invention procure la pos- In all cases, the invention provides the pos-

sibilité d'une densité de composants maximale compatible avec le maintien d'un écartement de 0,25 mm mais elle est également applicable quelle que soit la densité souhaitée  sensitivity of a maximum component density compatible with maintaining a spacing of 0.25 mm, but it is also applicable whatever the desired density

pour les composants tout en réalisant une densité intrinsè-  for the components while achieving an intrinsic density

quement plus grande pour les diverses liaisons à fil. slightly larger for the various wire connections.

Bien que l'invention ait été illustrée et décrite en rapport avec un seul mode de réalisation, il va de soi que celui-ci sert essentiellement à illustrer ltinvention sans aucun caractère restrictif. Par exemple, au lieu d'utiliser un paquet céramique multicouche à trois couches céramiques, il est possible d'en utiliser quatre,  Although the invention has been illustrated and described in relation to a single embodiment, it goes without saying that this essentially serves to illustrate the invention without any restrictive character. For example, instead of using a multilayer ceramic package with three ceramic layers, it is possible to use four,

cinq ou tout autre nombre permettant de constituer la com- five or any other number to constitute the com-

binaison souhaitée d'écartement des fils, de superposition des couches et des divers agencements de circuits imprimés aussi bien que d'architecture pour les groupes de chips à interconnexions. Toutes ces variantes sont considérées desired combination of wire spacing, superposition of layers and various arrangements of printed circuits as well as architecture for groups of chips with interconnections. All these variants are considered

comme faisant partie de la présente invention.  as part of the present invention.

Claims (12)

REVENDICATIONS l. Procédé pour fabriquer un support de chips multicouche, à forte densité de composants, caractérisé en ce qu'il comprend les étapes consistant à former une l. Method for manufacturing a multilayer chip carrier, with a high density of components, characterized in that it comprises the steps consisting in forming a première couche (14) de supportde chipsdestinée à rece- first layer (14) of chip support intended to receive voir au moins un chips (40), et au moins une couche sup-  see at least one chips (40), and at least one top layer pim.entaire (18, 20); à former des bornes de liaison avec  pim.entaire (18, 20); to form connecting terminals with ce chips (40); à former des pistes conductrices métalli-  this chips (40); to form metallic conductive tracks sées (26, 24, 30) sur lesdites couches (14, 18, 20); et 1-0 form=-,entre ce chips (40) et des pistes conductrices décalées mutuellement sur ces couches (14, 18, 20), des liaisons à fil (42) qui alternent entre les différents  seeds (26, 24, 30) on said layers (14, 18, 20); and 1-0 form = -, between this chips (40) and conductive tracks offset mutually on these layers (14, 18, 20), wire connections (42) which alternate between the different niveaux desdites couches (14, 18, 20).  levels of said layers (14, 18, 20). 2. Procédé selon la revendication 1, carac-  2. Method according to claim 1, charac- térisé en ce qu'il comprend les étapes consistant à cons- terized in that it includes the steps of cons- tituer chacune des susdites couches (14, 18, 20) par com-  titrate each of the above layers (14, 18, 20) by ceramlquesceramics pression de particules/et a soumettre les couches de par- particle pressure / and to subject the layers of par- ticules céramiques ainsi comprimées à une cuisson simulta-  ceramic tiles thus compressed when fired simultaneously née de façon à fritter les particules et à lier ensemble  born in order to sinter the particles and to bind together ces diverses couches.these various layers. 3. Procédé selon la revendication 1, carac-  3. Method according to claim 1, charac- térisé en ce qu'il comprend l'étape consistant à placer  in that it includes the step of placing une couche-cadre (20) et une couche-couvercle (22> à l'ex-  a framework layer (20) and a cover layer (22> ex- trémité supérieure de l'empilage des susdites couches (14, upper end of the stack of the above layers (14, 18, 20) et à ménager, sur la face inférieure (31)'du sup- 18, 20) and to spare, on the underside (31) 'of the sup- port multicouche, plusieurs plages conductrices (33) des- multi-layer port, several conductive pads (33) of the tinées à servir de sorties vers une carte métallisée (24).  designed to serve as outputs to a metallic card (24). 4. Procédé selon la revendication 1, carac- 4. Method according to claim 1, charac- térisé en ce qu'il comprend les étapes consistant à former  terized in that it includes the steps of forming plusieurs plages de raccordement (38) sur celle des cou-  several connection pads (38) on that of the couplings ches (14) qui est destinée à recevoir des chips (40) et effectuer de courtes liaisons à fil entre les chips ches (14) which is intended to receive chips (40) and make short wire connections between the chips (40) par l'intermédiaire de ces plages de raccordement (38).  (40) via these connection pads (38). 5. Procédé selon la revendication 1, caracté-  5. Method according to claim 1, character- risé en ce qu'il comprend l'étape consistant à sceller, à l'intérieur dudit support, une cavité dans laquelle le  laughed at in that it includes the step of sealing, inside said support, a cavity in which the chips (40) a été monté.chips (40) has been fitted. 6. Procédé selon la revendication 1, carac-  6. Method according to claim 1, charac- c térisé en ce qu'il comprend l'étape constituant à disposer les liaisons à fil (42) entre le chips (40) et les pistes métallisées (26, 28, 30) desdites couches (14, 18, 20) et à alterner les liaisons ' plusieurs niveaux entre ce chips (40) et ces couches (14, 13, 20) de façon qu'elles inté- ressent au moins deux couches alternées du support de  c terized in that it comprises the step of placing the wire connections (42) between the chips (40) and the metallized tracks (26, 28, 30) of said layers (14, 18, 20) and alternating the multi-level connections between this chips (40) and these layers (14, 13, 20) so that they involve at least two alternating layers of the support chips multicouche.multilayer chips. 7. Paquet céramique multicouche à plusieurs lames (14, 18, 20) séparées dont une lame intermédiaire  7. Multilayer ceramic package with several separate blades (14, 18, 20) including an intermediate blade (14) destinée à recevoir un groupe de chips (16), carac-  (14) intended to receive a group of chips (16), charac- térisé en ce qu'il comprend au moins un chips (40) disposé sur cette lame intermédiaire (14); des motifs conducteurs  terized in that it comprises at least one chips (40) disposed on this intermediate blade (14); conductive patterns (26, 287 30) sur chacune de ces lames (14, 18, 20), cer-  (26, 287 30) on each of these blades (14, 18, 20), certain tainsde ces motifs conducteurs étant munis de bornes à fil (46); des moyens conducteurs métallisées (32, 34) reliant entre eux les motifs conducteurs (26, 28, 30) des diverses lames superposées (14, 18, 20); et des liaisons à fil (42) all of these conductive patterns being provided with wire terminals (46); metallized conductive means (32, 34) connecting together the conductive patterns (26, 28, 30) of the various superimposed blades (14, 18, 20); and wire connections (42) assurant un écartement d'au moins 0,25 mm entre les sus-  ensuring a gap of at least 0.25 mm between the dites bornes (46) du fait qu'elles s'étendent entre ledit chips (40), par une de leurs extrémités, et des niveaux alternés des lames (14, 18, 20), par leur autre extrémité, afin d'assurer des liaisons électriques entre ledit chips  said terminals (46) because they extend between said chips (40), by one of their ends, and alternate levels of the blades (14, 18, 20), by their other end, in order to ensure electrical connections between said chips (40) et les motifs conducteurs (26, 28, 30).  (40) and the conductive patterns (26, 28, 30). 8. Paquet céramique multicouche selon la re-  8. Multilayer ceramic package according to re- vendication 7, caractérisé en ce que les moyens conducteurs (32, 34) comprennent des tunnels emplis de métal (32), qui forment des chemins conducteurs entre les motifs conducteurs (26, 28, 30) portés par les faces respectives de lames (14, 18, 20) choisies parmi celles qui constituent le paquet céramique (10), et des chemins conducteurs (34) métallisés en bordure, qui relient entre eux les motifs conducteurs  vendication 7, characterized in that the conductive means (32, 34) comprise metal-filled tunnels (32), which form conductive paths between the conductive patterns (26, 28, 30) carried by the respective faces of the blades (14 , 18, 20) chosen from those which constitute the ceramic package (10), and conductive paths (34) metallized at the edge, which connect the conductive patterns to each other (26> 28, 30) portés par d'autres lames céramiques du sup- (26> 28, 30) carried by other ceramic blades of the sup- port (10), ce grâce à quoi les motifs conducteurs de ces lames sont reliés électriquement ensemble et audit chips port (10), whereby the conductive patterns of these blades are electrically connected together and to said chips (40).(40). 9. Paquet céramique multicouche selon la re-  9. Multilayer ceramic package according to re- vendication 7, caractérisé en ce qu'il comprend des moyens formant des plages de raccordement (38) à celui des niveaux du paquet céramique ('10) c est disposé le groupe de chips (16) ainsi que de courtes liaisons à fil avec ces plages de raccordement (35), ce qui fournit un réseau conducteur entre les chips (40) dudit groupe (16), ce paquet céramique multicouche (10) étant adapté à une forte densité de com- posants.  vendication 7, characterized in that it comprises means forming connection pads (38) to that of the levels of the ceramic package ('10) c is arranged the group of chips (16) as well as short wire connections with these connection pads (35), which provides a conductive network between the chips (40) of said group (16), this multilayer ceramic package (10) being adapted to a high density of components. 10. Paquet céramique multicouche selon la10. Multilayer ceramic package according to revendication 7, caractérisé en ce qu'il comprend des mo-  claim 7, characterized in that it comprises mo- yens pour y former une cavité intérieure, la lame intermé- yen to form an interior cavity, the intermediate blade diaire (14) comprenant à l'intérieur de cette cavité des plages de raccordement (38) servant à relier entre eux diary (14) comprising inside this cavity connecting pads (38) used to connect them les chips (40) du groupe de chips (16).  the chips (40) of the group of chips (16). 11. Paquet céramique multicouche selon la re-  11. Multilayer ceramic package according to re- vendication 7, caractérisé en ce que les lames (12, 14, 18) sont faites de couches comprimées de particules céramiques qui sont ensuite soumises à une cuisson pour développer vendication 7, characterized in that the blades (12, 14, 18) are made of compressed layers of ceramic particles which are then fired to develop d- liaisons de couche à couche, entre les surfaces en con- d- layer-to-layer connections, between the surfaces in contact tact des diverses lames céramiques. tact of the various ceramic blades. 12. Paquet céramique multicouche selon la 12. Multilayer ceramic package according to revendication 10, caractérisé en ce qu'il comprend un grou-  claim 10, characterized in that it comprises a group pe de chips (16) à forte densité de composants; une cavité intérieure pour recevoir ce groupe de chips (16) à forte densité de composants; des moyens pour former des liaisons mutuelles avec ces chips (40) et bornes à fil (46), entre le groupe de chips (16) et des niveaux alternés de motifs conducteurs (26, 28, 30) formés sur les diverses lames  eg chips (16) with a high density of components; an interior cavity for receiving this group of chips (16) with a high density of components; means for forming mutual links with these chips (40) and wire terminals (46), between the group of chips (16) and alternating levels of conductive patterns (26, 28, 30) formed on the various blades céramiques à plusieurs niveaux, de façon à former un boî- multi-level ceramics, so as to form a box tier céramique muticouche pour ledit paquet céramique mul-  multilayer ceramic tier for said multi-ceramic package ticouche (10).three-layer (10).
FR8108451A 1980-05-15 1981-04-28 MULTI-LAYER CERAMIC INTEGRATED CIRCUIT AND ITS MANUFACTURING METHOD Expired FR2482818B1 (en)

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GB2077036A (en) 1981-12-09
US4320438A (en) 1982-03-16
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CA1154541A (en) 1983-09-27

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