FR2454242A1 - TDM switching circuit - has control and buffer memory in which address depends on same contents of memory - Google Patents
TDM switching circuit - has control and buffer memory in which address depends on same contents of memoryInfo
- Publication number
- FR2454242A1 FR2454242A1 FR7836373A FR7836373A FR2454242A1 FR 2454242 A1 FR2454242 A1 FR 2454242A1 FR 7836373 A FR7836373 A FR 7836373A FR 7836373 A FR7836373 A FR 7836373A FR 2454242 A1 FR2454242 A1 FR 2454242A1
- Authority
- FR
- France
- Prior art keywords
- super
- multiplex
- memory
- route
- outgoing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Time-Division Multiplex Systems (AREA)
Abstract
A TDM switching circuit comprises a number of incoming multiplex routes converted in a super-multiplexer into an incoming super-multiplex route, an outgoing super-multiplex route converted by a super-demultiplexer into a number of outgoing multiplex routes, and a buffer memory whose write input is connected to the incoming super-multiplex route and whose read output is connected to the outgoing super-multiplex route. The words present in the time gaps of the incoming super-multiplex route are written sequentially in the information memory of the buffer memory. The buffer memory is addressable by its content and has a circular memory aassociated with the information memory locations in addition to a fixed address memory addressing the components of the outgoing super-multiplex route, and comparators associated with respective information memory locations and address memory locations. Each comparator compares the arbitrary addresses written in the address memory locations with the fixed address of the component routes of the outgoing super-multiplex route and controls the reading of the word associated with the arbitrary address when identity occurs.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR7836373A FR2454242B1 (en) | 1978-12-26 | 1978-12-26 | TIME DIVISION MULTIPLEX SWITCHING NETWORK IN WHICH THE BUFFER MEMORY IS ASSOCIATIVE, CIRCULATED AND IN THE FORM OF A COUPLED LOAD DEVICE |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR7836373A FR2454242B1 (en) | 1978-12-26 | 1978-12-26 | TIME DIVISION MULTIPLEX SWITCHING NETWORK IN WHICH THE BUFFER MEMORY IS ASSOCIATIVE, CIRCULATED AND IN THE FORM OF A COUPLED LOAD DEVICE |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2454242A1 true FR2454242A1 (en) | 1980-11-07 |
FR2454242B1 FR2454242B1 (en) | 1986-02-14 |
Family
ID=9216531
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7836373A Expired FR2454242B1 (en) | 1978-12-26 | 1978-12-26 | TIME DIVISION MULTIPLEX SWITCHING NETWORK IN WHICH THE BUFFER MEMORY IS ASSOCIATIVE, CIRCULATED AND IN THE FORM OF A COUPLED LOAD DEVICE |
Country Status (1)
Country | Link |
---|---|
FR (1) | FR2454242B1 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2504760A1 (en) * | 1981-04-23 | 1982-10-29 | Western Electric Co | SIGNAL TRANSFER CIRCUIT |
FR2504762A1 (en) * | 1981-04-23 | 1982-10-29 | Western Electric Co | DISTRIBUTED TYPE CONFERENCING SYSTEM FOR A TELECOMMUNICATIONS NETWORK |
EP0184774A2 (en) * | 1984-12-14 | 1986-06-18 | Alcatel N.V. | Memory arrangement and a switching stage comprising a memory arrangement for the establishment of dynamic connecting routes |
FR2677201A1 (en) * | 1991-06-03 | 1992-12-04 | Alcatel Business Systems | Control configuration for a buffer memory of a time-based switch |
-
1978
- 1978-12-26 FR FR7836373A patent/FR2454242B1/en not_active Expired
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2504760A1 (en) * | 1981-04-23 | 1982-10-29 | Western Electric Co | SIGNAL TRANSFER CIRCUIT |
FR2504762A1 (en) * | 1981-04-23 | 1982-10-29 | Western Electric Co | DISTRIBUTED TYPE CONFERENCING SYSTEM FOR A TELECOMMUNICATIONS NETWORK |
EP0184774A2 (en) * | 1984-12-14 | 1986-06-18 | Alcatel N.V. | Memory arrangement and a switching stage comprising a memory arrangement for the establishment of dynamic connecting routes |
EP0184774A3 (en) * | 1984-12-14 | 1988-09-21 | Alcatel N.V. | Memory arrangement and a switching stage comprising a memory arrangement for the establishment of dynamic connecting routes |
FR2677201A1 (en) * | 1991-06-03 | 1992-12-04 | Alcatel Business Systems | Control configuration for a buffer memory of a time-based switch |
Also Published As
Publication number | Publication date |
---|---|
FR2454242B1 (en) | 1986-02-14 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |