FR2450006A1 - Programmable digital signal generator - has counter driven by clock and connected to phase authorisation device comprising memories and registers - Google Patents

Programmable digital signal generator - has counter driven by clock and connected to phase authorisation device comprising memories and registers

Info

Publication number
FR2450006A1
FR2450006A1 FR7904537A FR7904537A FR2450006A1 FR 2450006 A1 FR2450006 A1 FR 2450006A1 FR 7904537 A FR7904537 A FR 7904537A FR 7904537 A FR7904537 A FR 7904537A FR 2450006 A1 FR2450006 A1 FR 2450006A1
Authority
FR
France
Prior art keywords
clock
authorisation device
output
register
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7904537A
Other languages
French (fr)
Other versions
FR2450006B1 (en
Inventor
Gilbert Camille Guyot
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
Le Materiel Telephonique Thomson CSF
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Le Materiel Telephonique Thomson CSF filed Critical Le Materiel Telephonique Thomson CSF
Priority to FR7904537A priority Critical patent/FR2450006A1/en
Publication of FR2450006A1 publication Critical patent/FR2450006A1/en
Application granted granted Critical
Publication of FR2450006B1 publication Critical patent/FR2450006B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
    • H03K5/1502—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs programmable
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/28—Systems using multi-frequency codes with simultaneous transmission of different frequencies each representing one code element

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Pulse Circuits (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

The generator has a clock connected to the clock input of a digital counter counting downwards. The outputs of the counter are connected to a phase authorisation device comprising one or more permanent memories whose outputs are coupled via an intermediate authorisation register and an output authorisation device to the outputs of the digital signal generator. The intermediate registers receive a clock signal differing from that received by the output authorisation device. The clock input of the intermediate register is connected via an inverter and delay circuit to the output of the clock. The clock input of the output register is connected directly to the clock. The inverter and delay circuit have a delay of the same order as the response time of the intermediate register. The generator can be synchronised by an external clock signal. The circuit may be used as a multifrequency code receiver for PCM telephones.
FR7904537A 1979-02-22 1979-02-22 Programmable digital signal generator - has counter driven by clock and connected to phase authorisation device comprising memories and registers Granted FR2450006A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR7904537A FR2450006A1 (en) 1979-02-22 1979-02-22 Programmable digital signal generator - has counter driven by clock and connected to phase authorisation device comprising memories and registers

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7904537A FR2450006A1 (en) 1979-02-22 1979-02-22 Programmable digital signal generator - has counter driven by clock and connected to phase authorisation device comprising memories and registers

Publications (2)

Publication Number Publication Date
FR2450006A1 true FR2450006A1 (en) 1980-09-19
FR2450006B1 FR2450006B1 (en) 1982-08-06

Family

ID=9222322

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7904537A Granted FR2450006A1 (en) 1979-02-22 1979-02-22 Programmable digital signal generator - has counter driven by clock and connected to phase authorisation device comprising memories and registers

Country Status (1)

Country Link
FR (1) FR2450006A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0054159A2 (en) * 1980-12-15 1982-06-23 BURROUGHS CORPORATION (a Michigan corporation) Programmable timing pulse generator
US4553100A (en) * 1982-06-07 1985-11-12 Takeda Riken Co., Ltd. Counter-address memory for multi-channel timing signals
EP0168232A2 (en) * 1984-07-09 1986-01-15 Advanced Micro Devices, Inc. Apparatus for generating digital timing waveforms

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2155311A5 (en) * 1971-10-08 1973-05-18 Zellweger Uster Ag
DE2524129A1 (en) * 1974-06-03 1975-12-04 Cselt Centro Studi Lab Telecom Programmable time control for logic circuits - has counter dividing elementary clock signals and coupled to ROM

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2155311A5 (en) * 1971-10-08 1973-05-18 Zellweger Uster Ag
DE2524129A1 (en) * 1974-06-03 1975-12-04 Cselt Centro Studi Lab Telecom Programmable time control for logic circuits - has counter dividing elementary clock signals and coupled to ROM

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
EXBK/76 *
EXBK/78 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0054159A2 (en) * 1980-12-15 1982-06-23 BURROUGHS CORPORATION (a Michigan corporation) Programmable timing pulse generator
EP0054159A3 (en) * 1980-12-15 1982-07-28 BURROUGHS CORPORATION (a Michigan corporation) Programmable timing pulse generator
US4553100A (en) * 1982-06-07 1985-11-12 Takeda Riken Co., Ltd. Counter-address memory for multi-channel timing signals
EP0168232A2 (en) * 1984-07-09 1986-01-15 Advanced Micro Devices, Inc. Apparatus for generating digital timing waveforms
EP0168232A3 (en) * 1984-07-09 1988-05-25 Advanced Micro Devices, Inc. Apparatus for generating digital timing waveforms

Also Published As

Publication number Publication date
FR2450006B1 (en) 1982-08-06

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Legal Events

Date Code Title Description
ST Notification of lapse