FR2447577B1 - Dispositif de traitement de donnees comportant une pluralite de sous-processeurs. - Google Patents
Dispositif de traitement de donnees comportant une pluralite de sous-processeurs.Info
- Publication number
- FR2447577B1 FR2447577B1 FR8001507A FR8001507A FR2447577B1 FR 2447577 B1 FR2447577 B1 FR 2447577B1 FR 8001507 A FR8001507 A FR 8001507A FR 8001507 A FR8001507 A FR 8001507A FR 2447577 B1 FR2447577 B1 FR 2447577B1
- Authority
- FR
- France
- Prior art keywords
- processors
- sub
- data processing
- processing device
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4405—Initialisation of multiprocessor systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Security & Cryptography (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Hardware Redundancy (AREA)
- Multi Processors (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54007973A JPS594050B2 (ja) | 1979-01-25 | 1979-01-25 | 情報処理システム |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2447577A1 FR2447577A1 (fr) | 1980-08-22 |
FR2447577B1 true FR2447577B1 (fr) | 1986-09-26 |
Family
ID=11680395
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR8001507A Expired FR2447577B1 (fr) | 1979-01-25 | 1980-01-24 | Dispositif de traitement de donnees comportant une pluralite de sous-processeurs. |
Country Status (2)
Country | Link |
---|---|
JP (1) | JPS594050B2 (fr) |
FR (1) | FR2447577B1 (fr) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57139861A (en) * | 1981-02-25 | 1982-08-30 | Nissan Motor Co Ltd | Multicomputer system |
JPS582047U (ja) * | 1981-06-25 | 1983-01-07 | 日本電気株式会社 | 障害検出機能を有する情報処理装置 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1434186A (en) * | 1972-04-26 | 1976-05-05 | Gen Electric Co Ltd | Multiprocessor computer systems |
US3812468A (en) * | 1972-05-12 | 1974-05-21 | Burroughs Corp | Multiprocessing system having means for dynamic redesignation of unit functions |
US3806887A (en) * | 1973-01-02 | 1974-04-23 | Fte Automatic Electric Labor I | Access circuit for central processors of digital communication system |
US4038648A (en) * | 1974-06-03 | 1977-07-26 | Chesley Gilman D | Self-configurable circuit structure for achieving wafer scale integration |
-
1979
- 1979-01-25 JP JP54007973A patent/JPS594050B2/ja not_active Expired
-
1980
- 1980-01-24 FR FR8001507A patent/FR2447577B1/fr not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS5599662A (en) | 1980-07-29 |
FR2447577A1 (fr) | 1980-08-22 |
JPS594050B2 (ja) | 1984-01-27 |
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