FR2445988A1 - IMPROVED ADDRESSING DEVICE OF A DATA PROCESSING SYSTEM - Google Patents

IMPROVED ADDRESSING DEVICE OF A DATA PROCESSING SYSTEM

Info

Publication number
FR2445988A1
FR2445988A1 FR7931456A FR7931456A FR2445988A1 FR 2445988 A1 FR2445988 A1 FR 2445988A1 FR 7931456 A FR7931456 A FR 7931456A FR 7931456 A FR7931456 A FR 7931456A FR 2445988 A1 FR2445988 A1 FR 2445988A1
Authority
FR
France
Prior art keywords
addressing
bus
processing system
data processing
usart
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7931456A
Other languages
French (fr)
Other versions
FR2445988B1 (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Italia SpA
Bull HN Information Systems Inc
Original Assignee
Honeywell Information Systems Italia SpA
Honeywell Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US06/000,463 external-priority patent/US4290104A/en
Priority claimed from US06/000,314 external-priority patent/US4257101A/en
Application filed by Honeywell Information Systems Italia SpA, Honeywell Information Systems Inc filed Critical Honeywell Information Systems Italia SpA
Publication of FR2445988A1 publication Critical patent/FR2445988A1/en
Application granted granted Critical
Publication of FR2445988B1 publication Critical patent/FR2445988B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0615—Address space extension
    • G06F12/0623—Address space extension for memory modules
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Microcomputers (AREA)

Abstract

L'invention concerne un dispositif d'adressage perfectionné d'un système de traitement de données. Ce dispositif permet d'accroître la capacité d'adressage d'un microprocesseur 101 dans ce système de traitement qui comprend en outre un émetteur-récepteur universel (USART), un registre, une mémoire virtuelle et une mémoire réelle 108, un bus U reliant le circuit USART au microprocesseur, un bus I reliant le registre au bus U, un bus M reliant les mémoires réelle et virtuelle au bus U. Ce dispositif est caractérisé en ce qu'il comprend un générateur 105 de signaux de commande, un premier moyen d'adressage 106 pour adresser la mémoire virtuelle, un second moyen d'adressage 107 pour adresser la memoire réelle, un troisième moyen 111 pour modifier les adresses du second moyen en réponse à des signaux de commande du générateur et un quatrième moyen 120, 121 relié au troisième moyen et au bus U pour adresser le circuit USART. Application à la maintenance à distance d'un ordinateur.The invention relates to an improved addressing device for a data processing system. This device makes it possible to increase the addressing capacity of a microprocessor 101 in this processing system which further comprises a universal transceiver (USART), a register, a virtual memory and a real memory 108, a U bus connecting the USART circuit to the microprocessor, an I bus connecting the register to the U bus, an M bus connecting the real and virtual memories to the U bus. This device is characterized in that it comprises a generator 105 of control signals, a first means address 106 for addressing the virtual memory, a second addressing means 107 for addressing the real memory, a third means 111 for modifying the addresses of the second means in response to control signals from the generator and a fourth means 120, 121 connected to the third means and to the U bus to address the USART circuit. Application to the remote maintenance of a computer.

FR7931456A 1979-01-02 1979-12-21 IMPROVED ADDRESSING DEVICE OF A DATA PROCESSING SYSTEM Granted FR2445988A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US30479A 1979-01-02 1979-01-02
US06/000,463 US4290104A (en) 1979-01-02 1979-01-02 Computer system having a paging apparatus for mapping virtual addresses to real addresses for a memory of a multiline communications controller
US06/000,314 US4257101A (en) 1979-01-02 1979-01-02 Hardware in a computer system for maintenance by a remote computer system

Publications (2)

Publication Number Publication Date
FR2445988A1 true FR2445988A1 (en) 1980-08-01
FR2445988B1 FR2445988B1 (en) 1985-04-19

Family

ID=27356644

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7931456A Granted FR2445988A1 (en) 1979-01-02 1979-12-21 IMPROVED ADDRESSING DEVICE OF A DATA PROCESSING SYSTEM

Country Status (3)

Country Link
DE (1) DE2952314A1 (en)
FR (1) FR2445988A1 (en)
GB (1) GB2057729B (en)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3284778A (en) * 1962-01-04 1966-11-08 Siemens Ag Processor systems with index registers for address modification in digital computers
US3461433A (en) * 1967-01-27 1969-08-12 Sperry Rand Corp Relative addressing system for memories
GB1353311A (en) * 1971-12-23 1974-05-15 Ibm Memory system
US3909798A (en) * 1974-01-25 1975-09-30 Raytheon Co Virtual addressing method and apparatus
FR2305793A1 (en) * 1975-03-26 1976-10-22 Honeywell Inf Systems PROCESS FOR GENERATING THE ADDRESSES OF A MEMORY ORGANIZED BY PAGES
US4010451A (en) * 1972-10-03 1977-03-01 National Research Development Corporation Data structure processor
US4057847A (en) * 1976-06-14 1977-11-08 Sperry Rand Corporation Remote controlled test interface unit
GB1495332A (en) * 1974-02-26 1977-12-14 Periphonics Corp Memory having non-fixed relationships between addresses and storage locations

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3251041A (en) * 1962-04-17 1966-05-10 Melpar Inc Computer memory system
US3267462A (en) * 1963-08-13 1966-08-16 Keltec Ind Inc Transponder incorporating negative resistance amplifiers and multiport directional couplers
FR1567705A (en) * 1967-06-09 1969-04-08
FR122199A (en) * 1973-12-17

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3284778A (en) * 1962-01-04 1966-11-08 Siemens Ag Processor systems with index registers for address modification in digital computers
US3461433A (en) * 1967-01-27 1969-08-12 Sperry Rand Corp Relative addressing system for memories
GB1353311A (en) * 1971-12-23 1974-05-15 Ibm Memory system
US4010451A (en) * 1972-10-03 1977-03-01 National Research Development Corporation Data structure processor
US3909798A (en) * 1974-01-25 1975-09-30 Raytheon Co Virtual addressing method and apparatus
GB1495332A (en) * 1974-02-26 1977-12-14 Periphonics Corp Memory having non-fixed relationships between addresses and storage locations
FR2305793A1 (en) * 1975-03-26 1976-10-22 Honeywell Inf Systems PROCESS FOR GENERATING THE ADDRESSES OF A MEMORY ORGANIZED BY PAGES
US4057847A (en) * 1976-06-14 1977-11-08 Sperry Rand Corporation Remote controlled test interface unit

Also Published As

Publication number Publication date
GB2057729B (en) 1983-08-10
GB2057729A (en) 1981-04-01
FR2445988B1 (en) 1985-04-19
DE2952314A1 (en) 1980-07-17
DE2952314C2 (en) 1987-11-05

Similar Documents

Publication Publication Date Title
US4070706A (en) Parallel requestor priority determination and requestor address matching in a cache memory system
FR2400729A1 (en) DEVICE FOR THE TRANSFORMATION OF VIRTUAL ADDRESSES INTO PHYSICAL ADDRESSES IN A DATA PROCESSING SYSTEM
DE69228380D1 (en) METHOD FOR INCREASING THE DATA PROCESSING SPEED IN A COMPUTER SYSTEM
FR2472233B1 (en) MEMORY CONTROL DEVICE FOR DATA PROCESSING SYSTEM
EP0518488A1 (en) Bus interface and processing system
FR2436443A1 (en) CHANNEL ADDRESS CONTROL DEVICE FOR A COMPUTER SYSTEM
SE455740B (en) MEMORY MANAGEMENT SYSTEM PROVIDED FOR USE IN COMPUTER SYSTEM USING VIRTUAL MEMORY TECHNOLOGY
FR2377667A1 (en) SYSTEM FOR BLOCKING THE MEMORY OF A DATA PROCESSING SYSTEM
YU47428B (en) DEVICE FOR INCREASING THE AVAILABILITY OF OPERANDS IN THE DATA PROCESSING SYSTEM
FR2445988A1 (en) IMPROVED ADDRESSING DEVICE OF A DATA PROCESSING SYSTEM
FR2357002A1 (en) ADDRESS COMPARISON DEVICE FOR DATA PROCESSING SYSTEMS
TNSN87107A1 (en) METHOD AND DEVICE FOR PERFORMING TWO SEQUENCES OF INSTRUCTIONS IN A PREDETERMINED ORDER
FR2445556A1 (en) TERMINAL SYSTEM WITH DIRECT MEMORY ACCESS DEVICE
EP0532690A1 (en) Method and apparatus for managing page zero memory accesses in a multi-processor system
DE69128948T2 (en) Device for controlling access to a data bus
FR2645320B1 (en) COMPACT MEMORY MODULE FOR DATA MEMORY CARD OF AN IMAGE PROCESSOR
EP0109337A3 (en) Data processing device with a multi-microcomputer for image processing
US5823871A (en) Interface control device for use with TV game equipment
FR2445557A1 (en) DATA TRANSFER DEVICE
FR2446515A1 (en) MULTIPROCESSOR CONTROL DEVICE FOR CONNECTION UNIT FRAMES
FR2448189A1 (en) ANTEMEMORY UNIT WITH SIMULTANEOUS READ / WRITE DEVICE
FR2413717A1 (en) INTERRUPTION PROCESSING DEVICE FOR A COMPUTER
SU1591030A2 (en) Device for interfacing two computers
BE1003383A6 (en) INPUT DEVICE FOR TESTING A COMPUTER.
SU1735864A1 (en) Data processing unit

Legal Events

Date Code Title Description
ST Notification of lapse