FR2419563A1 - Memoire de masse a l'etat solide a autocorrection, organisee en mots, pour systeme de controle de programmes enregistres - Google Patents
Memoire de masse a l'etat solide a autocorrection, organisee en mots, pour systeme de controle de programmes enregistresInfo
- Publication number
- FR2419563A1 FR2419563A1 FR7904801A FR7904801A FR2419563A1 FR 2419563 A1 FR2419563 A1 FR 2419563A1 FR 7904801 A FR7904801 A FR 7904801A FR 7904801 A FR7904801 A FR 7904801A FR 2419563 A1 FR2419563 A1 FR 2419563A1
- Authority
- FR
- France
- Prior art keywords
- self
- organized
- correction
- memory
- mass memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000007787 solid Substances 0.000 title 1
- 230000002457 bidirectional effect Effects 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/007—Digital input from or digital output to memories of the shift register type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
- G11C19/287—Organisation of a multiplicity of shift registers
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q3/00—Selecting arrangements
- H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
- H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
- H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
- H04Q3/54575—Software application
- H04Q3/54591—Supervision, e.g. fault localisation, traffic measurements, avoiding errors, failure recovery, monitoring, statistical analysis
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13168—Error Correction
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- Human Computer Interaction (AREA)
- Computer Networks & Wireless Communication (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Read Only Memory (AREA)
- Exchange Systems With Centralized Control (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Mémoire de masse à l'état solide à autocorrection, organisée en mots, comportant un ou une pluralité de modules de mémoire, un module de contrôle et un bus interne bidirectionnel. Chaque module de mémoire ME1 comprend une pluralité de rangées de circuits intégrés de mémoire AC1-1... AC2-21 réalisés selon la technologie de charges couplées et se composant de blocs de registre de décalage organisés selon une configuration série-parallèle-série, et des moyens d'entrée/sortie SF, RT1, A1, A2, CM1 aptes à connecter lesdits circuits AC audit bus interne 1; le module de contrôle comprend une base de temps microprogrammée, un circuit de contrôle d'adressage, des moyens d'entrée/sortie et une logique d'autocorrection. L'invention est utilisable dans les systèmes de contrôle de programmes enregistrés pour appareils de télécommunications.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT67499/78A IT1108375B (it) | 1978-03-09 | 1978-03-09 | Memoria di massa allo stato solido con autocorrezione e organizzata a parole per un sistema di controllo a programma registrato |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2419563A1 true FR2419563A1 (fr) | 1979-10-05 |
FR2419563B1 FR2419563B1 (fr) | 1984-01-27 |
Family
ID=11302932
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7904801A Granted FR2419563A1 (fr) | 1978-03-09 | 1979-02-26 | Memoire de masse a l'etat solide a autocorrection, organisee en mots, pour systeme de controle de programmes enregistres |
Country Status (10)
Country | Link |
---|---|
US (1) | US4216532A (fr) |
JP (1) | JPS54126434A (fr) |
BE (1) | BE874402A (fr) |
BR (1) | BR7901391A (fr) |
CA (1) | CA1114513A (fr) |
DE (1) | DE2909151C2 (fr) |
FR (1) | FR2419563A1 (fr) |
GB (1) | GB2016180B (fr) |
IT (1) | IT1108375B (fr) |
NL (1) | NL7901871A (fr) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
IT1109655B (it) * | 1978-06-28 | 1985-12-23 | Cselt Centro Studi Lab Telecom | Memoria di massa allo stato solido organizzata a bit autocorrettiva e riconfigurabile per un sistema di controllo a programma registrato |
CA1232355A (fr) * | 1983-09-02 | 1988-02-02 | Wang Laboratories, Inc. | Module de memoire en ligne |
GB2172126A (en) * | 1985-01-24 | 1986-09-10 | John Richard Mumford | Interchangeable solid state memory device |
US6842802B2 (en) * | 2001-11-30 | 2005-01-11 | Aftg-Tg, L.L.C. | Programmatic time-gap defect correction apparatus and method |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2141094A5 (fr) * | 1971-06-11 | 1973-01-19 | Ibm | |
DE2817559A1 (de) * | 1977-04-21 | 1978-11-02 | Texas Instruments Inc | Steueranordnung fuer eine speichervorrichtung |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3953837A (en) * | 1974-11-27 | 1976-04-27 | Texas Instruments Incorporated | Dual serial-parallel-serial analog memory |
DE2524802A1 (de) * | 1975-06-04 | 1976-12-16 | Siemens Ag | Arbeitsspeicheranordnung |
-
1978
- 1978-03-09 IT IT67499/78A patent/IT1108375B/it active
-
1979
- 1979-02-23 BE BE193654A patent/BE874402A/fr not_active IP Right Cessation
- 1979-02-26 FR FR7904801A patent/FR2419563A1/fr active Granted
- 1979-03-02 US US06/017,037 patent/US4216532A/en not_active Expired - Lifetime
- 1979-03-02 CA CA322,714A patent/CA1114513A/fr not_active Expired
- 1979-03-07 BR BR7901391A patent/BR7901391A/pt unknown
- 1979-03-08 NL NL7901871A patent/NL7901871A/xx not_active Application Discontinuation
- 1979-03-08 GB GB7908282A patent/GB2016180B/en not_active Expired
- 1979-03-08 JP JP2759079A patent/JPS54126434A/ja active Pending
- 1979-03-08 DE DE2909151A patent/DE2909151C2/de not_active Expired
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2141094A5 (fr) * | 1971-06-11 | 1973-01-19 | Ibm | |
DE2817559A1 (de) * | 1977-04-21 | 1978-11-02 | Texas Instruments Inc | Steueranordnung fuer eine speichervorrichtung |
Non-Patent Citations (4)
Title |
---|
EXBK/75 * |
EXBK/76 * |
EXBK/77 * |
EXBK/78 * |
Also Published As
Publication number | Publication date |
---|---|
IT1108375B (it) | 1985-12-09 |
GB2016180A (en) | 1979-09-19 |
NL7901871A (nl) | 1979-09-11 |
JPS54126434A (en) | 1979-10-01 |
US4216532A (en) | 1980-08-05 |
GB2016180B (en) | 1982-06-09 |
CA1114513A (fr) | 1981-12-15 |
IT7867499A0 (it) | 1978-03-09 |
DE2909151A1 (de) | 1979-09-13 |
BE874402A (fr) | 1979-06-18 |
BR7901391A (pt) | 1979-10-02 |
DE2909151C2 (de) | 1983-06-09 |
FR2419563B1 (fr) | 1984-01-27 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |