FR2413828A2 - SYNCHRONISM MAINTENANCE CIRCUIT FOR DIGITAL TELECOMMUNICATIONS NETWORK - Google Patents
SYNCHRONISM MAINTENANCE CIRCUIT FOR DIGITAL TELECOMMUNICATIONS NETWORKInfo
- Publication number
- FR2413828A2 FR2413828A2 FR7836937A FR7836937A FR2413828A2 FR 2413828 A2 FR2413828 A2 FR 2413828A2 FR 7836937 A FR7836937 A FR 7836937A FR 7836937 A FR7836937 A FR 7836937A FR 2413828 A2 FR2413828 A2 FR 2413828A2
- Authority
- FR
- France
- Prior art keywords
- input
- output
- clock
- address
- signals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0676—Mutual
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Time-Division Multiplex Systems (AREA)
Abstract
An arrangement for maintaining synchronism in a digital telecommunication network comprises a plurality of transit stations. Each transit station includes a clock means (1) which is arranged to supply a local station clock signal and which is provided with a control input (3). A comparator means (5) has a first input arranged to be supplied with line clock signals associated with a plurality of incoming lines from the other transit stations and a second input arranged to be supplied with said local station clock signal. The comparator means is also provided with a signal output (6) arranged to supply sequentially local comparison signals for the line clock signals and connected to the control input of the clock means. The last mentioned connection is effected by means of a loop filter comprising a memory means (24) having an address input (25) and a read output (26) and which is arranged to store selected weighting coefficients for the line clock signals, an address counter means (27) having an output (33) arranged for a sequential read out of address words associated with the local comparison signals for said line clock signals and connected to the address input of the memory means, and a multiplier means (34) having a first input connected to the signal output of the comparator means, a second input connected to the read output of the memory means and an output connected to the control input of the clock means via an averaging means (38). According to the invention, the loop filter is localized in a central monitoring station in the telecommunication network wherein it is connected between the signal output (6) of the comparator means (5) and the control input (3), of the clock means (1) in said transit stations via a first and second signalling channel in the telecommunication network and wherein buffer storage means (36) are arranged for said local comparison signals for the line clock signals. The buffer storage means have an address input (46) for read out connected to the output (33) of said address counter means (27).
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| SE7714965A SE7714965L (en) | 1977-12-30 | 1977-12-30 | DEVICE FOR MAINTAINING SYNCHRONISM IN A DIGITAL TELECOMMUNICATIONS NETWORK |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| FR2413828A2 true FR2413828A2 (en) | 1979-07-27 |
Family
ID=20333359
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR7836937A Pending FR2413828A2 (en) | 1977-12-30 | 1978-12-29 | SYNCHRONISM MAINTENANCE CIRCUIT FOR DIGITAL TELECOMMUNICATIONS NETWORK |
Country Status (7)
| Country | Link |
|---|---|
| JP (1) | JPS55500022A (en) |
| AU (1) | AU4270478A (en) |
| ES (1) | ES476486A1 (en) |
| FR (1) | FR2413828A2 (en) |
| NL (1) | NL7812583A (en) |
| SE (1) | SE7714965L (en) |
| WO (1) | WO1979000459A1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SE430456B (en) * | 1982-03-10 | 1983-11-14 | Ericsson Telefon Ab L M | SET AND DEVICE FOR PHASE SYNCHRONIZING A BROADCASTING STATION IN A DIGITAL TELECOMMUNICATION NETWORK |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SE398698B (en) * | 1976-04-27 | 1978-01-09 | Ericsson Telefon Ab L M | DEVICE FOR FASIN SYNCHRONIZATION OF A COMMUNICATION STATION IN A DIGITAL TELECOMMUNICATIONS NETWORK |
-
1977
- 1977-12-30 SE SE7714965A patent/SE7714965L/en unknown
-
1978
- 1978-12-05 WO PCT/SE1978/000090 patent/WO1979000459A1/en unknown
- 1978-12-05 JP JP50012378A patent/JPS55500022A/ja active Pending
- 1978-12-19 AU AU42704/78A patent/AU4270478A/en active Pending
- 1978-12-27 NL NL7812583A patent/NL7812583A/en not_active Application Discontinuation
- 1978-12-29 FR FR7836937A patent/FR2413828A2/en active Pending
- 1978-12-29 ES ES476486A patent/ES476486A1/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| SE7714965L (en) | 1979-07-01 |
| JPS55500022A (en) | 1980-01-24 |
| NL7812583A (en) | 1979-07-03 |
| ES476486A1 (en) | 1979-04-16 |
| AU4270478A (en) | 1979-07-05 |
| WO1979000459A1 (en) | 1979-07-26 |
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