FR2413718B1 - Procede de realisation de la coincidence de memoires tampon dans un systeme informatique multiprocesseur - Google Patents
Procede de realisation de la coincidence de memoires tampon dans un systeme informatique multiprocesseurInfo
- Publication number
- FR2413718B1 FR2413718B1 FR7836905A FR7836905A FR2413718B1 FR 2413718 B1 FR2413718 B1 FR 2413718B1 FR 7836905 A FR7836905 A FR 7836905A FR 7836905 A FR7836905 A FR 7836905A FR 2413718 B1 FR2413718 B1 FR 2413718B1
- Authority
- FR
- France
- Prior art keywords
- coincidence
- realizing
- computer system
- buffer memories
- multiprocessor computer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Multi Processors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP52160451A JPS5849945B2 (ja) | 1977-12-29 | 1977-12-29 | バツフア合せ方式 |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2413718A1 FR2413718A1 (fr) | 1979-07-27 |
FR2413718B1 true FR2413718B1 (fr) | 1986-03-28 |
Family
ID=15715208
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7836905A Expired FR2413718B1 (fr) | 1977-12-29 | 1978-12-29 | Procede de realisation de la coincidence de memoires tampon dans un systeme informatique multiprocesseur |
Country Status (5)
Country | Link |
---|---|
US (1) | US4290103A (fr) |
JP (1) | JPS5849945B2 (fr) |
DE (1) | DE2856715C3 (fr) |
FR (1) | FR2413718B1 (fr) |
GB (1) | GB2011667B (fr) |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4345309A (en) * | 1980-01-28 | 1982-08-17 | Digital Equipment Corporation | Relating to cached multiprocessor system with pipeline timing |
US4399506A (en) * | 1980-10-06 | 1983-08-16 | International Business Machines Corporation | Store-in-cache processor means for clearing main storage |
CA1187198A (fr) * | 1981-06-15 | 1985-05-14 | Takashi Chiba | Systeme pour controler l'acces a un tampon de canaux |
US4464712A (en) * | 1981-07-06 | 1984-08-07 | International Business Machines Corporation | Second level cache replacement method and apparatus |
US4442487A (en) * | 1981-12-31 | 1984-04-10 | International Business Machines Corporation | Three level memory hierarchy using write and share flags |
JPS60124754A (ja) * | 1983-12-09 | 1985-07-03 | Fujitsu Ltd | バッファ記憶制御装置 |
CA1241768A (fr) * | 1984-06-22 | 1988-09-06 | Miyuki Ishida | Circuit de controle de drapeaux pour memoire tampon |
US4755930A (en) * | 1985-06-27 | 1988-07-05 | Encore Computer Corporation | Hierarchical cache memory system and method |
JPS62147548A (ja) * | 1985-12-23 | 1987-07-01 | Mitsubishi Electric Corp | 外部記憶制御装置 |
US4797814A (en) * | 1986-05-01 | 1989-01-10 | International Business Machines Corporation | Variable address mode cache |
US5179665A (en) * | 1987-06-24 | 1993-01-12 | Westinghouse Electric Corp. | Microprocessor information exchange with updating of messages by asynchronous processors using assigned and/or available buffers in dual port memory |
US5058006A (en) * | 1988-06-27 | 1991-10-15 | Digital Equipment Corporation | Method and apparatus for filtering invalidate requests |
EP0348628A3 (fr) * | 1988-06-28 | 1991-01-02 | International Business Machines Corporation | Système d'antémémoire |
US5032985A (en) * | 1988-07-21 | 1991-07-16 | International Business Machines Corporation | Multiprocessor system with memory fetch buffer invoked during cross-interrogation |
DE4005319C2 (de) * | 1989-02-22 | 1994-06-16 | Siemens Nixdorf Inf Syst | Verfahren und Anordnung zur Aufrechterhaltung der Datenkonsistenz in einem Multiprozessorsystem mit privaten Cachespeichern |
JPH035851A (ja) * | 1989-06-01 | 1991-01-11 | Fujitsu Ltd | バッファ記憶装置 |
US5307477A (en) * | 1989-12-01 | 1994-04-26 | Mips Computer Systems, Inc. | Two-level cache memory system |
US5467460A (en) * | 1990-02-14 | 1995-11-14 | Intel Corporation | M&A for minimizing data transfer to main memory from a writeback cache during a cache miss |
CA2047888A1 (fr) * | 1990-07-27 | 1992-01-28 | Hirosada Tone | Systeme de commande pour memoire hierarchisee |
US5269009A (en) * | 1990-09-04 | 1993-12-07 | International Business Machines Corporation | Processor system with improved memory transfer means |
JP2707958B2 (ja) * | 1993-12-09 | 1998-02-04 | 日本電気株式会社 | キャッシュ一致処理制御装置 |
GB2450538A (en) * | 2007-06-28 | 2008-12-31 | Symbian Software Ltd | Copying computer files when manipulation is requested |
KR102629561B1 (ko) * | 2021-01-15 | 2024-01-25 | 한국건설기술연구원 | 슬래브의 단열 구조물 및 그 시공방법 |
KR102570281B1 (ko) * | 2022-06-14 | 2023-08-24 | 한국건설기술연구원 | 입체 경사의 형성이 가능한 단열부재 및 이를 이용한 슬래브의 단열 구조물 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3581291A (en) * | 1968-10-31 | 1971-05-25 | Hitachi Ltd | Memory control system in multiprocessing system |
US3771137A (en) * | 1971-09-10 | 1973-11-06 | Ibm | Memory control in a multipurpose system utilizing a broadcast |
JPS5440182B2 (fr) * | 1974-02-26 | 1979-12-01 | ||
JPS5295128A (en) * | 1976-02-06 | 1977-08-10 | Hitachi Ltd | Information processing device |
US4136386A (en) * | 1977-10-06 | 1979-01-23 | International Business Machines Corporation | Backing store access coordination in a multi-processor system |
US4142234A (en) * | 1977-11-28 | 1979-02-27 | International Business Machines Corporation | Bias filter memory for filtering out unnecessary interrogations of cache directories in a multiprocessor system |
-
1977
- 1977-12-29 JP JP52160451A patent/JPS5849945B2/ja not_active Expired
-
1978
- 1978-10-26 GB GB7842069A patent/GB2011667B/en not_active Expired
- 1978-10-30 US US05/955,760 patent/US4290103A/en not_active Expired - Lifetime
- 1978-12-29 DE DE2856715A patent/DE2856715C3/de not_active Expired
- 1978-12-29 FR FR7836905A patent/FR2413718B1/fr not_active Expired
Also Published As
Publication number | Publication date |
---|---|
DE2856715A1 (de) | 1979-09-27 |
JPS5849945B2 (ja) | 1983-11-08 |
GB2011667A (en) | 1979-07-11 |
JPS5492137A (en) | 1979-07-21 |
US4290103A (en) | 1981-09-15 |
FR2413718A1 (fr) | 1979-07-27 |
DE2856715C3 (de) | 1981-10-15 |
GB2011667B (en) | 1982-05-19 |
DE2856715B2 (de) | 1981-02-19 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |