FR2373192A1 - Coding and decoding system for A=D conversion - operates with initial bit sequence divided into blocks handled separately - Google Patents

Coding and decoding system for A=D conversion - operates with initial bit sequence divided into blocks handled separately

Info

Publication number
FR2373192A1
FR2373192A1 FR7636531A FR7636531A FR2373192A1 FR 2373192 A1 FR2373192 A1 FR 2373192A1 FR 7636531 A FR7636531 A FR 7636531A FR 7636531 A FR7636531 A FR 7636531A FR 2373192 A1 FR2373192 A1 FR 2373192A1
Authority
FR
France
Prior art keywords
bit sequence
coding
bit
block
decoding system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7636531A
Other languages
French (fr)
Other versions
FR2373192B3 (en
Inventor
Jean-Marc Kergosien
Jean-Claude Lehureau
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
Thomson CSF SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson CSF SA filed Critical Thomson CSF SA
Priority to FR7636531A priority Critical patent/FR2373192A1/en
Publication of FR2373192A1 publication Critical patent/FR2373192A1/en
Application granted granted Critical
Publication of FR2373192B3 publication Critical patent/FR2373192B3/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4906—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Error Detection And Correction (AREA)

Abstract

The coding-decoding system is used for a data bit sequence provided by a source and transmitted to a reception unit in analogue form. The data bit sequence is divided into single bit blocks, a number of parity bits associated with each block. Each block is converted into an analogue value, which can then be reconverted back into a bit block. The parity bits associated with each block are provided by repetition of the preceding data bits, such that each bit is contained within a number of successive blocks, but with a different weighting. These successive blocks are stored in a memory providing access to the values assigned to each bit, for error correction.
FR7636531A 1976-12-03 1976-12-03 Coding and decoding system for A=D conversion - operates with initial bit sequence divided into blocks handled separately Granted FR2373192A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR7636531A FR2373192A1 (en) 1976-12-03 1976-12-03 Coding and decoding system for A=D conversion - operates with initial bit sequence divided into blocks handled separately

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7636531A FR2373192A1 (en) 1976-12-03 1976-12-03 Coding and decoding system for A=D conversion - operates with initial bit sequence divided into blocks handled separately

Publications (2)

Publication Number Publication Date
FR2373192A1 true FR2373192A1 (en) 1978-06-30
FR2373192B3 FR2373192B3 (en) 1980-09-19

Family

ID=9180644

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7636531A Granted FR2373192A1 (en) 1976-12-03 1976-12-03 Coding and decoding system for A=D conversion - operates with initial bit sequence divided into blocks handled separately

Country Status (1)

Country Link
FR (1) FR2373192A1 (en)

Also Published As

Publication number Publication date
FR2373192B3 (en) 1980-09-19

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