FR2362470A1 - Cellule de memoire a acces direct bipolaire de schottky a double entree - Google Patents
Cellule de memoire a acces direct bipolaire de schottky a double entreeInfo
- Publication number
- FR2362470A1 FR2362470A1 FR7724720A FR7724720A FR2362470A1 FR 2362470 A1 FR2362470 A1 FR 2362470A1 FR 7724720 A FR7724720 A FR 7724720A FR 7724720 A FR7724720 A FR 7724720A FR 2362470 A1 FR2362470 A1 FR 2362470A1
- Authority
- FR
- France
- Prior art keywords
- lines
- memory cell
- access memory
- direct access
- double entry
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
- H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
- H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
- H03K3/286—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/411—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only
- G11C11/4113—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only with at least one cell access to base or collector of at least one of said transistors, e.g. via access diodes, access transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
- G11C11/416—Read-write [R-W] circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Static Random-Access Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
La cellule suivant l'invention comprend une paire de transistors de Schottky NPN connectés en montage multivibrateur bistable non saturable. Le collecteur de chaque transistor est couplé avec le collecteur d'un transistor latéral dont l'émetteur est connecté aux lignes de chiffre ou de bit de sortie de la mémoire. La base de chacun des transistors latéraux est reliée à l'une des deux lignes de sélection, de sorte que le signal << lecture>> appliqué à l'une quelconque de ces deux lignes permet à un transistor latéral de détecter l'état de la bascule. On effectue l'écriture en appliquant des signaux logiques hauts aux deux lignes de sélection et à l'une des lignes de bit, cependant que la seconde ligne de bit est commutée à un état bas. Application notamment aux calculateurs numériques.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US71453576A | 1976-08-16 | 1976-08-16 |
Publications (1)
Publication Number | Publication Date |
---|---|
FR2362470A1 true FR2362470A1 (fr) | 1978-03-17 |
Family
ID=24870414
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7724720A Withdrawn FR2362470A1 (fr) | 1976-08-16 | 1977-08-11 | Cellule de memoire a acces direct bipolaire de schottky a double entree |
Country Status (6)
Country | Link |
---|---|
US (1) | US4138739A (fr) |
JP (1) | JPS6010392B2 (fr) |
CA (1) | CA1092239A (fr) |
DE (1) | DE2726997A1 (fr) |
FR (1) | FR2362470A1 (fr) |
GB (1) | GB1565146A (fr) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4280197A (en) * | 1979-12-07 | 1981-07-21 | Ibm Corporation | Multiple access store |
US4287575A (en) * | 1979-12-28 | 1981-09-01 | International Business Machines Corporation | High speed high density, multi-port random access memory cell |
JPS6257892U (fr) * | 1985-09-28 | 1987-04-10 | ||
JPS62102499A (ja) * | 1985-10-28 | 1987-05-12 | Nec Corp | メモリ回路 |
GB2247550B (en) * | 1990-06-29 | 1994-08-03 | Digital Equipment Corp | Bipolar transistor memory cell and method |
US5265047A (en) * | 1992-03-09 | 1993-11-23 | Monolithic System Technology | High density SRAM circuit with single-ended memory cells |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3614753A (en) * | 1969-11-10 | 1971-10-19 | Shell Oil Co | Single-rail solid-state memory with capacitive storage |
US3675218A (en) * | 1970-01-15 | 1972-07-04 | Ibm | Independent read-write monolithic memory array |
US3753247A (en) * | 1971-04-22 | 1973-08-14 | Rca Corp | Array of devices responsive to differential light signals |
US3979735A (en) * | 1973-12-13 | 1976-09-07 | Rca Corporation | Information storage circuit |
US3919566A (en) * | 1973-12-26 | 1975-11-11 | Motorola Inc | Sense-write circuit for bipolar integrated circuit ram |
US3909807A (en) * | 1974-09-03 | 1975-09-30 | Bell Telephone Labor Inc | Integrated circuit memory cell |
DE2460150C2 (de) * | 1974-12-19 | 1984-07-12 | Ibm Deutschland Gmbh, 7000 Stuttgart | Monolitisch integrierbare Speicheranordnung |
-
1977
- 1977-05-10 GB GB19586/77A patent/GB1565146A/en not_active Expired
- 1977-05-27 JP JP52061291A patent/JPS6010392B2/ja not_active Expired
- 1977-06-01 CA CA279,657A patent/CA1092239A/fr not_active Expired
- 1977-06-15 DE DE19772726997 patent/DE2726997A1/de not_active Withdrawn
- 1977-08-11 FR FR7724720A patent/FR2362470A1/fr not_active Withdrawn
- 1977-10-31 US US05/846,479 patent/US4138739A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPS6010392B2 (ja) | 1985-03-16 |
US4138739A (en) | 1979-02-06 |
JPS5323529A (en) | 1978-03-04 |
CA1092239A (fr) | 1980-12-23 |
GB1565146A (en) | 1980-04-16 |
DE2726997A1 (de) | 1978-02-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS5986097U (ja) | ランダム・アクセス・メモリ | |
GB1402918A (en) | Memory system | |
KR920001542A (ko) | 감지 증폭기를 갖는 반도체 메모리 | |
EP0137135A3 (fr) | Mémoire semi-conductrice | |
KR910017636A (ko) | 반도체 기억장치 | |
FR2385179A1 (fr) | Circuits d'acces a des cellules d'emmagasinage et leur mode de fonctionnement | |
FR2362470A1 (fr) | Cellule de memoire a acces direct bipolaire de schottky a double entree | |
KR0154193B1 (ko) | 센스 앰프회로 | |
JPH01130387A (ja) | 半導体記憶装置 | |
GB1509633A (en) | Memory device | |
US5239506A (en) | Latch and data out driver for memory arrays | |
US3588848A (en) | Input-output control circuit for memory circuit | |
EP0169351A3 (fr) | Réseau de portes intégrées sur une puce | |
KR910013282A (ko) | 복수포트 반도체메모리 | |
GB1128576A (en) | Data store | |
KR870007511A (ko) | 데이타 판독회로 | |
KR900008523A (ko) | 반도체 메모리 소자 | |
GB1522444A (en) | Detector circuit for reading signals on data lines | |
KR880004484A (ko) | 메모리 셀회로 | |
JPS6383992A (ja) | Lsiメモリ | |
GB1410875A (en) | Static flipflop circuits | |
KR890008847A (ko) | 불휘발성 메모리 | |
JPS6217320B2 (fr) | ||
JPS63877B2 (fr) | ||
IT1043636B (it) | Cella di memoria perfezionata |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |