FR2356276A1 - Semiconductor device with two layers of opposite conductivity - has one layer with zone of reduced thickness peripherally surrounding semiconductor device (NL 23.12.77) - Google Patents
Semiconductor device with two layers of opposite conductivity - has one layer with zone of reduced thickness peripherally surrounding semiconductor device (NL 23.12.77)Info
- Publication number
- FR2356276A1 FR2356276A1 FR7718467A FR7718467A FR2356276A1 FR 2356276 A1 FR2356276 A1 FR 2356276A1 FR 7718467 A FR7718467 A FR 7718467A FR 7718467 A FR7718467 A FR 7718467A FR 2356276 A1 FR2356276 A1 FR 2356276A1
- Authority
- FR
- France
- Prior art keywords
- semiconductor device
- layers
- zone
- layer
- reduced thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title abstract 6
- 230000015556 catabolic process Effects 0.000 abstract 1
- 230000008878 coupling Effects 0.000 abstract 1
- 238000010168 coupling process Methods 0.000 abstract 1
- 238000005859 coupling reaction Methods 0.000 abstract 1
- 239000012535 impurity Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
- Bipolar Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
A junction is produced between the two semiconductor layers. Two ideal, single-dimensional depletion thickness region in the two layers. In order to increase the device breakdown voltage, it has a relatively thin zone (28) in the first semi-conductor layer (24) which surrounds the device. A zone of a relatively constant thickness (Y), smaller than the thickness of the single-dimensional depletion region in the first semiconductor layer (24). This relatively thin zone (28) has a width at least equal to half the coupling distance of the pn-junction. Preferably the semi-conductor layers have different impurity concentrations. The pre-junction may be flat or planar.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US69801476A | 1976-06-21 | 1976-06-21 |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2356276A1 true FR2356276A1 (en) | 1978-01-20 |
FR2356276B1 FR2356276B1 (en) | 1983-02-04 |
Family
ID=24803556
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7718467A Granted FR2356276A1 (en) | 1976-06-21 | 1977-06-16 | Semiconductor device with two layers of opposite conductivity - has one layer with zone of reduced thickness peripherally surrounding semiconductor device (NL 23.12.77) |
Country Status (5)
Country | Link |
---|---|
JP (1) | JPS538069A (en) |
DE (1) | DE2727487C2 (en) |
FR (1) | FR2356276A1 (en) |
NL (1) | NL180265C (en) |
SE (1) | SE7707190L (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2449971A1 (en) * | 1979-02-22 | 1980-09-19 | Rca Corp | ONE-TIME ATTACK METHOD FOR FORMING A MESA STRUCTURE HAVING MULTI-STAGE WALL |
EP0144876A2 (en) * | 1983-12-07 | 1985-06-19 | BBC Brown Boveri AG | Semiconductor device |
EP0164645A2 (en) * | 1984-06-14 | 1985-12-18 | Asea Brown Boveri Aktiengesellschaft | Silicon semiconductor device having a contour of the border formed by chemical attack, and process for manufacturing this device |
EP0389863A1 (en) * | 1989-03-29 | 1990-10-03 | Siemens Aktiengesellschaft | Process for manufacturing a high-voltage withstanding planar p-n junction |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6190463A (en) * | 1984-10-11 | 1986-05-08 | Hitachi Ltd | Semiconductor device |
DE10349908C5 (en) * | 2003-10-25 | 2009-02-12 | Semikron Elektronik Gmbh & Co. Kg | Method for producing a doubly passivated power semiconductor device having a MESA edge structure |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1052661A (en) * | 1963-01-30 | 1900-01-01 | ||
DE1539961A1 (en) * | 1965-03-17 | 1970-01-22 | Fuji Electric Co Ltd | Semiconductor component with at least two pn junctions in the monocrystalline semiconductor body |
DE1276207B (en) * | 1966-09-09 | 1968-08-29 | Licentia Gmbh | Semiconductor component |
-
1977
- 1977-06-10 NL NLAANVRAGE7706389,A patent/NL180265C/en not_active IP Right Cessation
- 1977-06-16 FR FR7718467A patent/FR2356276A1/en active Granted
- 1977-06-18 DE DE2727487A patent/DE2727487C2/en not_active Expired
- 1977-06-21 JP JP7290177A patent/JPS538069A/en active Granted
- 1977-06-21 SE SE7707190A patent/SE7707190L/en unknown
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2449971A1 (en) * | 1979-02-22 | 1980-09-19 | Rca Corp | ONE-TIME ATTACK METHOD FOR FORMING A MESA STRUCTURE HAVING MULTI-STAGE WALL |
EP0144876A2 (en) * | 1983-12-07 | 1985-06-19 | BBC Brown Boveri AG | Semiconductor device |
EP0144876A3 (en) * | 1983-12-07 | 1985-07-03 | Bbc Aktiengesellschaft Brown, Boveri & Cie. | Semiconductor device |
EP0164645A2 (en) * | 1984-06-14 | 1985-12-18 | Asea Brown Boveri Aktiengesellschaft | Silicon semiconductor device having a contour of the border formed by chemical attack, and process for manufacturing this device |
EP0164645A3 (en) * | 1984-06-14 | 1987-09-30 | Asea Brown Boveri Aktiengesellschaft | Silicon semiconductor device having a contour of the border formed by chemical attack, and process for manufacturing this device |
EP0389863A1 (en) * | 1989-03-29 | 1990-10-03 | Siemens Aktiengesellschaft | Process for manufacturing a high-voltage withstanding planar p-n junction |
Also Published As
Publication number | Publication date |
---|---|
JPS5639057B2 (en) | 1981-09-10 |
SE7707190L (en) | 1977-12-22 |
DE2727487C2 (en) | 1985-05-15 |
FR2356276B1 (en) | 1983-02-04 |
NL180265C (en) | 1987-01-16 |
JPS538069A (en) | 1978-01-25 |
NL180265B (en) | 1986-08-18 |
DE2727487A1 (en) | 1977-12-29 |
NL7706389A (en) | 1977-12-23 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |