FR2341201A1 - Procede d'isolement entre regions d'un dispositif semiconducteur et dispositif ainsi obtenu - Google Patents

Procede d'isolement entre regions d'un dispositif semiconducteur et dispositif ainsi obtenu

Info

Publication number
FR2341201A1
FR2341201A1 FR7604169A FR7604169A FR2341201A1 FR 2341201 A1 FR2341201 A1 FR 2341201A1 FR 7604169 A FR7604169 A FR 7604169A FR 7604169 A FR7604169 A FR 7604169A FR 2341201 A1 FR2341201 A1 FR 2341201A1
Authority
FR
France
Prior art keywords
regions
isolation process
semiconductor device
semiconductor
isolation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7604169A
Other languages
English (en)
Other versions
FR2341201B1 (fr
Inventor
Michel De Brebisson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Radiotechnique Compelec RTC SA
Original Assignee
Radiotechnique Compelec RTC SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Radiotechnique Compelec RTC SA filed Critical Radiotechnique Compelec RTC SA
Priority to FR7604169A priority Critical patent/FR2341201A1/fr
Priority to US05/764,587 priority patent/US4113513A/en
Priority to DE2704471A priority patent/DE2704471C2/de
Priority to CA271,539A priority patent/CA1075374A/fr
Priority to GB5706/77A priority patent/GB1572854A/en
Priority to IT20241/77A priority patent/IT1076585B/it
Priority to JP1454677A priority patent/JPS5299767A/ja
Priority to AU22241/77A priority patent/AU505245B2/en
Priority to NLAANVRAGE7701511,A priority patent/NL176622C/xx
Publication of FR2341201A1 publication Critical patent/FR2341201A1/fr
Application granted granted Critical
Publication of FR2341201B1 publication Critical patent/FR2341201B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
FR7604169A 1976-02-16 1976-02-16 Procede d'isolement entre regions d'un dispositif semiconducteur et dispositif ainsi obtenu Granted FR2341201A1 (fr)

Priority Applications (9)

Application Number Priority Date Filing Date Title
FR7604169A FR2341201A1 (fr) 1976-02-16 1976-02-16 Procede d'isolement entre regions d'un dispositif semiconducteur et dispositif ainsi obtenu
US05/764,587 US4113513A (en) 1976-02-16 1977-02-01 Method of manufacturing a semiconductor device by non-selectively implanting a zone of pre-determined low resistivity
DE2704471A DE2704471C2 (de) 1976-02-16 1977-02-03 Verfahren zur Isolation von Halbleitergebieten
CA271,539A CA1075374A (fr) 1976-02-16 1977-02-10 Methode d'isolement pour semiconducteur
GB5706/77A GB1572854A (en) 1976-02-16 1977-02-11 Semiconductor device manufacture
IT20241/77A IT1076585B (it) 1976-02-16 1977-02-11 Metodo di fabbricazione di un dispositivo semiconduttore e dispositivo fabbricato con l'ausilio di tale metodo
JP1454677A JPS5299767A (en) 1976-02-16 1977-02-12 Method of making semiconductor device
AU22241/77A AU505245B2 (en) 1976-02-16 1977-02-14 Manufacturing semiconductor devices
NLAANVRAGE7701511,A NL176622C (nl) 1976-02-16 1977-02-14 Werkwijze voor de vervaardiging van een halfgeleiderinrichting.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7604169A FR2341201A1 (fr) 1976-02-16 1976-02-16 Procede d'isolement entre regions d'un dispositif semiconducteur et dispositif ainsi obtenu

Publications (2)

Publication Number Publication Date
FR2341201A1 true FR2341201A1 (fr) 1977-09-09
FR2341201B1 FR2341201B1 (fr) 1980-05-09

Family

ID=9169154

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7604169A Granted FR2341201A1 (fr) 1976-02-16 1976-02-16 Procede d'isolement entre regions d'un dispositif semiconducteur et dispositif ainsi obtenu

Country Status (9)

Country Link
US (1) US4113513A (fr)
JP (1) JPS5299767A (fr)
AU (1) AU505245B2 (fr)
CA (1) CA1075374A (fr)
DE (1) DE2704471C2 (fr)
FR (1) FR2341201A1 (fr)
GB (1) GB1572854A (fr)
IT (1) IT1076585B (fr)
NL (1) NL176622C (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0075588A1 (fr) * 1981-04-06 1983-04-06 Motorola Inc Procede de fabrication d'un canal enfoui auto-aligne et produits de ce procede.

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4247862B1 (en) * 1977-08-26 1995-12-26 Intel Corp Ionzation resistant mos structure
EP0033600A3 (fr) * 1980-01-18 1981-11-25 British Steel Corporation Procédé de fabrication d'acier ayant une structure à deux phases
US4362574A (en) * 1980-07-09 1982-12-07 Raytheon Company Integrated circuit and manufacturing method
US9941353B2 (en) * 2016-05-20 2018-04-10 Newport Fab, Llc Structure and method for mitigating substrate parasitics in bulk high resistivity substrate technology

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3386865A (en) * 1965-05-10 1968-06-04 Ibm Process of making planar semiconductor devices isolated by encapsulating oxide filled channels
NL7010208A (fr) * 1966-10-05 1972-01-12 Philips Nv
JPS4836598B1 (fr) * 1969-09-05 1973-11-06
NL169121C (nl) * 1970-07-10 1982-06-01 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een halfgeleiderlichaam, dat aan een oppervlak is voorzien van een althans ten dele in het halfgeleiderlichaam verzonken, door thermische oxydatie gevormd oxydepatroon.
US3748187A (en) * 1971-08-03 1973-07-24 Hughes Aircraft Co Self-registered doped layer for preventing field inversion in mis circuits
JPS5228550B2 (fr) * 1972-10-04 1977-07-27
US3886000A (en) * 1973-11-05 1975-05-27 Ibm Method for controlling dielectric isolation of a semiconductor device
JPS5546059B2 (fr) * 1973-12-22 1980-11-21
US4023195A (en) * 1974-10-23 1977-05-10 Smc Microsystems Corporation MOS field-effect transistor structure with mesa-like contact and gate areas and selectively deeper junctions
US4011105A (en) * 1975-09-15 1977-03-08 Mos Technology, Inc. Field inversion control for n-channel device integrated circuits

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0075588A1 (fr) * 1981-04-06 1983-04-06 Motorola Inc Procede de fabrication d'un canal enfoui auto-aligne et produits de ce procede.
EP0075588A4 (fr) * 1981-04-06 1984-07-18 Motorola Inc Procede de fabrication d'un canal enfoui auto-aligne et produits de ce procede.

Also Published As

Publication number Publication date
FR2341201B1 (fr) 1980-05-09
NL176622B (nl) 1984-12-03
IT1076585B (it) 1985-04-27
NL7701511A (nl) 1977-08-18
DE2704471A1 (de) 1977-08-18
NL176622C (nl) 1985-05-01
AU2224177A (en) 1978-08-24
GB1572854A (en) 1980-08-06
JPS5299767A (en) 1977-08-22
CA1075374A (fr) 1980-04-08
JPS5439708B2 (fr) 1979-11-29
US4113513A (en) 1978-09-12
AU505245B2 (en) 1979-11-15
DE2704471C2 (de) 1983-08-11

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Legal Events

Date Code Title Description
CA Change of address
CD Change of name or company name
ST Notification of lapse