FR2312061A1 - Programme control of process cycles - has programmed memory containing processor instructions - Google Patents

Programme control of process cycles - has programmed memory containing processor instructions

Info

Publication number
FR2312061A1
FR2312061A1 FR7614258A FR7614258A FR2312061A1 FR 2312061 A1 FR2312061 A1 FR 2312061A1 FR 7614258 A FR7614258 A FR 7614258A FR 7614258 A FR7614258 A FR 7614258A FR 2312061 A1 FR2312061 A1 FR 2312061A1
Authority
FR
France
Prior art keywords
bit
processor
peripherals
word
programme
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7614258A
Other languages
French (fr)
Other versions
FR2312061B3 (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of FR2312061A1 publication Critical patent/FR2312061A1/en
Application granted granted Critical
Publication of FR2312061B3 publication Critical patent/FR2312061B3/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
    • G05B19/052—Linking several PLC's
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/11—Plc I-O input output
    • G05B2219/1159—Image table, memory

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Multi Processors (AREA)
  • Advance Control (AREA)

Abstract

The programme controlled system for process applications uses a bit processor for operation of peripherals requiring a single bit order and a word processor for peripherals requiring a coded word of information. A digital word processor (WP) is coupled over an interface bus (DS) with standard peripherals (STP) such as page memories, displays, tape etc., process peripherals (PRP) such as multiplexers, D/A converters etc. and also any associated processor (VER). A programme memory (PSP) couples over the bus with a co-ordinate (KOR) tied to the bit processor (BP). The bit processor (BP) connects with an interface bus and communicates with single bit output peripherals (BA), bit memory (BSP) and bit input peripherals (BE). The programme memory (PSP) holds both the instructions for the word and bit memories alternately and enables the fast operation of the bit processor to be fully utilised.
FR7614258A 1975-05-20 1976-05-12 Programme control of process cycles - has programmed memory containing processor instructions Granted FR2312061A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19752522343 DE2522343C3 (en) 1975-05-20 1975-05-20 Arrangement for the control of process flows

Publications (2)

Publication Number Publication Date
FR2312061A1 true FR2312061A1 (en) 1976-12-17
FR2312061B3 FR2312061B3 (en) 1979-02-02

Family

ID=5946993

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7614258A Granted FR2312061A1 (en) 1975-05-20 1976-05-12 Programme control of process cycles - has programmed memory containing processor instructions

Country Status (2)

Country Link
DE (1) DE2522343C3 (en)
FR (1) FR2312061A1 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0237680A2 (en) * 1986-02-17 1987-09-23 Tektronix, Inc. Event distribution and combination system
EP0290121A1 (en) * 1987-04-21 1988-11-09 Tektronix Inc. Improved event distribution and combination system
EP0362819A2 (en) * 1988-10-05 1990-04-11 Kabushiki Kaisha Toshiba Programmable controller
EP0539115A2 (en) * 1991-10-24 1993-04-28 Hitachi, Ltd. Programmable controller and sequence control method
FR2695739A1 (en) * 1992-09-15 1994-03-18 April Automates Sa Data treatment process for e.g. robot, automatic machine - uses memory area to store boolean data on robot inputs and outputs for treatment by co-processor

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4058711A (en) * 1976-04-16 1977-11-15 Cincinnati Milacron Inc. Asynchronous dual function multiprocessor machine control
US4296464A (en) * 1977-03-03 1981-10-20 Honeywell Inc. Process control system with local microprocessor control means
CA1103364A (en) * 1977-04-25 1981-06-16 Raymond A. Grudowski Programmable controller with integral microprocessor
DE3101270C2 (en) * 1981-01-16 1985-07-25 Christian Dipl.-Ing. 8000 München Nitschke Computer arrangement for word processing with a device for expanding functions
DD266719A3 (en) * 1983-08-02 1989-04-12 Numerik Karl Marx Veb PROGRAM CONTROL ARRANGEMENT FOR CONTROLLING MACHINES AND PROCESSES
JPH0827645B2 (en) * 1987-04-27 1996-03-21 株式会社東芝 Programmable controller
DE3718639A1 (en) * 1987-06-04 1988-12-22 Kloeckner Moeller Elektrizit Method and circuit arrangement for driving two or more microprocessors in parallel operation, particularly in stored program control units
JP2530380B2 (en) * 1990-04-02 1996-09-04 株式会社日立製作所 Process control method and control controller

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0237680A2 (en) * 1986-02-17 1987-09-23 Tektronix, Inc. Event distribution and combination system
EP0237680A3 (en) * 1986-02-17 1988-11-09 Tektronix, Inc. Event distribution and combination system
EP0290121A1 (en) * 1987-04-21 1988-11-09 Tektronix Inc. Improved event distribution and combination system
EP0362819A2 (en) * 1988-10-05 1990-04-11 Kabushiki Kaisha Toshiba Programmable controller
EP0362819A3 (en) * 1988-10-05 1990-11-28 Kabushiki Kaisha Toshiba Programmable controller
EP0539115A2 (en) * 1991-10-24 1993-04-28 Hitachi, Ltd. Programmable controller and sequence control method
EP0539115A3 (en) * 1991-10-24 1994-11-09 Hitachi Ltd Programmable controller and sequence control method
US5504930A (en) * 1991-10-24 1996-04-02 Hitachi, Ltd. Programmable controller and sequence control method
FR2695739A1 (en) * 1992-09-15 1994-03-18 April Automates Sa Data treatment process for e.g. robot, automatic machine - uses memory area to store boolean data on robot inputs and outputs for treatment by co-processor

Also Published As

Publication number Publication date
DE2522343C3 (en) 1979-03-08
DE2522343A1 (en) 1976-12-02
DE2522343B2 (en) 1977-03-17
FR2312061B3 (en) 1979-02-02

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