FR1378131A - Procédé de formation de modèle dans une couche épitaxique de semiconducteur et dispositifs ainsi fabriqués - Google Patents

Procédé de formation de modèle dans une couche épitaxique de semiconducteur et dispositifs ainsi fabriqués

Info

Publication number
FR1378131A
FR1378131A FR947228A FR947228A FR1378131A FR 1378131 A FR1378131 A FR 1378131A FR 947228 A FR947228 A FR 947228A FR 947228 A FR947228 A FR 947228A FR 1378131 A FR1378131 A FR 1378131A
Authority
FR
France
Prior art keywords
fabricated
devices
semiconductor layer
pattern formation
epitaxial semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR947228A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Corp
Original Assignee
Fairchild Camera and Instrument Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Camera and Instrument Corp filed Critical Fairchild Camera and Instrument Corp
Priority to FR947228A priority Critical patent/FR1378131A/fr
Priority claimed from US374027A external-priority patent/US3260902A/en
Application granted granted Critical
Publication of FR1378131A publication Critical patent/FR1378131A/fr
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/761PN junctions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
FR947228A 1962-10-05 1963-09-11 Procédé de formation de modèle dans une couche épitaxique de semiconducteur et dispositifs ainsi fabriqués Expired FR1378131A (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR947228A FR1378131A (fr) 1962-10-05 1963-09-11 Procédé de formation de modèle dans une couche épitaxique de semiconducteur et dispositifs ainsi fabriqués

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US22857662A 1962-10-05 1962-10-05
FR947228A FR1378131A (fr) 1962-10-05 1963-09-11 Procédé de formation de modèle dans une couche épitaxique de semiconducteur et dispositifs ainsi fabriqués
US374027A US3260902A (en) 1962-10-05 1964-06-10 Monocrystal transistors with region for isolating unit

Publications (1)

Publication Number Publication Date
FR1378131A true FR1378131A (fr) 1964-11-13

Family

ID=27247457

Family Applications (1)

Application Number Title Priority Date Filing Date
FR947228A Expired FR1378131A (fr) 1962-10-05 1963-09-11 Procédé de formation de modèle dans une couche épitaxique de semiconducteur et dispositifs ainsi fabriqués

Country Status (1)

Country Link
FR (1) FR1378131A (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1297763B (de) * 1964-07-18 1969-06-19 Fujitsu Ltd Verfahren zum Herstellen eines Transistors fuer sehr hohe Frequenzen
FR2042556A1 (fr) * 1969-05-12 1971-02-12 Eastman Kodak Co

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1297763B (de) * 1964-07-18 1969-06-19 Fujitsu Ltd Verfahren zum Herstellen eines Transistors fuer sehr hohe Frequenzen
FR2042556A1 (fr) * 1969-05-12 1971-02-12 Eastman Kodak Co

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