FI981226A - Symbol Synchronization Method - Google Patents
Symbol Synchronization Method Download PDFInfo
- Publication number
- FI981226A FI981226A FI981226A FI981226A FI981226A FI 981226 A FI981226 A FI 981226A FI 981226 A FI981226 A FI 981226A FI 981226 A FI981226 A FI 981226A FI 981226 A FI981226 A FI 981226A
- Authority
- FI
- Finland
- Prior art keywords
- synchronization method
- symbol synchronization
- symbol
- synchronization
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0334—Processing of samples having at least three levels, e.g. soft decisions
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
- H04L27/22—Demodulator circuits; Receiver circuits
- H04L27/233—Demodulator circuits; Receiver circuits using non-coherent demodulation
- H04L27/2332—Demodulator circuits; Receiver circuits using non-coherent demodulation using a non-coherent carrier
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FI981226A FI106502B (en) | 1998-05-29 | 1998-05-29 | Symbol synchronization method |
AU45170/99A AU4517099A (en) | 1998-05-29 | 1999-05-27 | Symbol synchronizing method |
PCT/FI1999/000456 WO1999063721A1 (en) | 1998-05-29 | 1999-05-27 | Symbol synchronizing method |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FI981226 | 1998-05-29 | ||
FI981226A FI106502B (en) | 1998-05-29 | 1998-05-29 | Symbol synchronization method |
Publications (3)
Publication Number | Publication Date |
---|---|
FI981226A0 FI981226A0 (en) | 1998-05-29 |
FI981226A true FI981226A (en) | 1999-11-30 |
FI106502B FI106502B (en) | 2001-02-15 |
Family
ID=8551862
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FI981226A FI106502B (en) | 1998-05-29 | 1998-05-29 | Symbol synchronization method |
Country Status (3)
Country | Link |
---|---|
AU (1) | AU4517099A (en) |
FI (1) | FI106502B (en) |
WO (1) | WO1999063721A1 (en) |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3399013B2 (en) * | 1993-04-02 | 2003-04-21 | 株式会社デンソー | Digital phase modulation signal demodulator |
FI94818C (en) * | 1993-06-02 | 1995-10-25 | Nokia Telecommunications Oy | A method for demodulating a digitally modulated signal and a demodulator |
JP3390272B2 (en) * | 1994-11-10 | 2003-03-24 | 沖電気工業株式会社 | Synchronous detection circuit |
JPH1028149A (en) * | 1996-07-10 | 1998-01-27 | Matsushita Electric Ind Co Ltd | Clock recovery circuit |
-
1998
- 1998-05-29 FI FI981226A patent/FI106502B/en active
-
1999
- 1999-05-27 AU AU45170/99A patent/AU4517099A/en not_active Abandoned
- 1999-05-27 WO PCT/FI1999/000456 patent/WO1999063721A1/en active Application Filing
Also Published As
Publication number | Publication date |
---|---|
AU4517099A (en) | 1999-12-20 |
WO1999063721A1 (en) | 1999-12-09 |
FI981226A0 (en) | 1998-05-29 |
FI106502B (en) | 2001-02-15 |
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