FI843759L - FOERFARANDE FOER DRIFT AV EN MULTIPROCESSOR-STYRRAEKNARE, SAERSKILT FOER CENTRALSTYRENHETEN VID ETT TELEFONFOERMEDLINGSSYSTEM. - Google Patents
FOERFARANDE FOER DRIFT AV EN MULTIPROCESSOR-STYRRAEKNARE, SAERSKILT FOER CENTRALSTYRENHETEN VID ETT TELEFONFOERMEDLINGSSYSTEM.Info
- Publication number
- FI843759L FI843759L FI843759A FI843759A FI843759L FI 843759 L FI843759 L FI 843759L FI 843759 A FI843759 A FI 843759A FI 843759 A FI843759 A FI 843759A FI 843759 L FI843759 L FI 843759L
- Authority
- FI
- Finland
- Prior art keywords
- special
- cmy
- processor
- foer
- inherently
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q3/00—Selecting arrangements
- H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
- H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
- H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
- H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
- H04Q3/5455—Multi-processor, parallelism, distributed systems
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q3/00—Selecting arrangements
- H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
- H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
- H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
- H04Q3/54508—Configuration, initialisation
- H04Q3/54516—Initialization, software or data downloading
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/1305—Software aspects
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13109—Initializing, personal profile
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13376—Information service, downloading of information, 0800/0900 services
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Hardware Redundancy (AREA)
- Exchange Systems With Centralized Control (AREA)
- Storage Device Security (AREA)
- Executing Machine-Instructions (AREA)
- Pyridine Compounds (AREA)
- Multi Processors (AREA)
- Memory System (AREA)
Abstract
Method for the operation of a multiprocessor controller, at least some of the processors (BP, CP, IOC, IOP) having access via first switches (S) and thus via each half (B:CMY0, B:CMY1) of a central inherently duplicated bus system (B:CMY) and second switches (SW) connected thereto to each half of an inherently duplicated main memory (CMY), or to each half (e.g. MB3a or MB3b) of one or more inherently duplicated memory banks (MB) of the main memory (CMY). In a special operating time, a redundant part of the controller is separated and interconnected to form a small, discrete, independently operating special processor by interconnecting individual redundant processors of this group (e.g. CP9 and/or IOC1) to one half (e.g. B:CMY1) of the bus system (B:CMY) and to a part of the main memory (CMY) or the memory banks (MB) in order to form an independent special processor for a special program, and continuing to run the so far normally operating program in the remaining parts of the controller, that is to say in the residual processor. The special processor later interrupts its special program. The components of the special processor are reconnected to the residual processor in such a way that only the normal operating program or a newly input modification thereof runs. <IMAGE>
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19833334796 DE3334796A1 (en) | 1983-09-26 | 1983-09-26 | METHOD FOR OPERATING A MULTIPROCESSOR CONTROLLER, ESPECIALLY FOR THE CENTRAL CONTROL UNIT OF A TELECOMMUNICATION SWITCHING SYSTEM |
DE3334796 | 1983-09-26 |
Publications (4)
Publication Number | Publication Date |
---|---|
FI843759A0 FI843759A0 (en) | 1984-09-25 |
FI843759L true FI843759L (en) | 1985-03-27 |
FI88219B FI88219B (en) | 1992-12-31 |
FI88219C FI88219C (en) | 1993-04-13 |
Family
ID=6210097
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FI843759A FI88219C (en) | 1983-09-26 | 1984-09-25 | Method of operating a multiprocessor controller, especially for the central controller of a telephone switching system |
Country Status (6)
Country | Link |
---|---|
EP (1) | EP0141246B1 (en) |
JP (1) | JPH0666985B2 (en) |
AT (1) | ATE63029T1 (en) |
DE (2) | DE3334796A1 (en) |
FI (1) | FI88219C (en) |
ZA (1) | ZA847567B (en) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3334796A1 (en) * | 1983-09-26 | 1984-11-08 | Siemens AG, 1000 Berlin und 8000 München | METHOD FOR OPERATING A MULTIPROCESSOR CONTROLLER, ESPECIALLY FOR THE CENTRAL CONTROL UNIT OF A TELECOMMUNICATION SWITCHING SYSTEM |
DE3629399A1 (en) * | 1986-08-29 | 1988-03-03 | Siemens Ag | Method for operating the central memory of a multiprocessor-type common control unit of a switching system |
WO1988007314A1 (en) * | 1987-03-19 | 1988-09-22 | Siemens Aktiengesellschaft | Process for operating a multiprocessor central control unit of a relay system |
CA2003338A1 (en) * | 1987-11-09 | 1990-06-09 | Richard W. Cutts, Jr. | Synchronization of fault-tolerant computer system having multiple processors |
AU616213B2 (en) * | 1987-11-09 | 1991-10-24 | Tandem Computers Incorporated | Method and apparatus for synchronizing a plurality of processors |
US4965717A (en) * | 1988-12-09 | 1990-10-23 | Tandem Computers Incorporated | Multiple processor system having shared memory with private-write capability |
US5295258A (en) | 1989-12-22 | 1994-03-15 | Tandem Computers Incorporated | Fault-tolerant computer system with online recovery and reintegration of redundant components |
US6950893B2 (en) * | 2001-03-22 | 2005-09-27 | I-Bus Corporation | Hybrid switching architecture |
KR101131306B1 (en) | 2004-06-30 | 2012-03-30 | 엘지디스플레이 주식회사 | Back light unit of liquid crystal display device |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2232256A5 (en) * | 1973-05-29 | 1974-12-27 | Labo Cent Telecommunicat | |
US4363094A (en) * | 1977-12-29 | 1982-12-07 | M/A-COM DDC, Inc. | Communications processor |
DE3334773A1 (en) * | 1983-09-26 | 1984-11-08 | Siemens AG, 1000 Berlin und 8000 München | METHOD FOR OPERATING A PAIR OF MEMORY BLOCKS OPERATING IN NORMAL OPERATING TIME |
DE3334796A1 (en) * | 1983-09-26 | 1984-11-08 | Siemens AG, 1000 Berlin und 8000 München | METHOD FOR OPERATING A MULTIPROCESSOR CONTROLLER, ESPECIALLY FOR THE CENTRAL CONTROL UNIT OF A TELECOMMUNICATION SWITCHING SYSTEM |
-
1983
- 1983-09-26 DE DE19833334796 patent/DE3334796A1/en not_active Withdrawn
-
1984
- 1984-09-25 AT AT84111429T patent/ATE63029T1/en not_active IP Right Cessation
- 1984-09-25 FI FI843759A patent/FI88219C/en not_active IP Right Cessation
- 1984-09-25 DE DE8484111429T patent/DE3484496D1/en not_active Expired - Fee Related
- 1984-09-25 EP EP84111429A patent/EP0141246B1/en not_active Expired - Lifetime
- 1984-09-26 JP JP59199701A patent/JPH0666985B2/en not_active Expired - Fee Related
- 1984-09-26 ZA ZA847567A patent/ZA847567B/en unknown
Also Published As
Publication number | Publication date |
---|---|
FI843759A0 (en) | 1984-09-25 |
FI88219C (en) | 1993-04-13 |
JPH0666985B2 (en) | 1994-08-24 |
ATE63029T1 (en) | 1991-05-15 |
ZA847567B (en) | 1985-05-29 |
EP0141246A3 (en) | 1988-02-10 |
JPS60102089A (en) | 1985-06-06 |
EP0141246A2 (en) | 1985-05-15 |
FI88219B (en) | 1992-12-31 |
DE3484496D1 (en) | 1991-05-29 |
DE3334796A1 (en) | 1984-11-08 |
EP0141246B1 (en) | 1991-04-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
AU585076B2 (en) | Interrupt handling in a multiprocessor computing system | |
SE8603945L (en) | PROCEDURE FOR CONTINUOUS SWITCHING BETWEEN ACTIVE AND EMERGENCY DEVICES OF A COMPUTER EQUIPMENT AND DEVICE FOR IMPLEMENTATION OF THE PROCEDURE | |
GB0007412D0 (en) | Information processing system | |
FI843759L (en) | FOERFARANDE FOER DRIFT AV EN MULTIPROCESSOR-STYRRAEKNARE, SAERSKILT FOER CENTRALSTYRENHETEN VID ETT TELEFONFOERMEDLINGSSYSTEM. | |
DE69317507D1 (en) | Fault-tolerant computer system with a fault detector provided in each processor module | |
ATE63189T1 (en) | MULTIPROCESSOR COMPUTER, IN PARTICULAR MULTIPROCESSOR CENTRAL CONTROL UNIT OF A TELEPHONE SWITCHING SYSTEM. | |
EP0230512A3 (en) | Method for resolving conflicts between interrupt sources sharing the same priority | |
KR950035209A (en) | Horizontally distributed network system and multiprocessor system | |
JPS575162A (en) | Redundant system controller | |
EP0274715A3 (en) | Method for load distribution among the central processors of the multiprocessor's central control unit of a switching system | |
GB1531334A (en) | Switching system | |
JPS5819973A (en) | Multiprocessor computer of time division bus system | |
JPS57111639A (en) | Program debugging system | |
JPS54150939A (en) | Bus control system | |
SU1010734A1 (en) | Device for control of switching-over of reserve | |
JPS6126145A (en) | Controlling method of integration data | |
JPS56145452A (en) | Control system for power source fault of multiprocessor processing system | |
JPS6459434A (en) | Input/output control system for virtual computer | |
GB2303234B (en) | Information processing system | |
JPS56108161A (en) | Operation control system for multiprocessor | |
JPS56121169A (en) | Duplex system of computer | |
JPS60138652A (en) | Memory bank switching system | |
JPS5829032A (en) | Data transfer system | |
JPS643741A (en) | Recovery control system for virtual computer system | |
JPS55105728A (en) | Composite computer system |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM | Patent lapsed |
Owner name: SIEMENS AKTIENGESELLSCHAFT |