FI20205765A1

FI20205765A1 - Method for manufacturing n-type crystalline silicon cell

Info

Publication number: FI20205765A1
Application number: FI20205765A
Authority: FI
Inventors: Zhichun Ni; Zhi Yang; Shude Zhang; Qingzhu Wei
Original assignee: Suzhou Talesun Solar Tech Co Ltd
Priority date: 2019-07-24
Filing date: 2020-04-03
Publication date: 2021-01-25
Also published as: CN110571302A; WO2021012710A1

Abstract

The invention discloses a method for manufacturing an N-type crystalline silicon cell, comprising the following steps in sequence: A. doping boron in one surface of a textured N-type crystalline silicon wafer (5); B. placing the boron-doped N-type crystalline silicon wafer (5) in a first solution for treatment in a floating mode while keeping the boron-doped surface upward; C. growing an oxide thin layer (6) on the other surface of the N-type crystalline silicon wafer (5); D. depositing a polysilicon layer (7) on the oxide thin layer (6) and doping phosphorus element; E. placing the N-type crystalline silicon wafer (5) in a second solution for treatment in a floating mode while keeping the phosphorus-doped surface upward; F. placing the N-type crystalline silicon wafer (5) treated by the second solution in an alkaline solution for treatment; G. removing a phosphosilicate glass and borosilicate glass on the surfaces of the N-type crystalline silicon wafer (5); H. oxidizing the surfaces of the N-type crystalline silicon wafer (5); I. depositing a passivation anti-reflection layer (2) and a passivation layer (8) on the surface of the N-type crystalline silicon wafer (5); J. performing a metallization process. The above preparation method solves the problem of electric leakage in N-type crystalline silicon cells.

Description

PCT/CN2020/083205 ChinableIP Ref.: OP2020439FI METHOD FOR MANUFACTURING N-TYPE CRYSTALLINE SILICON

CELL

[0001] The present application claims priority to Chinese Patent Application No.

201910671184.7 filed on July 24, 2019 in the China National Intellectual Property Administration, which is incorporated herein by reference in its entirety.

FIELD OF TECHNOLOGY

[0002] The invention belongs to the field of solar cells, and relates to a method for manufacturing an N-type crystalline silicon cell.

BACKGROUND

[0003] Conventional fossil fuels are increasingly depleted. Among all sustainable energy sources, solar energy is undoubtedly the cleanest, most common, and most potential alternative energy source. Currently, silicon solar cells occupy an important position in the field of photovoltaics, because the silicon material has extremely rich reserves in the earth's crust and, silicon solar cells have excellent electrical and mechanical properties compared to other types of solar cells. Therefore, the development of cost-effective silicon solar cells has become the major research 9 direction of photovoltaic companies in various countries. N 20 [0004] The silicon wafer substrates used in the existing silicon solar cells mainly

NN ? include P-type and N-type silicon wafers. However, light induced degradation(LID) - phenomenon generally occurs in P-type mono-crystalline silicon, because the presence a + of boron-oxygen complex defects and carbon-oxygen complex defects in the P-type

LO = mono-crystalline silicon reduce the lifetime and diffusion length of the minority carriers, N 25 so that the conversion efficiency of the cell is reduced. Compared to a solar cell that is

N fabricated by using a P-type silicon wafer as a substrate, a solar cell fabricated by using a N-type silicon wafer as a substrate has no obvious LID phenomenon because no 1

PCT/CN2020/083205 ChinableIP Ref.: OP2020439FI boron-oxygen complex exist in a N-type silicon wafer. The lifetime of the minority carriers in the N-type silicon wafer is longer than that of a P-type silicon wafer, so N-type silicon solar cells are getting more and more attention.

[0005] Existing crystalline silicon solar cells mainly include single-surface solar cells and double-surface solar cells. Sunlight absorption and photoelectric conversion can only be performed on the front side of the single-surface solar cell, as the back side of the cell is covered with metal aluminum. Thus, the sunlight that has reached the back side of the cell through a way such as reflection and scattering is blocked by the metal aluminum and cannot penetrate the metal aluminum to reach the silicon substrate, so that the sunlight reaching the back side of the cell cannot be effectively absorbed. In order to further improve the sunlight absorption of crystalline silicon solar cells, the photovoltaic industry gradually begin to develop a crystalline silicon solar cell that can absorb sunlight on both sides, that is, a crystalline silicon double-surface solar cell.

[0006] The back side of currently popular N-type crystalline silicon double-surface cell is a phosphorus-doped surface, which is mainly passivated by SiOx and SiNx. Although a better passivation effect can be achieved in the non-metallic area of the back side, there are still relatively high recombination of carriers in the metallized area. Such the high recombination of carriers limits further improvement of the photoelectric conversion efficiency of crystalline silicon solar cells. In order to continue improving the photoelectric conversion efficiency of crystalline silicon solar cells, a carrier-selective structure can be used to reduce the carrier recombination in the metallized area and 9 further reduce the recombination in the non-metallic area on the back side of the N-type N crystalline silicon double-surface cell. S [0007] However, when the carrier-selective structure is prepared on the back side of N 25 an N-type crystalline silicon cell, the doping elements will diffract to the undoped surface a during the doping process whether an in-situ doping method or a thermal diffusion 5 doping method is used, which induces that the positive electrode and negative N electrode of the cell are directly connected together without being insulated, and leads - to an electric leakage.

SUMMARY 2

PCT/CN2020/083205 ChinableIP Ref.: OP2020439FI

[0008] For the above technical problems, the present invention aims to provide a method for manufacturing an N-type crystalline silicon cell, which solves the problem of electric leakage of an N-type crystalline silicon cell that has a carrier-selective structure on its back side.

[0009] In order to achieve the above objectives, the present invention has adopted the following technical solutions.

[0010] A method for manufacturing an N-type crystalline silicon cell includes the following steps in seguence: A. A boron-doping process is performed on a surface of a textured N-type crystalline silicon wafer; B. The boron-doped N-type crystalline silicon wafer is placed in a first solution for treatment in a floating mode while keeping the boron-doped surface upward. The first solution includes a mixed solution comprising HF and HNOj;, or a mixed solution comprising HF, HNO3 and HS Oy; C. An oxide thin layer is grown on the other surface of the N-type crystalline silicon wafer; D. A polysilicon layer is deposited on the oxide thin layer and doped with phosphorus element; E. The N-type crystalline silicon wafer is placed in a second solution for treatment in a floating mode with keeping the phosphorus-doped surface upward. The second solution comprises HF; > F. The N-type crystalline silicon wafer treated by the second solution is placed in an S alkaline solution for treatment;

K <Q G The phosphosilicate glass and borosilicate glass on the surfaces of the N-type

N N 25 crystalline silicon wafer treated by the alkaline solution are removed;

I a - H. The surfaces of the N-type crystalline silicon wafer treated in the step G are

LO 2 oxidized;

S S I. Afirst passivation anti-reflection layer is deposited on the boron-doped surface of the

N N-type crystalline silicon wafer, and a second passivation anti-reflection layer is deposited on the phosphorus-doped surface of the N-type crystalline silicon wafer; 3

PCT/CN2020/083205 ChinableIP Ref.: OP2020439FI J. A metallization process is performed to form a front metal electrode and a back metal electrode.

[0011] Preferably, in the step B, a water film is firstly formed on the boron-doped surface of the N-type crystalline silicon wafer, and then the N-type crystalline silicon wafer is placed in the first solution for treatment in a floating mode; in the step E, a water film is firstly formed on the phosphorus-doped surface of the N-type crystalline silicon wafer, and then the N-type crystalline silicon wafer is placed in the second solution for treatment in a floating mode. Specifically, the water films are formed by spraying.

[0012] In a preferred embodiment, the step B is specifically implemented as follows: — the water film is formed on the boron-doped surface of the N-type crystalline silicon wafer, and then the N-type crystalline silicon wafer is conveyed via a chain conveyer device so as to pass through the first solution in a floating mode while keeping the boron-doped surface upward.

[0013] More preferably, the first solution is a mixed solution comprising HF, HNO3 and deionized water, or is a mixed solution comprising HF, HNO3, H2S04 and deionized water; and the chain conveyer device has a conveying speed of 1.8m/s to 2.2m/s. Specifically, the volume ratio of HF, HNO3, H2SO4 and deionized water is (10-20) : (80~130) : (40-60) : 100.

[0014] Furthermore, the chain conveyer device has a conveying speed in a range from

1.8m/sto2.2 m/s.

[0015] Preferably, the step E is specifically implemented as follows: a water film is formed on the phosphorus-doped surface of the N-type crystalline silicon wafer, and then o the N-type crystalline silicon wafer is conveyed via a chain conveyer device so as to pass N through the second solution in a floating mode while keeping the phosphorus-doped S 25 surface upward. Specifically, the water film is formed by spraying. N [0016] More preferably, the second solution is a solution comprising HF and deionized E water, the volume concentration of HF in the second solution is in a range from 3% to 7%, & and the conveying speed of the chain conveyer device is in a range from 1.6 m/s to 2.0

LO 3 m/s.

[0017] Preferably, the alkaline solution in the step F is NaOH, KOH, TMAH or NH4OH. More preferably, the alkaline solution is KOH solution with a volume concentration of 2% to 5%. 4

PCT/CN2020/083205 ChinableIP Ref.: OP2020439FI

[0018] Preferably, the oxide thin layer in the step C is a silicon oxide thin layer; in the step D, phosphorus element is doped during the deposition of the polysilicon layer or after the deposition of the polysilicon layer.

[0019] Preferably, the step H is specifically implemented as follows: the N-type crystalline silicon wafer is oxidized, next the oxide on the surfaces is removed, and then the surfaces of the N-type crystalline silicon wafer are oxidized.

[0020] More preferably, in the step H, the N-type crystalline silicon wafer is firstly oxidized by an ozone solution or a HNO; solution, and placed in a HF solution to remove the oxide layers on the surfaces, and then the surfaces of the N-type crystalline silicon — are oxidized by the ozone solution or the HNO; solution again.

[0021] Preferably, the water film formed on the boron-doped surface has a thickness ranging from 0.1 mm to 5 mm, and the chain conveyer device has a conveying speed ranging from 1.8 m/s to 4.2 m/s.

[0022] Preferably, the water film formed on the phosphorus-doped surface has a thickness ranging from 0.1 mm to 5 mm, and the chain conveyer device has a conveying speed ranging from 1.8 m/s to 4.2 m/s.

[0023] Preferably, if the first solution is a mixed solution comprising HF and HNO3, the volume ratio of HF and HNO; is 1 : (5~8), wherein, the volume concentration of HF is 49%, and the volume concentration of HNO3 is 68%.

[0024] Preferably, if the first solution is a mixed solution comprising HF, HNO; and H2SO4, the volume ratio of HF, HNO3 and H2SOs is (10-20) : (80~130) : (40-60), wherein, the volume concentration of HF is 49%, the volume concentration of HNO3 is N 68%, and the volume concentration of HSO4 is 96%.

N N [0025] In a specific and preferred embodiment, the preparation method includes the N 25 following steps in sequence: E (1) A texturing process (a pyramidal texture surface is formed on the surface) to a 10 N-type crystalline silicon wafer is performed;

N S (2) A boron-doping process is performed on a surface of the textured N-type crystalline silicon wafer; (3) A water film is formed on the boron-doped surface of the silicon wafer doped with boron, and then the silicon wafer is passed through a first solution in a floating mode 5

PCT/CN2020/083205 ChinableIP Ref.: OP2020439FI while keeping the doped surface upward by using a chain conveyer, wherein, the first solution contains HF, deionized water, HNO; and H>SOi;; (4) A SiOx thin layer is grown on the back side of the N-type crystalline silicon wafer; (5) A polysilicon layer is deposited on the back side of the N-type crystalline silicon wafer; (6) Phosphorus element is doped in-situ during the deposition of the polysilicon layer or after the deposition process of the polysilicon layer; (7) A water film is formed on the phosphorus-doped surface of the N-type crystalline silicon wafer doped with phosphorus, and then the N-type crystalline silicon wafer is passed through a second solution in a floating mode while keeping the phosphorus-doped surface upward by using a chain conveyer, wherein, the second solution contains HF; (8) The N-type crystalline silicon wafer is placed in an alkaline solution, and is removed the doped layers at the edges of the silicon wafer by the reaction of the alkaline solution with silicon in order to prevent from electric leakage; the alkaline solution may contain deionized water and at least one of NaOH, KOH, TMAH or NH4OH; (9) The N-type crystalline silicon wafer is placed in a mixed solution of HF and deionized water to remove the phosphosilicate glass and borosilicate glass on the surfaces: (10) The N-type crystalline silicon wafer is oxidized, and the oxidation process can be implemented with an ozone solution or a HNO; solution; > (11) The N-type crystalline silicon wafer is placed in a mixed solution of HF and S deionized water to remove the oxide layers on the surfaces;

K <Q (12) The surfaces of the N-type crystalline silicon wafer are oxidized, and the oxidation

N N 25 process can be implemented with an ozone solution or a HNO3 solution;

I a - (13) An aluminum oxide layer is deposited on the boron-doped surface of the N-type

LO = crystalline silicon wafer;

O O (14) A SiNx layer is deposited on the boron-doped surface and the phosphorus-doped surface of the N-type crystalline silicon wafer, respectively; (15) A metallization process is performed on the surfaces of the N-type crystalline 6

PCT/CN2020/083205 ChinableIP Ref.: OP2020439FI silicon wafer.

[0026] Compared with the prior art, the present invention that has adopted the above schemes has the following advantages.

[0027] The method for manufacturing the N-type crystalline silicon cell of the present invention can solve the electric leakage problem of the cell edges and significantly reduce the electric leakage for reverse voltage of the N-type crystalline silicon cell on the basis of effectively protecting the boron-doped surface and the phosphorus-doped surface of an N-type crystalline silicon cell; the preparation method is simple and suitable for popularization and application.

BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The drawings required in the description of the embodiments will be briefly introduced below in order to describe the technical solutions of the present invention more clearly. It would have been obvious that the drawings in the following description are only some embodiments of the present invention, and based on these drawings, those of ordinary skill in the art can obtain other drawings without any creative work.

[0029] FIG 1 is a schematic structural diagram of a boron-doped N-type crystalline silicon wafer in an embodiment of the present application;

[0030] FIG 2 is a schematic structural diagram of an N-type crystalline silicon wafer in which the boron silicon oxide formed on the back and side surfaces of FIG. 1 is removed;

[0031] FIG 3 is a schematic structural diagram of a phosphorus-doped N-type crystalline silicon wafer in an embodiment of the present application;

O N [0032] FIG 4 is a schematic structural diagram of an N-type crystalline silicon wafer in

N NM which the phosphorus silicon oxide formed on the side surfaces of FIG. 3 is removed;

O N [0033] FIG 5 is a schematic structural diagram of an N-type crystalline silicon wafer E 25 — obtained by placing the silicon wafer of FIG. 4 into an alkaline solution for treatment; 2 [0034] FIG 6 is a schematic structural diagram of an N-type crystalline silicon cell

N 2 prepared according to an embodiment of the present application;

QA

O N [0035] FIG7 is a schematic structural diagram of an N-type crystalline silicon cell prepared in Example 1.

PCT/CN2020/083205 ChinableIP Ref.: OP2020439FI

[0036] Herein: 1. Front metal electrode; 2. SiNx layer; 3. AlOx layer; 4. Boron-doped layer; 5. N-type crystalline silicon wafer; 6. SiO, layer; 7. polysilicon layer; 8. SiNx layer;

9. Back metal electrode.

DESCRIPTION OF THE EMBODIMENTS

[0037] Hereinafter, the preferred embodiments of the present invention are described in detail in conjunction with the accompanying drawings in order to make the advantages and features of the present invention easier to be understood by those skilled in the art. It should be noted that the description of these embodiments is used to facilitate understanding of the present invention, but does not limit the present invention. In addition, the technical features described below that are involved in the various embodiments of the present invention can be combined if they do not conflict with each other.

[0038] The embodiments of the present application provide a method for manufacturing an N-type crystalline silicon cell, and the method includes the following — steps.

[0039] Step 1: Aboron-doping process is performed on a surface of the textured N-type crystalline silicon wafer 5.

[0040] That is, in step 1, the boron-doping process is performed on single surface of the textured N-type crystalline silicon wafer 5.

[0041] In the embodiments of the present application, the texturing method for the N-type crystalline silicon wafer 5 may be any feasible method in the prior art, which is not S limited in the present application. For example, the front surface of the N-type crystalline N silicon wafer 5 can be immersed in a texturing solution comprising KOH, a texturing 5 additive and deionized water. After etching, an uneven texture surface, for example, a AN 25 pyramidal texture surface, is formed on the front surface of the N-type crystalline silicon E wafer 5. The texturing process on the surface of the N-type crystalline silicon wafer 5 10 mainly aims to reduce the reflectance of sunlight on the N-type crystalline silicon wafer 5 5 and increase the absorption of sunlight by the N-type crystalline silicon wafer 5. The O volume concentration of KOH in the texturing solution can be in a range from 1% to 10%, and the texturing time can be in a range from 500 to 2000 seconds. More preferably, the volume concentration of KOH in the texturing solution is 3%, and the texturing time is 8

PCT/CN2020/083205 ChinableIP Ref.: OP2020439FI 800 seconds. When the volume concentration of KOH in the texturing solution is 3% and the texturing time is 800 seconds, the degree of etching on the N-type crystalline silicon wafer by the texturing solution can be better controlled, so that an ideal texture surface can be obtained.

[0042] In the embodiments of the present application, any feasible boron-doping method in the prior art may be used, which is not limited in the present application. For example, the boron-doping process can be performed by a thermal diffusion method. After the textured surface of the N-type crystalline silicon wafer 5 is doped with boron element, a boron-doped surface is formed on the textured surface of the N-type — crystalline silicon wafer 5.

[0043] In the embodiments of the present application, for convenience of description, the surface treated by a single-surface doping of boron in the N-type crystalline silicon wafer 5 is called the front surface, and the other surface is called the back surface.

[0044] It should also be noted that no matter which the doping methods in the prior art is used, gas is generally needed to assist doping. For example, in a thermal diffusion method, the N-type crystalline silicon wafer 5 is placed in a diffusion furnace and warmed to a preset temperature, and a boron source, oxygen and nitrogen are fed to deposit on a surface of the N-type crystalline silicon wafer 5. Specifically, the doping source, i.e., the boron source, may be N, that carries BBrs, wherein the flow rate of Na that carries BBr3 may be 150 sccm, the flow rate of nitrogen that does not carry the source may be 30 SLM, the flow rate of oxygen may be 600 sccm, the source supplying time may be 25 min, and the temperature of thermal diffusion may be 900 *C. It can be seen that, as shown in Fig. 1, during the boron-doping process on the front surface of the N-type N crystalline silicon wafer 5, as a result of the action of gases, not only the front surface of . 25 the N-type crystalline silicon wafer is doped with the boron element to form a = boron-doped surface, but the back surface and side surfaces (i.e., the edges of the - N-type crystalline silicon wafer) of the N-type crystalline silicon wafer may also be doped E with some boron element, so that a boron silicon oxide layer may be formed on both of & the back surface and side surfaces. In addition, a boron-silicon impurity layer may further S 30 exist between the back surface of the N-type crystalline silicon wafer and the boron N silicon oxide layer and between the side surface of the N-type crystalline silicon wafer and the boron silicon oxide layer. 9

PCT/CN2020/083205 ChinableIP Ref.: OP2020439FI

[0045] Step 2: The boron-doped N-type crystalline silicon wafer is placed in a first solution for treatment in a floating mode, while keeping the boron-doped surface upward. The first solution includes a mixed solution comprising HF and HNO3, or a mixed solution comprising HF, HNO3 and H2S04.

[0046] In order to eliminate the influence of boron-doping on the back and side surfaces of the N-type crystalline silicon wafer in step 1, the boron silicon oxide and boron-silicon impurity layers formed on the back and side surfaces of the N-type crystalline silicon wafer are firstly removed in step 2 so as to obtain the structure shown in Fig. 2. Specifically, the boron-doped N-type crystalline silicon wafer prepared in step 1 is subjected to floating in the first solution, wherein the boron-doped surface of the N-type crystalline silicon wafer does not contact the first solution. As a feasible way, the first solution is placed in a holding tank in which a chain conveyer device is disposed, and the boron-doped N-type crystalline silicon wafer is placed on the chain conveyer device. Wherein, the boron-doped surface faces upward and does not contact the first solution, so that the first solution is only in contact with the back and side surfaces of the N-type crystalline silicon wafer.

[0047] The first solution is used to remove the boron silicon oxide and boron-silicon impurity layers formed on the back and side surfaces of the N-type crystalline silicon wafer. The first solution may be a mixed solution comprising HF and HNO3, or a mixed — solution comprising HF, HNO3 and H>S04.

[0048] If the first solution is the mixed solution comprising HF and HNO3, the corresponding volume ratio of HF and HNO; is 1 : (5-8), wherein the volume concentration of HF is 49% and the volume concentration of HNO3 is 68%. HF is mainly N used to remove the boron silicon oxide formed on the back and side surfaces of the . 25 N-type crystalline silicon wafer, and HNO; is mainly used to remove the boron-silicon N impurity layers formed on the back and side surfaces of the N-type crystalline silicon I wafer. When the volume ratio of HF and HNO; is 1 : (5~8), the reaction rate of the first E solution with the boron silicon oxide and boron-silicon impurity layers on the back and & side surfaces of the N-type crystalline silicon wafer can be well controlled to meet S 30 requirements of large-scale industrial production. - [0049] If the first solution is a mixed solution comprising HF, HNO; and H,SO,, the corresponding volume ratio of HF, HNO3 and H2SO4 is (10-20) : (80-130) : (40-60), 10

PCT/CN2020/083205 ChinableIP Ref.: OP2020439FI wherein, the volume concentration of HF is 49%, the volume concentration of HNO3 is 68%, and the volume concentration of H,SO4 is 96%. HF is mainly used to remove the boron silicon oxide formed on the back and side surfaces of the N-type crystalline silicon wafer, and HNO3 and H,SO4 are mainly used to remove the boron-silicon impurity layers formedon the back and side surfaces of the N-type crystalline silicon wafer. On the one hand, experimental data show that after the back and side surfaces of the N-type crystalline silicon wafer prepared in the step 1 are cleaned in a first solution containing H2SO4, the resultant cell can have a electric leakage of 0.03 A to 0.09 A for 12V reverse voltage. On the other hand, in the case that H,SO4 having the above volume concentration is used, the acidity of HNO; may be weakened in a certain degree by H2SO,, so that the etching rate of the boron-silicon impurity layers can be reduced.

[0050] Reducing the etching rate of the boron-silicon impurity layer can bring the following benefits: as an N-type crystalline silicon wafer can be conveyed via a chain conveyer device at a speed of 1.8 m/s to 4.2 m/s, if the first solution used is the mixed — solution comprising HF, HNO3 and H2S0O4, wherein the volume ratio of the above three is (10-20) : (80~130) : (40-60), and the volume concentration of HF is 49%, the volume concentration of HNO3 is 68%, and the volume concentration of H,SO4 is 96%, the boron-silicon impurity layers on the back and side surfaces of the obtained N-type crystalline silicon wafer is just completely removed without over etching, after the back and side surfaces of the N-type crystalline silicon wafer are treated in the first solution at the above conveying speed.

[0051] During the movement of the N-type crystalline silicon wafer driven by the chain conveyer device, if the conveying speed of the chain conveyer device exceeds 0.5 m/s, S the first solution will splash onto the front surface of the N-type crystalline silicon wafer, N 25 thereby destroying the boron silicon oxide on the boron-doped surface. Therefore, a = water film can be formed on the boron-doped surface firstly, and the N-type crystalline N silicon wafer is then treated in the first solution by using the conveying by the chain E: conveyer device in such a way that the back and side surfaces of the N-type crystalline & silicon wafer rather than the boron-doped surface are in contact with the first solution. In S 30 this way, the influence of the boron-doping process on the back and side surfaces of the N-type crystalline silicon wafer in step 1 can be eliminated, and the boron-doped surface can be protected from etching by the first solution. The method of forming the water film on the boron-doped surface of the N-type crystalline silicon wafer may be a water 11

PCT/CN2020/083205 ChinableIP Ref.: OP2020439FI spraying method, for example, a spray device is used to spray water on the boron-doped surface so as to form a water film.

[0052] In a preferred embodiment, the water film formed on the boron-doped surface has a thickness of 0.1 mm to 5 mm, and the chain conveyer device has a conveying speedof 1.8 m/s to 4.2 m/s.

[0053] If the thickness of the water film formed on the boron-doped surface is less than

0.1mm, the splashed first solution will damage the water film that has a thickness less than 0.1 mm during the movement of the N-type crystalline silicon wafer driven by the chain conveyer device, and then the boron-doped surface under the water film will be etched; if the thickness of the water film formed on the boron-doped surface is greater than 5 mm, the weight of the water film is so large that the water film will fall off from the boron-doped surface due to the inertia along with the rapid movement of the chain conveyer device, and the boron-doped surface under the water film will be etched by the splashed first solution. If the thickness of the water film formed on the boron-doped surface is between 0.1 mm and 5 mm, in the case that the conveying speed of the chain conveyer device is 1.8 ~ 4.2 m/s, the water film will not be damaged by the splashed first solution, and will not fall off automatically, thereby ensuring the guality and speed of the treatment in step 2 described above.

[0054] Step 3: An oxide thin layer 6 is prepared on the back surface of the N-type crystalline silicon wafer.

[0055] In the embodiments of the present application, the oxide thin layer 6 is mainly used to improve the conversion rate of solar energy. The oxide thin layer 6 may be a o silicon dioxide thin layer or molybdenum oxide thin layer, etc., which is not limited in this O application. S 25 [0056] The method for manufacturing the oxide thin layer is not limited to the N embodiments of the present application. For example, the oxide thin layer 6 can be E grown directly on the back surface of the N-type crystalline silicon wafer under a suitable 13 temperature and atmosphere condition; for another example, the oxide thin layer 6 can

N O be deposited on the back surface of the N-type crystalline silicon wafer.

QA

O N 30 [0057] In step 4, a polysilicon layer 7 is deposited on the oxide thin layer 6 and doped with phosphorus.

[0058] Polysilicon has relatively high conversion and mobility ratio, and its photoelectric 12

PCT/CN2020/083205 ChinableIP Ref.: OP2020439FI efficiency will not decay with the continuation of the illumination time.

[0059] Further, the phosphorus element may be doped during the deposition of the polysilicon layer 7 or after the deposition of the polysilicon layer 7.

[0060] First, it should be noted that in step 1, after the boron-doping on the front surface of the N-type crystalline silicon wafer, the obtained boron-doped surface includes not only the doped boron element but also the resulting boron silicon oxide. Meanwhile, the boron-doped surface is not treated in step 2, so the boron silicon oxide on the boron-doped surface will not be destroyed. Thus, referring to Fig. 3, when the phosphorus-doping process is performed on the polysilicon layer, only the side surfaces of the N-type crystalline silicon wafer will be affected and doped with some phosphorus element so as to form the corresponding phosphorus silicon oxide and phosphorus-silicon impurity layers, and the effect on the boron-doped surface by phosphorus will be blocked by the boron silicon oxide on the boron-doped surface; that is, the boron-doped surface will not be doped with phosphorus.

[0061] In addition, the phosphorus-doping method in step 4 may refer to the boron-doping method in step 1. The difference between the phosphorus-doping and boron-doping method is mainly that the doping source and conditions are different. When a phosphorus-doping process is performed, the doping source should be phosphorus source.

[0062] Step 5: The N-type crystalline silicon wafer is placed in a second solution for treatment in a floating mode while keeping the phosphorus-doped surface upward, and the second solution includes HF. o [0063] In the step 4, the polysilicon layer 7 is doped with phosphorus to form a N phosphorus-doped surface. In order to remove the phosphorous silicon oxide formed on S 25 — the side surfaces and the boron silicon oxide on the boron-doped surface of the N-type N crystalline silicon wafer, without damaging the boron-silicon doped layer of the z boron-doped surface, the phosphorus-doped N-type crystalline silicon wafer is placed to 13 be floating in HF in such a way that the phosphorus-doped surface of the N-type 5 crystalline silicon wafer does not contact the second solution. After the above treatment, O 30 the structure shown in FIG. 4 is obtained. In a feasible way, similar to the step 2, the second solution is placed in a holding tank in which a chain conveyer device is disposed, and the phosphorus-doped N-type crystalline silicon wafer is placed on the chain 13

PCT/CN2020/083205 ChinableIP Ref.: OP2020439FI conveyer device, wherein, the phosphorus-doped surface is kept facing upward and does not contact the second solution so that the second solution only contacts the front and side surfaces of the N-type crystalline silicon wafer.

[0064] The water film formed on the phosphorus-doped surface has a thickness of 0.1 mmto5mm, and the chain conveyer device has a conveying speed of 1.8 m/s to 4.2 m/s.

[0065] If the thickness of the water film formed on the phosphorus-doped surface is less than 0.1 mm, the splashed second solution will damage the water film that has a thickness less than 0.1 mm during the movement of the N-type crystalline silicon wafer driven by the chain conveyer device, and then the phosphorus-doped surface under the water film will be etched; if the thickness of the water film formed on the phosphorus-doped surface is greater than 5 mm, the weight of the water film is so large that the water film will fall off from the phosphorus-doped surface due to the inertia along with the rapid movement of the chain conveyer device, and the phosphorus-doped surface under the water film will be etched by the splashed second solution. If the thickness of the water film formed on the phosphorus-doped surface is between 0.1 mm and 5 mm, in the case that the conveying speed of the chain conveyer device is 1.8 ~ 4.2 m/s, the water film will not be damaged by the splashed second solution, and will not fall off automatically, thereby ensuring the guality and speed of the treatment in step 5 — described above.

[0066] On the one hand, the second solution is used to remove the phosphorous silicon oxide formed on the side surfaces of the N-type crystalline silicon wafer; on the other hand, the second solution can remove the boron silicon oxide on the boron-doped N surface, and make the boron-doped surface clean more cleanly. The volume concentration of HF in the second solution may be 3% to 7%.

N [0067] Step 6: The N-type crystalline silicon wafer that has been treated by the second x solution is placed in an alkaline solution for treatment.

13 [0068] After the treatment in the above steps, the N-type crystalline silicon wafer that 5 has been treated by the second solution is placed in an alkaline solution for treatment, in O 30 order to avoid that some phosphorous-silicon impurity layers remain on the side surfaces of the N-type crystalline silicon wafer. The alkaline solution may be reacted with silicon, but not with oxides. Therefore, only the silicon exposed on the side surfaces of the 14

PCT/CN2020/083205 ChinableIP Ref.: OP2020439FI N-type crystalline silicon wafer can react with the alkaline solution, and thus the phosphorous-silicon impurity layer on the side surfaces can be removed. As shown in Fig. 5, a certain thickness of the side surfaces of the N-type crystalline silicon wafer will be etched away by the alkaline solution, so that the boron-doped surface on the front side of the N-type crystalline silicon wafer is separated from the phosphorus-doped surface on the back side; that is, the boron-doped surface is completely isolated from the phosphorus-doped surface by the N-type crystalline silicon wafer interposed between the boron-doped surface and phosphorus-doped surface, so there will be no electric leakage.

[0069] Wherein, the alkaline solution may be NaOH, KOH, TMAH or NH40H, etc, which is not limited in this application. Preferably, the alkaline solution is a KOH solution with a volume concentration of 2% to 5%. The alkaline solution in step 6 is used to etch away a certain thickness of silicon so as to completely separate the boron-doped surface from the phosphorous-doped surface on the back side. Consequently, if the concentration of the alkaline solution is too low, the etching is too slow to achieve the desired effect; but if the concentration of the alkaline solution is too high, the etching will be too fast, resulting in over etching by the solution. When the alkaline solution is a KOH solution with a volume concentration of 2% to 5%, the etching effect can be achieved, and the etching rate can be controlled to avoid over etching.

[0070] Step 7: After the treatment by the alkaline solution, the phosphosilicate glass and borosilicate glass on the surfaces of the N-type crystalline silicon wafer are removed.

[0071] Further, the phosphosilicate glass on the phosphorus-doped surface and the N borosilicate glass on the boron-doped surface can be removed with HF. The —phosphosilicate glass and borosilicate glass may be the phosphorus silicon oxide and N boron silicate oxide, respectively. After removing the phosphosilicate glass and the - borosilicate glass, the boron-doped surface is a silicon surface that is only doped with E boron, and the phosphorus-doped surface is a silicon surface that is only doped with : phosphorus. O 30 [0072] Step 8. The surfaces of the N-type crystalline silicon wafer that have been treated in step / are oxidized.

[0073] Specifically, the N-type crystalline silicon wafer can be placed in a mixed 15

PCT/CN2020/083205 ChinableIP Ref.: OP2020439FI solution of HF and deionized water to remove the oxide layer on the surfaces; then the surfaces of the N-type crystalline silicon wafer can be oxidized. The oxidation process can be implemented with an ozone solution or a HNO3 solution.

[0074] Further after oxidation of the surface, an aluminum oxide layer is deposited on theboron-doped surface of the N-type crystalline silicon wafer.

[0075] Depositing an oxide layer on the boron-doped surface can improve the conversion efficiency of solar energy. For example, an aluminum oxide layer is deposited on the boron-doped surface, and the aluminum oxide layer may have a thickness of 6 nm.

[0076] Step 9. Afirst passivation anti-reflection layer 2 is deposited on the boron-doped surface of the N-type crystalline silicon wafer, and a second passivation anti-reflection layer 8 is deposited on the phosphorus-doped surface.

[0077] In the embodiments of the present application, the materials of the first passivation anti-reflection layer 2 and the second passivation anti-reflection layer 8 are not limited, and the first passivation anti-reflection layer 2 and the second passivation anti-reflection layer 8 can have the same or different materials and structures. The first passivation anti-reflection layer 2 and the second passivation anti-reflection layer 8 may each have a single-layer structure or a multi-layer composite structure. The materials of the first passivation anti-reflection layer 2 and the second passivation anti-reflection layer 8 may be any material that can be used for anti-reflection in the prior art, such as silicon nitride.

[0078] Step 10: A metallization process is performed to form a front metal electrode and o a back metal electrode.

O . [0079] In the embodiments of the present application, any method for manufacturing a = 25 metal electrode in the prior art may be used. For example, the first passivation - anti-reflection layer 2 is printed a silver paste, and dried at a temperature of 300 *C; and & the second passivation anti-reflection layer 8 is printed an aluminum paste and sintered, & wherein the maximum sintering temperature is up to 900 °C.

LO N [0080] It should be noted that both the front metal electrode and the back metal

N electrode use conductive metal materials, such as copper, silver, iron, etc., which are not limited in this application.

16

PCT/CN2020/083205 ChinableIP Ref.: OP2020439FI

[0081] In summary, the present application provides a method for manufacturing an N-type crystalline silicon cell. An N-type crystalline silicon wafer is firstly doped with boron on the front surface, and is placed to be floating in a first solution to remove the boron silicon oxide on the back and side surfaces of the N-type crystalline silicon wafer; and then the N-type crystalline silicon wafer is doped with phosphorus on the back surface, and is placed to be floating in a second solution to remove the phosphorous silicon oxide on the side surfaces of the N-type crystalline silicon wafer. Further, after the N-type crystalline silicon wafer that has been treated by the second solution is placed in an alkaline solution for treatment, it can be realized that the obtained boron-doped — surface is completely separated from the phosphorus-doped surface by the N-type crystalline silicon wafer interposed between the boron-doped surface and phosphorus-doped surface, so that no electric leakage occurs. Therefore, as shown in Fig. 6, electric leakage will not occur in the N-type crystalline silicon cell prepared by using the resultant N-type crystalline silicon wafer in which the boron-doped surface and the phosphorus-doped surface are completely isolated from each other. Example 1

[0082] Fig. 7 shows an N-type crystalline silicon cell produced according to the present example. The N-type crystalline silicon cell includes a front metal electrode 1, a SiNx layer 2, an AlOx layer 3, a boron-doped layer 4, an N-type crystalline silicon wafer 5, a SiO; layer 6, a polysilicon layer 7, a SiNx layer 8 and a back metal electrode 9, wherein, the SiNx layer 2, AlOx layer 3, boron-doped layer 4, N-type crystalline silicon wafer 5, SiO, layer 6, polysilicon layer 7 and SiNx layer 8 are stacked sequentially from top to bottom; the front metal electrode 1 passes through the SiNx layer 2 and the AlOx layer 3 S to form an ohmic contact with the boron-doped layer 4; and the back metal electrode 9 a 25 passes through the SiNx layer 8 to form an ohmic contact with the polysilicon layer 7. = [0083] Wherein, the SiNx layer 2 refers to silicon nitride layer, and the AlOx layer 3 2 refers to an aluminum oxide layer. o [0084] The N-type crystalline silicon cell shown in Fig. 7 is fabricated by the following 5 steps. A group of N-type crystalline silicon wafers (50 pieces) is provided and processed O 30 in the following way. (1) A texturing process is performed on the N-type crystalline silicon wafer, and a pyramidal texture surface is formed on a surface of the silicon wafer. The texturing 17

PCT/CN2020/083205 ChinableIP Ref.: OP2020439FI solution comprises KOH, a texturing additive and deionized water, wherein the volume concentration of KOH is 3%, and the texturing time is 800 seconds; (2) The N-type silicon wafer is subjected to single surface-doping by using a boron diffusion tube. The doping source is N, that carries BBrs. The flow rate of N, that carries BBrzs is 150 sccm, the flow rate of No that does not carry the source is 30 SLM, and the flow rate of oxygen is 600 sccm. The source supplying time is 25min, and the temperature is 900 °C; (3) A water film is formed on the boron-doped surface of the silicon wafer, and the silicon wafer is conveyed by a chain conveyer device so as to pass through a first solution in a floating mode while keeping the water film upward, wherein, the first solution comprises HF of 30L, HNO; of 230L, H>SO4 of 60L, and deionized water of 200L, the temperature of the solution is 16 °C, and the speed of the convey belt is 2 m/s; (4) A SiOx thin layer is grown by LPCVD method on the non-boron-doped surface of the N-type crystalline silicon wafer; IS —(5) Apolysilicon layer is deposited by LPCVD method on the non-boron-doped surface of the N-type crystalline silicon wafer; (6) The non-boron-doped surface of the N-type crystalline silicon wafer is subjected to phosphorus-doping by using a phosphorus diffusion tube. The doping source is N, that carries POCI3, wherein the flow rate of Na that carries POCI; is 100 sccm, the flow rate of nitrogen gas that does not carry the source is 5 SLM, and the flow rate of oxygen is 600 sccm, the source supplying time is 30min, and the temperature is 880 °C; (7) A water film is formed on the phosphorus-doped surface of the silicon wafer by using N A chain cleaning machine, and the silicon wafer passes through a mixed solution of HF . and deionized water in a floating mode, the concentration of HF is 5%, and the = 25 conveying speed is 1.8 m/s;

N z (8) The N-type crystalline silicon wafer is placed in a KOH alkaline solution, the volume so concentration of KOH is 3%, and the reaction time is 600 seconds;

O 5 (9) The N-type crystalline silicon wafer is placed in a HF solution, the volume O concentration of the HF solution is 5%, and the reaction time is 300 seconds; (10) The N-type crystalline silicon wafer is placed in a HNO3 solution, the volume concentration of the HNO3 solution is 67%, and the reaction time is 300 seconds; 18

PCT/CN2020/083205 ChinableIP Ref.: OP2020439FI (11) The N-type crystalline silicon wafer is placed in a HF solution, the volume concentration of the HF solution is 5%, and the reaction time is 300 seconds; (12) The N-type crystalline silicon wafer is placed in a HNO3 solution, the volume concentration of the HNO; solution is 67%, and the reaction time is 300 seconds; (13) An AlOx layer is deposited by atomic layer deposition (ALD) method on the boron-doped surface of the N-type crystalline silicon wafer, and the AlOx layer has a thickness of 6 nm; (14) A SiNx layer is deposited on the back and front of the N-type crystalline silicon wafer, respectively, and each of the SiNx layers has a thickness of 90 nm and a refractive index of 2.05; (15) A silver paste is printed on the phosphorus-doped surface of the N-type crystalline silicon wafer, and dried at a temperature of 300 °C; (16) An aluminum paste is printed on the boron-doped surface of the N-type crystalline silicon wafer and sintered, wherein the maximum sintering temperature is up to 900 °C. Example 2

[0085] The steps in Example 2 are substantially the same as Example 1. The difference with Example 1 is that the first solution in the step (3) of Example 2 comprises HF of 18L, HNO; of 121L, H2S04 of 60L, and deionized water of 140L, the temperature of the solution is 16 °C, and the speed of the convey belt is 2 m/s. Example 3

[0086] The steps in Example 3 are substantially the same as Example 1. The S difference with Example 1 is that the first solution in step (3) of Example 3 comprises HF

O N of 20L, HNO3 of 150L, HSOs of 66L, and deionized water of 150L, the temperature of

NN <Q the solution is 16 °C, and the speed of the convey belt is 2 m/s.

N z 25 Example4 0 [0087] The steps in Example 4 are substantially the same as Example 1. The 5 difference with Example 1 is that the first solution in step (3) of Example 4 comprises HF

O N of 40L, HNO3 of 200L, H,SO4 of 76L, and deionized water of 2861, the temperature of

N the solution is 16 *C, and the speed of the convey belt is 2 m/s. Example 5 19

PCT/CN2020/083205 ChinableIP Ref.: OP2020439FI

[0088] The steps in Example 5 are substantially the same as Example 1. The difference with Example 1 is that the first solution in step (3) of Example 4 comprises HF of 30L, HNO3 of 200L, and deionized water of 200L, the temperature of the solution is 16 °C, and the speed of the convey belt is 2 m/s. Example6

[0089] The steps in Example 6 are substantially the same as Example 1. The difference with Example 1 is that the first solution in step (3) of Example 6 comprises HF of 18L, HNO; of 120L, and deionized water of 130L, the temperature of the solution is 16 *C, and the speed of the convey belt is 2 m/s. Example7

[0090] The steps in Example 7 are substantially the same as Example 1. The difference with Example 1 is that the first solution in step (3) of Example 7 comprises HF of 40L, HNO3 of 200L, and deionized water of 260L, the temperature of the solution is 16 *C, and the speed of the convey belt is 2 m/s. IS Comparative Example 1

[0091] An N-type crystalline silicon cell is fabricated by the following steps, wherein a group of N-type crystalline silicon wafers (50 pieces) are provided and processed in the following way. (1) A texturing process is performed on the N-type crystalline silicon wafer, and a pyramidal texture surface is formed on a surface of the silicon wafer. The texturing solution comprises KOH, a texturing additive and deionized water, the volume concentration of KOH is 3%, and the texturing time is 800 seconds;

O

QA S (2) The N-type silicon wafer is subjected to single surface-doping by using a boron S diffusion tube. The doping source is N, that carries BBr;. The flow rate of N, that carries N 25 BBrsis 150 sccm, the flow rate of Na that does not carry the source is 30 SLM, and the E flow rate of oxygen is 600 sccm. The source supplying time is 25min, and the 10 temperature is 900 °C;

N S (3) A SiOx thin layer is grown by LPCVD method on the non-boron-doped surface of N-type crystalline silicon wafer; (4) Apolysilicon layer is deposited by LPCVD method on the non-boron-doped surface of N-type crystalline silicon wafer; 20

PCT/CN2020/083205 ChinableIP Ref.: OP2020439FI (5) The non-boron-doped surface of the N-type silicon wafer is subjected to phosphorus-doping by using a phosphorus diffusion tube. The doping source is N, that carries POCI3, wherein the flow rate of Na that carries POCI; is 100 sccm, the flow rate of nitrogen gas that does not carry the source is 5 SLM, and the flow rate of oxygen is 600 sccm, the source supplying time is 30min, and the temperature is 880 °C; (6) The N-type crystalline silicon wafer is placed in a HF solution, the volume concentration of the HF solution is 5%, and the reaction time is 300 seconds; (7) The N-type crystalline silicon wafer is placed in a HNO3 solution, the volume concentration of the HNO3 solution is 67%, and the reaction time is 300 seconds; (8) The N-type crystalline silicon wafer is placed in a HF solution, the volume concentration of the HF solution is 5%, and the reaction time is 300 seconds; (9) The N-type crystalline silicon wafer is placed in a HNO3 solution, the volume concentration of the HNO3 solution is 67%, and the reaction time is 300 seconds; (10) An AlOx layer is deposited by atomic layer deposition (ALD) method on the IS boron-doped surface of the N-type crystalline silicon wafer, and the AlOx layer has a thickness of 6 nm; (11) A SiNx layer is deposited on the back and front of the N-type crystalline silicon wafer, respectively, and each of the SiNx layers has a thickness of 90 nm and a refractive index of 2.05; (12) A silver paste is printed on the phosphorus-doped surface of the N-type crystalline silicon wafer, and dried at a temperature of 300 °C; > (13) A silver-aluminum paste is printed on the boron-doped surface of the N-type S crystalline silicon wafer and sintered, wherein the maximum sintering temperature is up 5 to 900 °C.

N N 25 [0092] After the preparation of the cells is completed, five cells are randomly selected

I = from the cells obtained in Example 1 and Comparative Example 1, respectively. The two & groups of cells are tested the electric leakage by using a cell IV tester. The data obtained S from the electric leakage tests are shown in Tables 1 and 2, respectively. Furthermore, two cells are randomly selected from the cells obtained in Examples 2 to 7, respectively, and each group of cells is tested the electric leakage by using a cell IV tester. The data obtained from the electric leakage tests are shown in Table 3, respectively. 21

PCT/CN2020/083205 ChinableIP Ref.: OP2020439FI Table 1 Data of the electric leakage test for the cells in Example 1 Cell No. Electric leakage for 12V reverse voltage

0.05A

0.03A

0.05A

0.06A

0.09A Table 2 Data of the electric leakage test for the cells in Comparative Example 1 Cell No. electric leakage for 12V reverse voltage 6 | A | Table 3 Data of the electric leakage test for the cells in Examples 2 to 7 Example Cell No. electric leakage for 12V reverse voltage Example 2 0.03A

0.04 A Example 3 6 | 0.03 A

0.05 A Example 4 0.06 A

0.07 A Example 5 0.10 A

0.11 A Example 6 0.12 A

0.13A S Example 7 0.12 N 0.11 A S [0093] As can be seen from Tables 1, 2 and 3, the cells fabricated by the preparation N 5 methods of Examples 1 to 7 have a lesser electric leakage for 12V reverse voltage. E Therefore, the electric leakage problem is solved, and the electric leakage for a reverse 2 voltage in the N-type crystalline silicon cell is significantly reduced. It can also be seen 2 from Table 2 that the cell, which is fabricated with the N-type crystalline silicon wafer that

QA S has been treated by the first solution containing H>SO4, can have an electric leakage of

0.03Ato 0.09A for 12V reverse voltage.

[0094] The embodiments described above are only preferred embodiments that are 22

PCT/CN2020/083205 ChinableIP Ref.: OP2020439FI used to explain the technical concept and features of the present invention. The embodiments are provided to enable those skilled in the art to understand the content of the present invention and implement it accordingly, and not to limit the scope of the present invention. Any eguivalent changes or modifications based on the principles of the present invention should be included in the protection scope of the present invention.

O QA O N

K <Q

N N

I Ao a

LO O N LO O QA O

N 23

Claims

PCT/CN2020/083205 ChinableIP Ref.: OP2020439FI WHAT IS CLAIMED IS:

1. Amethod for manufacturing an N-type crystalline silicon cell, comprising the following steps in seguence: A. performing boron doping on one surface of a textured N-type crystalline silicon wafer; B. placing the boron-doped N-type crystalline silicon wafer in a first solution for treatment in a floating mode while keeping the boron-doped surface upward, wherein the first solution includes a mixed solution comprising HF and HNO3, or a mixed solution comprising HF, HNO3 and H>SO;; C. growing an oxide thin layer on the other surface of the N-type crystalline silicon wafer; D. depositing a polysilicon layer on the oxide thin layer and doping phosphorus element; E. placing the N-type crystalline silicon wafer in a second solution for treatment in a floating mode while keeping the phosphorus-doped surface upward, wherein the second solution includes HF; F. placing the N-type crystalline silicon wafer treated by the second solution in an alkaline solution for treatment; G. removing a phosphosilicate glass and borosilicate glass on the surfaces of the N-type crystalline silicon wafer treated by the alkaline solution; H. oxidizing the surfaces of the N-type crystalline silicon wafer treated in the above step G; I. depositing a first passivation anti-reflection layer on the boron-doped surface of the N-type crystalline silicon wafer, and depositing a second passivation anti-reflection layer N on the phosphorus-doped surface;

N K J. performing a metallization process to form a front metal electrode and a back metal

O N electrode.

N E

2. The method for manufacturing an N-type crystalline silicon cell according to claim 1, O wherein, in the step B, a water film is firstly formed on the boron-doped surface of the N-type crystalline silicon wafer, and then the N-type crystalline silicon wafer is placed in O the first solution for treatment in a floating mode; In the step E, a water film is firstly formed on the phosphorus-doped surface of the N-type crystalline silicon wafer, and then the N-type crystalline silicon wafer is placed in the second solution for treatment in a 1/5

PCT/CN2020/083205 ChinableIP Ref.: OP2020439FI floating mode.

3. The method for manufacturing an N-type crystalline silicon cell according to claim 1 or 2, wherein, the step B is specifically implemented as follows: a water film is formed on the boron-doped surface of the N-type crystalline silicon wafer, and then the N-type crystalline silicon wafer is conveyed via a chain conveyer device so as to pass through the first solution in a floating mode while keeping the boron-doped surface upward.

4. The method for manufacturing an N-type crystalline silicon cell according to claim 3, wherein, the first solution is a mixed solution comprising HF, HNO3 and deionized water, or a mixed solution comprising HF, HNO3, H2S04 and deionized water; and the chain conveyer device has a conveying speed of 1.8 m/s to 2.2 m/s..

5. The method for manufacturing an N-type crystalline silicon cell method according to claim 1 or 2, wherein, the step E is specifically implemented as follows: a water film is formed on the phosphorus-doped surface of the N-type crystalline silicon wafer, and then the N-type crystalline silicon wafer is conveyed via a chain conveyer device so as to pass through the second solution in a floating mode while keeping the phosphorus-doped surface of the N-type crystalline silicon wafer upward.

6. The method for manufacturing an N-type crystalline silicon cell according to claim 1, wherein, the second solution may be a solution comprising HF and deionized water, the volume concentration of HF in the second solution is in a range from 3% to /%, and the chain conveyer device has a conveying speed of 1.6 m/s to 2.0 m/s.

7. The method for manufacturing an N-type crystalline silicon cell according to claim 1, wherein, the alkaline solution in the step F is a KOH solution with a volume concentration S of 2% to 5%. .

8. The method for manufacturing an N-type crystalline silicon cell according to claim 1, = wherein, the oxide thin layer in the step C is a silicon oxide thin layer; and in the step D, - phosphorus element is doped during the deposition of the polysilicon layer or after the & deposition of the polysilicon layer.

9. The method for manufacturing an N-type crystalline silicon cell according to claim 1, N wherein, the step H is specifically implemented as follows: first, the N-type crystalline N silicon wafer is oxidized, next the oxide on the surfaces is removed, and then the surfaces of the N-type crystalline silicon wafer are oxidized. 2/5

PCT/CN2020/083205 ChinableIP Ref.: OP2020439FI

10. The method for manufacturing an N-type crystalline silicon cell according to claim 1, wherein, in the step I, an aluminum oxide layer and a silicon nitride layer are sequentially deposited on the boron-doped surface of the N-type crystalline silicon wafer, and a silicon nitride layer is deposited on the phosphorus-doped surface of the N-type crystalline silicon wafer.

11. The method for manufacturing an N-type crystalline silicon cell according to claim 3, wherein, the water film formed on the boron-doped surface has a thickness ranging from

0.1 mm to 5 mm, and the chain conveyer device has a conveying speed ranging from 1.8 m/s to 4.2 m/s.

12. The method for manufacturing an N-type crystalline silicon cell according to claim 5, wherein, the water film formed on the phosphorus-doped surface has a thickness ranging from 0.1 mm to 5 mm, and the chain conveyer device has a conveying speed ranging from 1.8 m/s to 4.2 m/s.

13. The method for manufacturing an N-type crystalline silicon cell according to claim 1, wherein, if the first solution is a mixed solution comprising HF and HNO3, the volume ratio of HF and HNO9s is 1 : (5-8), wherein the volume concentration of HF is 49%, and the volume concentration of HNO3 is 68%.

14. The method for manufacturing an N-type crystalline silicon cell according to claim 1, wherein, if the first solution is a mixed solution comprising HF, HNO3 and H2SO,, the volume ratio of HF, HNO3 and H,SO4 is (10-20) : (80-130) : (40-60) wherein the volume concentration of HF is 49%, the volume concentration of HNO3 is 68%, and the volume concentration of H>SO4 is 96%.

O

QA

O

N

K <Q

N

I &

LO

O

N

LO

O

QA

O

N 3/5