FI20095557A0 - Valmistusmenetelmä ja elektroniikkamoduuli, joka tarjoaa uusia mahdollisuuksia johdevedoille - Google Patents

Valmistusmenetelmä ja elektroniikkamoduuli, joka tarjoaa uusia mahdollisuuksia johdevedoille

Info

Publication number
FI20095557A0
FI20095557A0 FI20095557A FI20095557A FI20095557A0 FI 20095557 A0 FI20095557 A0 FI 20095557A0 FI 20095557 A FI20095557 A FI 20095557A FI 20095557 A FI20095557 A FI 20095557A FI 20095557 A0 FI20095557 A0 FI 20095557A0
Authority
FI
Finland
Prior art keywords
conductors
manufacturing
electronics module
new opportunities
offers new
Prior art date
Application number
FI20095557A
Other languages
English (en)
Swedish (sv)
Inventor
Antti Kivikero
Pekka Kostensalo
Original Assignee
Imbera Electronics Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Imbera Electronics Oy filed Critical Imbera Electronics Oy
Priority to FI20095557A priority Critical patent/FI20095557A0/fi
Publication of FI20095557A0 publication Critical patent/FI20095557A0/fi
Priority to US15/938,967 priority patent/USRE48539E1/en
Priority to US17/213,981 priority patent/USRE49970E1/en
Priority to PCT/FI2010/050403 priority patent/WO2010133767A1/en
Priority to US13/698,670 priority patent/US9301394B2/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
FI20095557A 2009-05-19 2009-05-19 Valmistusmenetelmä ja elektroniikkamoduuli, joka tarjoaa uusia mahdollisuuksia johdevedoille FI20095557A0 (fi)

Priority Applications (5)

Application Number Priority Date Filing Date Title
FI20095557A FI20095557A0 (fi) 2009-05-19 2009-05-19 Valmistusmenetelmä ja elektroniikkamoduuli, joka tarjoaa uusia mahdollisuuksia johdevedoille
US15/938,967 USRE48539E1 (en) 2009-05-19 2010-05-19 Manufacturing method and electronic module with new routing possibilities
US17/213,981 USRE49970E1 (en) 2009-05-19 2010-05-19 Manufacturing method and electronic module with new routing possibilities
PCT/FI2010/050403 WO2010133767A1 (en) 2009-05-19 2010-05-19 Manufacturing method and electronic module with new routing possibilites
US13/698,670 US9301394B2 (en) 2009-05-19 2010-05-19 Manufacturing method and electronic module with new routing possibilities

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FI20095557A FI20095557A0 (fi) 2009-05-19 2009-05-19 Valmistusmenetelmä ja elektroniikkamoduuli, joka tarjoaa uusia mahdollisuuksia johdevedoille

Publications (1)

Publication Number Publication Date
FI20095557A0 true FI20095557A0 (fi) 2009-05-19

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FI20095557A FI20095557A0 (fi) 2009-05-19 2009-05-19 Valmistusmenetelmä ja elektroniikkamoduuli, joka tarjoaa uusia mahdollisuuksia johdevedoille

Country Status (3)

Country Link
US (3) USRE48539E1 (fi)
FI (1) FI20095557A0 (fi)
WO (1) WO2010133767A1 (fi)

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US8923008B2 (en) * 2011-03-08 2014-12-30 Ibiden Co., Ltd. Circuit board and method for manufacturing circuit board
DE102012102847A1 (de) * 2012-04-02 2013-10-02 Osram Opto Semiconductors Gmbh Licht emittierendes Halbleiterbauelement und Verfahren zur Herstellung eines Licht emittierenden Halbleiterbauelements
KR20170045553A (ko) * 2015-10-19 2017-04-27 에스케이하이닉스 주식회사 재배선 라인을 구비하는 반도체 장치
JP2017224788A (ja) * 2016-06-17 2017-12-21 ミヨシ電子株式会社 電子回路装置
KR102639101B1 (ko) * 2017-02-24 2024-02-22 에스케이하이닉스 주식회사 전자기간섭 차폐 구조를 갖는 반도체 패키지
US10658281B2 (en) * 2017-09-29 2020-05-19 Intel Corporation Integrated circuit substrate and method of making
US10438895B1 (en) * 2018-06-08 2019-10-08 American Semiconductor, Inc. Flexible micro-module
CN113163572A (zh) * 2020-01-22 2021-07-23 奥特斯(中国)有限公司 具有覆盖有超薄过渡层的部件的部件承载件
TWI780500B (zh) * 2020-10-12 2022-10-11 龍華科技大學 感應加熱應用於重佈線路的方法

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US20130175075A1 (en) 2013-07-11
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USRE49970E1 (en) 2024-05-14

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