ES8206939A1 - Perfeccionamientos en un circuito sincronizador de senales - Google Patents

Perfeccionamientos en un circuito sincronizador de senales

Info

Publication number
ES8206939A1
ES8206939A1 ES505737A ES505737A ES8206939A1 ES 8206939 A1 ES8206939 A1 ES 8206939A1 ES 505737 A ES505737 A ES 505737A ES 505737 A ES505737 A ES 505737A ES 8206939 A1 ES8206939 A1 ES 8206939A1
Authority
ES
Spain
Prior art keywords
circuit
pilot signal
delay time
latch circuits
sending
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES505737A
Other languages
English (en)
Other versions
ES505737A0 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of ES505737A0 publication Critical patent/ES505737A0/es
Publication of ES8206939A1 publication Critical patent/ES8206939A1/es
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/06—Speed or phase control by synchronisation signals the synchronisation signals differing from the information signals in amplitude, polarity or frequency or length
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0037—Delay of clock signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0041—Delay of data signal

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

CIRCUITO SINCRONIZADOR DE SEÑALES. COMPRENDE DIVERSAS VIA DE TRANSMISION DE SEÑAL CON TIEMPOS DE RETARDO DIFERENTES, CIRCUITO GENERADOR DE SEÑAL PILOTO QUE OPERA SOBRE LOS IMPULSOS DE SINCRONISMO DEL LADO TRANSMISOR, CIRCUITO ACTIVADOR DE CIRCUITOS DE RETENCION MEDIANTE APLICACION A ELLOS DE DICHAS SEÑALES PILOTO; ESTOS CIRCUITOS DE RENTENCION QUE OPERAN SOBRE LOS IMPULSOS DE SINCRONIZACION DEL LADO RECEPTOR, CIRCUITO DE PREDICCION DE DIFERENCIA DE FASE ENTRE LAS SEÑALES DEL SISTEMA DE IMPULSOS DE SINCRONISMO DE LOS LADOS TRANSMISOR Y RECEPTOR.
ES505737A 1980-09-27 1981-09-24 Perfeccionamientos en un circuito sincronizador de senales Expired ES8206939A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55133681A JPS5760754A (en) 1980-09-27 1980-09-27 Synchronizing circuit

Publications (2)

Publication Number Publication Date
ES505737A0 ES505737A0 (es) 1982-08-16
ES8206939A1 true ES8206939A1 (es) 1982-08-16

Family

ID=15110385

Family Applications (1)

Application Number Title Priority Date Filing Date
ES505737A Expired ES8206939A1 (es) 1980-09-27 1981-09-24 Perfeccionamientos en un circuito sincronizador de senales

Country Status (9)

Country Link
US (1) US4426713A (es)
EP (1) EP0049952B1 (es)
JP (1) JPS5760754A (es)
KR (1) KR850000952B1 (es)
AU (1) AU524158B2 (es)
BR (1) BR8106172A (es)
CA (1) CA1185342A (es)
DE (1) DE3171400D1 (es)
ES (1) ES8206939A1 (es)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4570162A (en) * 1982-09-13 1986-02-11 The University Of Toronto Innovations Foundation Local area networks
US4558422A (en) * 1983-03-23 1985-12-10 Tektronix, Inc. Digital signal sampling system with two unrelated sampling timebases
US4583013A (en) * 1984-02-13 1986-04-15 Rockwell International Corporation Oscillator signal detect circuit
US4700347A (en) * 1985-02-13 1987-10-13 Bolt Beranek And Newman Inc. Digital phase adjustment
US4691121A (en) * 1985-11-29 1987-09-01 Tektronix, Inc. Digital free-running clock synchronizer
US4771422A (en) * 1986-12-04 1988-09-13 Itt Corporation, Defense Communications Division Priority user protection in multiple priority switching systems
JPH0683172B2 (ja) * 1988-09-27 1994-10-19 日本電気株式会社 フレームアライメント方式
JPH02192337A (ja) * 1989-01-20 1990-07-30 Fujitsu Ltd 位相調整回路
US4949360A (en) * 1989-08-08 1990-08-14 International Business Machines Corporation Synchronizing circuit
US5001731A (en) * 1989-10-02 1991-03-19 Motorola, Inc. Method and apparatus for eliminating clockskew race condition errors
US5259006A (en) * 1990-04-18 1993-11-02 Quickturn Systems, Incorporated Method for substantially eliminating hold time violations in implementing high speed logic circuits or the like
US5729550A (en) * 1995-03-24 1998-03-17 Hitachi, Ltd. Data transmitter-receiver
US6370200B1 (en) * 1997-08-04 2002-04-09 Matsushita Electric Industrial Co., Ltd. Delay adjusting device and method for plural transmission lines
US6208907B1 (en) * 1998-01-30 2001-03-27 International Business Machines Corporation Domino to static circuit technique
DE102004010562B4 (de) * 2004-03-01 2008-04-24 Infineon Technologies Ag Schnittstellenvorrichtung und Verfahren zur Synchronisation von Daten
WO2020026363A1 (ja) 2018-07-31 2020-02-06 株式会社島津製作所 材料試験機

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3072804A (en) * 1959-12-14 1963-01-08 Bell Telephone Labor Inc Pulse position detector utilizing the storage effect of pnpn diodes
GB968730A (es) * 1962-02-09
US4119796A (en) * 1976-11-01 1978-10-10 Versitron, Inc. Automatic data synchronizer

Also Published As

Publication number Publication date
AU524158B2 (en) 1982-09-02
US4426713A (en) 1984-01-17
JPS5760754A (en) 1982-04-12
BR8106172A (pt) 1982-06-15
ES505737A0 (es) 1982-08-16
AU7559981A (en) 1982-05-06
CA1185342A (en) 1985-04-09
DE3171400D1 (en) 1985-08-22
EP0049952A1 (en) 1982-04-21
EP0049952B1 (en) 1985-07-17
KR830008574A (ko) 1983-12-10
JPS6114701B2 (es) 1986-04-19
KR850000952B1 (ko) 1985-06-29

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 20020506