ES457764A1 - Perfeccionamientos en disposiciones de control de acceso de memoria en dispositivos multi-procesadores de datos. - Google Patents
Perfeccionamientos en disposiciones de control de acceso de memoria en dispositivos multi-procesadores de datos.Info
- Publication number
- ES457764A1 ES457764A1 ES457764A ES457764A ES457764A1 ES 457764 A1 ES457764 A1 ES 457764A1 ES 457764 A ES457764 A ES 457764A ES 457764 A ES457764 A ES 457764A ES 457764 A1 ES457764 A1 ES 457764A1
- Authority
- ES
- Spain
- Prior art keywords
- main memory
- logical
- accessing
- control system
- shift register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
- G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
- G06F13/1631—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests through address comparison
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
- Memory System (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
Perfeccionamientos en disposiciones de control de acceso de memoria, en dispositivos multi-procesadores de datos, estando previstos entre por lo menos un dispositivo de acceso y una memoria principal compuesta de una pluralidad de almacenajes lógicos, accesibles independientemente y recibe por lo menos una petición desde el dispositivo de acceso, basado en el estado de la memoria principal, para permitir acceso a uno de los almacenajes lógicos, caracterizados porque está dispuesto un registro de traslado, compuesto de etapas de registro correspondiendo al tiempo de ciclo de la memoria principal y un circuito comparador, almacenándose en el registro de traslado, información de dirección de uno o varios de los almacenajes ocupados, y transladándose secuencialmente en sincronismo con una señal de registro de tiempo; *** Ver imagen 01
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4703976A JPS52130246A (en) | 1976-04-24 | 1976-04-24 | Memory access control system |
Publications (1)
Publication Number | Publication Date |
---|---|
ES457764A1 true ES457764A1 (es) | 1978-03-01 |
Family
ID=12764010
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES457764A Expired ES457764A1 (es) | 1976-04-24 | 1977-04-13 | Perfeccionamientos en disposiciones de control de acceso de memoria en dispositivos multi-procesadores de datos. |
Country Status (9)
Country | Link |
---|---|
US (1) | US4115851A (es) |
JP (1) | JPS52130246A (es) |
AU (1) | AU501316B2 (es) |
BR (1) | BR7702569A (es) |
CA (1) | CA1072216A (es) |
DE (1) | DE2717702C2 (es) |
ES (1) | ES457764A1 (es) |
FR (1) | FR2349192A1 (es) |
GB (1) | GB1568312A (es) |
Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4228500A (en) * | 1978-03-27 | 1980-10-14 | Honeywell Information Systems Inc. | Command stacking apparatus for use in a memory controller |
US4253144A (en) * | 1978-12-21 | 1981-02-24 | Burroughs Corporation | Multi-processor communication network |
US4307446A (en) * | 1979-05-02 | 1981-12-22 | Burroughs Corporation | Digital communication networks employing speed independent switches |
NL7907179A (nl) * | 1979-09-27 | 1981-03-31 | Philips Nv | Signaalprocessorinrichting met voorwaardelijke- -interrupteenheid en multiprocessorsysteem met deze signaalprocessorinrichtingen. |
US4384323A (en) * | 1980-02-25 | 1983-05-17 | Bell Telephone Laboratories, Incorporated | Store group bus allocation system |
US4393459A (en) * | 1980-07-17 | 1983-07-12 | International Business Machines Corp. | Status reporting with ancillary data |
US4380798A (en) * | 1980-09-15 | 1983-04-19 | Motorola, Inc. | Semaphore register including ownership bits |
JPS5786180A (en) * | 1980-11-17 | 1982-05-29 | Hitachi Ltd | Memory device having address converting mechanism |
US4410943A (en) * | 1981-03-23 | 1983-10-18 | Honeywell Information Systems Inc. | Memory delay start apparatus for a queued memory controller |
US4495567A (en) * | 1981-10-15 | 1985-01-22 | Codex Corporation | Multiprocessor/multimemory control system |
JPS5995151U (ja) * | 1982-12-20 | 1984-06-28 | 三菱重工業株式会社 | 粉体供給装置 |
US4594657A (en) * | 1983-04-22 | 1986-06-10 | Motorola, Inc. | Semaphore for memory shared by two asynchronous microcomputers |
US4654787A (en) * | 1983-07-29 | 1987-03-31 | Hewlett-Packard Company | Apparatus for locating memory modules having different sizes within a memory space |
US4722052A (en) * | 1984-04-02 | 1988-01-26 | Sperry Corporation | Multiple unit adapter |
US4630197A (en) * | 1984-04-06 | 1986-12-16 | Gte Communication Systems Corporation | Anti-mutilation circuit for protecting dynamic memory |
US4710868A (en) * | 1984-06-29 | 1987-12-01 | International Business Machines Corporation | Interconnect scheme for shared memory local networks |
US4745545A (en) * | 1985-06-28 | 1988-05-17 | Cray Research, Inc. | Memory reference control in a multiprocessor |
US4821185A (en) * | 1986-05-19 | 1989-04-11 | American Telephone And Telegraph Company | I/O interface system using plural buffers sized smaller than non-overlapping contiguous computer memory portions dedicated to each buffer |
US4807184A (en) * | 1986-08-11 | 1989-02-21 | Ltv Aerospace | Modular multiple processor architecture using distributed cross-point switch |
US4780822A (en) * | 1986-09-17 | 1988-10-25 | Integrated Device Technology, Inc. | Semaphore circuit for shared memory cells |
US5301278A (en) * | 1988-04-29 | 1994-04-05 | International Business Machines Corporation | Flexible dynamic memory controller |
US5142638A (en) * | 1989-02-07 | 1992-08-25 | Cray Research, Inc. | Apparatus for sharing memory in a multiprocessor system |
JP2626154B2 (ja) * | 1990-04-18 | 1997-07-02 | 日本電気株式会社 | メモリアクセス制御装置 |
JP2511588B2 (ja) * | 1990-09-03 | 1996-06-26 | インターナショナル・ビジネス・マシーンズ・コーポレイション | デ―タ処理ネットワ―ク、ロックを獲得させる方法及び直列化装置 |
US5206952A (en) * | 1990-09-12 | 1993-04-27 | Cray Research, Inc. | Fault tolerant networking architecture |
DE69230462T2 (de) * | 1991-11-19 | 2000-08-03 | Sun Microsystems, Inc. | Arbitrierung des Multiprozessorzugriffs zu gemeinsamen Mitteln |
JPH086889A (ja) * | 1994-06-20 | 1996-01-12 | Fujitsu Ltd | 入出力制御装置 |
US6022094A (en) * | 1995-09-27 | 2000-02-08 | Lexmark International, Inc. | Memory expansion circuit for ink jet print head identification circuit |
US7231499B2 (en) * | 2003-12-17 | 2007-06-12 | Broadcom Corporation | Prioritization of real time / non-real time memory requests from bus compliant devices |
JP4494899B2 (ja) * | 2004-07-29 | 2010-06-30 | 富士通株式会社 | プロセッサデバッグ装置およびプロセッサデバッグ方法 |
JP4650552B2 (ja) * | 2008-10-14 | 2011-03-16 | ソニー株式会社 | 電子機器、コンテンツ推薦方法及びプログラム |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3997875A (en) * | 1973-01-08 | 1976-12-14 | U.S. Philips Corporation | Computer configuration with claim cycles |
JPS5434500B2 (es) * | 1973-12-30 | 1979-10-27 | ||
US3967246A (en) * | 1974-06-05 | 1976-06-29 | Bell Telephone Laboratories, Incorporated | Digital computer arrangement for communicating data via data buses |
-
1976
- 1976-04-24 JP JP4703976A patent/JPS52130246A/ja active Granted
-
1977
- 1977-04-06 US US05/785,104 patent/US4115851A/en not_active Expired - Lifetime
- 1977-04-13 ES ES457764A patent/ES457764A1/es not_active Expired
- 1977-04-19 AU AU24419/77A patent/AU501316B2/en not_active Expired
- 1977-04-21 DE DE2717702A patent/DE2717702C2/de not_active Expired
- 1977-04-22 BR BR7702569A patent/BR7702569A/pt unknown
- 1977-04-22 GB GB16924/77A patent/GB1568312A/en not_active Expired
- 1977-04-22 FR FR7712198A patent/FR2349192A1/fr active Granted
- 1977-04-22 CA CA276,836A patent/CA1072216A/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS52130246A (en) | 1977-11-01 |
AU501316B2 (en) | 1979-06-14 |
AU2441977A (en) | 1978-10-26 |
CA1072216A (en) | 1980-02-19 |
US4115851A (en) | 1978-09-19 |
DE2717702C2 (de) | 1981-12-24 |
FR2349192B1 (es) | 1980-04-25 |
BR7702569A (pt) | 1978-02-21 |
JPS5756751B2 (es) | 1982-12-01 |
FR2349192A1 (fr) | 1977-11-18 |
GB1568312A (en) | 1980-05-29 |
DE2717702A1 (de) | 1977-11-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
ES457764A1 (es) | Perfeccionamientos en disposiciones de control de acceso de memoria en dispositivos multi-procesadores de datos. | |
US4031515A (en) | Apparatus for transmitting changeable length records having variable length words with interspersed record and word positioning codes | |
KR930004426B1 (ko) | 듀얼 포트 판독/기입 레지스터 파일 메모리 및 그 구성방법 | |
US4147083A (en) | Programmable voice characteristic memory system | |
GB886889A (en) | Improvements in memory systems for data processing devices | |
US5765203A (en) | Storage and addressing method for a buffer memory control system for accessing user and error imformation | |
ES8503868A1 (es) | Una instalacion de control de almacenamiento intermedio en un procesador de datos | |
GB1534189A (en) | Data processing apparatus | |
ES440887A1 (es) | Unidad de control de acceso para controlar un dispositivo dememoria. | |
US3478325A (en) | Delay line data transfer apparatus | |
US5179686A (en) | Method for automatically detecting the size of a memory by performing a memory warp operation | |
US3662348A (en) | Message assembly and response system | |
KR960005605A (ko) | 반도체 기억장치 | |
US4388701A (en) | Recirculating loop memory array having a shift register buffer for parallel fetching and storing | |
GB1119626A (en) | Computer memory testing system | |
GB1526828A (en) | Information processing system | |
US3701984A (en) | Memory subsystem array | |
US3771140A (en) | Storage configuration comprising shift registers | |
US4388687A (en) | Memory unit | |
KR900002189A (ko) | 컴퓨터 시스템에 있어서 데이타 신뢰성의 개선방법 및 장치 | |
AU643532B2 (en) | Data transfer interface module | |
US4198699A (en) | Mass memory access method and apparatus | |
US3441908A (en) | Data storage system | |
KR880004490A (ko) | 반도체 기억장치 | |
US4125879A (en) | Double ended stack computer store |