ES2161175B1 - J-K MASTER-SLAVE BIESTABLE WITH DATA LOCK. - Google Patents
J-K MASTER-SLAVE BIESTABLE WITH DATA LOCK.Info
- Publication number
- ES2161175B1 ES2161175B1 ES9902445A ES9902445A ES2161175B1 ES 2161175 B1 ES2161175 B1 ES 2161175B1 ES 9902445 A ES9902445 A ES 9902445A ES 9902445 A ES9902445 A ES 9902445A ES 2161175 B1 ES2161175 B1 ES 2161175B1
- Authority
- ES
- Spain
- Prior art keywords
- slave
- master
- data lock
- flip
- biestable
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Logic Circuits (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Biestable J-K Maestro-Esclavo con bloqueo de datos. El presente proyecto ofrece una nueva versión de biestable tipo J-K Maestro- Esclavo con bloqueo de datos. La captura de la información presente en la entrada y su cierre automático se realiza aquí por un F/F Maestro (1) constituído como biestable tipo D activado por el flanco creciente de la señal de reloj. La parte del F/F Esclavo se basa en el clásico latch tipo S-R (2) gobernado por el nivel C de reloj. La función lógica J-K propia de los dispositivos de esta índole es implementada mediante realimentación cruzada desde las salidas Q y Q del Esclavo hacia la red combinacional AND-OR (3) de la entrada. El circuito diseñado permite realizar una serie de configuraciones esquemáticas de frecuente uso sin necesidad de elementos inversores adicionales.Bistable J-K Master-Slave with data lock. This project offers a new version of flip-flop type J-K Master-Slave with data lock. The capture of the information present at the entrance and its automatic closing is done here by a Master F / F (1) constituted as flip-flop type D activated by the rising edge of the clock signal. The F / F Slave part is based on the classic latch type S-R (2) governed by the C level clock. The logical function J-K of the devices of this nature is implemented by means of cross feedback from the outputs Q and Q of the Slave to the combinatorial network AND-OR (3) of the input. The designed circuit allows a series of schematic configurations to be used frequently without the need for additional inverting elements.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
ES9902445A ES2161175B1 (en) | 1999-11-08 | 1999-11-08 | J-K MASTER-SLAVE BIESTABLE WITH DATA LOCK. |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
ES9902445A ES2161175B1 (en) | 1999-11-08 | 1999-11-08 | J-K MASTER-SLAVE BIESTABLE WITH DATA LOCK. |
Publications (2)
Publication Number | Publication Date |
---|---|
ES2161175A1 ES2161175A1 (en) | 2001-11-16 |
ES2161175B1 true ES2161175B1 (en) | 2002-08-01 |
Family
ID=8310510
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES9902445A Expired - Lifetime ES2161175B1 (en) | 1999-11-08 | 1999-11-08 | J-K MASTER-SLAVE BIESTABLE WITH DATA LOCK. |
Country Status (1)
Country | Link |
---|---|
ES (1) | ES2161175B1 (en) |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3591856A (en) * | 1967-11-07 | 1971-07-06 | Texas Instruments Inc | J-k master-slave flip-flop |
US4145623A (en) * | 1977-10-04 | 1979-03-20 | Burroughs Corporation | Current mode logic compatible emitter function type logic family |
US4300060A (en) * | 1979-12-10 | 1981-11-10 | General Motors Corporation | Signal programmable multiple function flip-flop |
US4349753A (en) * | 1980-09-29 | 1982-09-14 | Bell Telephone Laboratories, Incorporated | Emitter function logic flip-flop circuit |
-
1999
- 1999-11-08 ES ES9902445A patent/ES2161175B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
ES2161175A1 (en) | 2001-11-16 |
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Legal Events
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EC2A | Search report published |
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