ES2068268T3 - Dispositivo de tratamiento de mensajes de señalizacion en una red de telecomunicacion en tecnica temporal asincrona. - Google Patents

Dispositivo de tratamiento de mensajes de señalizacion en una red de telecomunicacion en tecnica temporal asincrona.

Info

Publication number
ES2068268T3
ES2068268T3 ES90105680T ES90105680T ES2068268T3 ES 2068268 T3 ES2068268 T3 ES 2068268T3 ES 90105680 T ES90105680 T ES 90105680T ES 90105680 T ES90105680 T ES 90105680T ES 2068268 T3 ES2068268 T3 ES 2068268T3
Authority
ES
Spain
Prior art keywords
processing circuit
memory
processor
reception
cells
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES90105680T
Other languages
English (en)
Inventor
Jean-Michel Balzano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel CIT SA
Original Assignee
Alcatel CIT SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel CIT SA filed Critical Alcatel CIT SA
Application granted granted Critical
Publication of ES2068268T3 publication Critical patent/ES2068268T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/20—Repeater circuits; Relay circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3036—Shared queuing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/55—Prevention, detection or correction of errors
    • H04L49/555—Error detection
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/40—Network security protocols

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Security & Cryptography (AREA)
  • Power Engineering (AREA)
  • Communication Control (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Radio Relay Systems (AREA)
  • Arrangements For Transmission Of Measured Signals (AREA)

Abstract

EL DISPOSITIVO CONSTA DE UN CIRCUITO DE TRATAMIENTO DEL PROTOCOLO (CTP) ENLAZADO A UNA RED (TTA), UNA MEMORIA (M) QUE TIENE UNA MEMORIA DE EMISION Y UNA MEMORIA DE RECEPCION, UNA MEMORIA DE CONTROL DE EMISION (FE) Y UNA MEMORIA DE CONTROL DE RECEPCION (FR). LAS MEMORIAS ESTAN ENLAZADAS AL CIRCUITO DE TRATAMIENTO POR UN BUS DE DATOS (BD) Y A UN PROCESADOR DE TRATAMIENTO DEL NIVEL 2.2 POR UN BUS (BP). LAS MEMORIAS DE CONTROL SON DE TIPO FIFO, ESCRIBIENDOSE LA MEMORIA DE CONTROL DE EMISION (FE) POR EL PROCESADOR Y LEYENDOSE MEDIANTE EL CIRCUITO DE TRATAMIENTO, Y LA MEMORIA DE CONTROL DE RECEPCION (FR) ESCRIBIENDOSE POR EL CIRCUITO DE TRATAMIENTO Y LEYENDOSE POR EL PROCESADOR. EL CIRCUITO DE TRATAMIENTO (CTP) EMITE Y RECIBE UNAS CELDAS QUE CONTIENEN INFORMACIONES DE SEÑALIZACION, Y PROPORCIONA FUNCIONES DE NIVEL 2.1DEL PROTOCOLO: DETECCION DE ERRORES DE TRANSMISION CELDA POR CELDA, DETECCION DE PERDIDAS O DE AÑADIDOS DE CELDAS, FRAGMENTACION EN CELDAS DE UN MENSAJE SUMINISTRADO POR EL PROCESADOR Y DESENTRELAZAMIENTO DE LAS CELDAS RELATIVAS A VARIOS MENSAJES EN LA RECEPCION.
ES90105680T 1989-03-30 1990-03-26 Dispositivo de tratamiento de mensajes de señalizacion en una red de telecomunicacion en tecnica temporal asincrona. Expired - Lifetime ES2068268T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8904168A FR2645380B1 (fr) 1989-03-30 1989-03-30 Dispositif de traitement de messages de signalisation dans un reseau de telecommunication en technique temporelle asynchrone

Publications (1)

Publication Number Publication Date
ES2068268T3 true ES2068268T3 (es) 1995-04-16

Family

ID=9380198

Family Applications (1)

Application Number Title Priority Date Filing Date
ES90105680T Expired - Lifetime ES2068268T3 (es) 1989-03-30 1990-03-26 Dispositivo de tratamiento de mensajes de señalizacion en una red de telecomunicacion en tecnica temporal asincrona.

Country Status (21)

Country Link
US (1) US5101403A (es)
EP (1) EP0390015B1 (es)
JP (1) JP2873044B2 (es)
KR (1) KR0140387B1 (es)
CN (1) CN1020033C (es)
AT (1) ATE115801T1 (es)
AU (1) AU623506B2 (es)
BR (1) BR9001458A (es)
CA (1) CA2013273C (es)
DE (1) DE69014949T2 (es)
DK (1) DK0390015T3 (es)
ES (1) ES2068268T3 (es)
FI (1) FI104868B (es)
FR (1) FR2645380B1 (es)
HK (1) HK144296A (es)
IL (1) IL93913A0 (es)
MX (1) MX172896B (es)
MY (1) MY107730A (es)
NO (1) NO302329B1 (es)
PH (1) PH27324A (es)
ZA (1) ZA902482B (es)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0453863A2 (en) * 1990-04-27 1991-10-30 National Semiconductor Corporation Methods and apparatus for implementing a media access control/host system interface
US5293377A (en) * 1990-10-05 1994-03-08 International Business Machines, Corporation Network control information without reserved bandwidth
GB2252020A (en) * 1990-12-04 1992-07-22 Ibm Flow control in data communication systems.
JP3365705B2 (ja) * 1995-05-24 2003-01-14 インターナショナル・ビジネス・マシーンズ・コーポレーション 分散型データ処理システム
JP2830774B2 (ja) * 1995-06-14 1998-12-02 日本電気株式会社 Ａｔｍ伝送装置
DE19530322A1 (de) * 1995-08-17 1997-02-20 Siemens Ag Verfahren zum Übertragen von Signalisierungsinformationen innerhalb eines Breitband-ISDN-Kommunikationsnetzes
US6269484B1 (en) 1997-06-24 2001-07-31 Ati Technologies Method and apparatus for de-interlacing interlaced content using motion vectors in compressed video streams
US20060126706A1 (en) * 2004-12-10 2006-06-15 Kevin Brand Auto-reboot modem
US7782873B2 (en) * 2005-08-23 2010-08-24 Slt Logic, Llc Omni-protocol engine for reconfigurable bit-stream processing in high-speed networks
US8189599B2 (en) * 2005-08-23 2012-05-29 Rpx Corporation Omni-protocol engine for reconfigurable bit-stream processing in high-speed networks
CN1976486B (zh) * 2005-11-28 2011-03-16 中兴通讯股份有限公司 一种信令转发***及其方法
US8115863B2 (en) * 2007-04-04 2012-02-14 Freescale Semiconductor, Inc. Video de-interlacer using pixel trajectory
US8964117B2 (en) 2007-09-28 2015-02-24 Ati Technologies Ulc Single-pass motion adaptive deinterlacer and method therefore
US8300987B2 (en) * 2007-09-28 2012-10-30 Ati Technologies Ulc Apparatus and method for generating a detail-enhanced upscaled image
US8259228B2 (en) * 2007-12-10 2012-09-04 Ati Technologies Ulc Method and apparatus for high quality video motion adaptive edge-directional deinterlacing
US8396129B2 (en) * 2007-12-28 2013-03-12 Ati Technologies Ulc Apparatus and method for single-pass, gradient-based motion compensated image rate conversion

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4748618A (en) * 1986-05-21 1988-05-31 Bell Communications Research, Inc. Telecommunications interface
FR2618279B1 (fr) * 1987-07-16 1989-10-20 Quinquis Jean Paul Systeme de commutation de paquets de donnees a priorites.
FR2618965B1 (fr) * 1987-07-30 1989-11-17 Servel Michel Systeme de commutation temporel de paquets de differentes longueurs

Also Published As

Publication number Publication date
US5101403A (en) 1992-03-31
DE69014949D1 (de) 1995-01-26
MY107730A (en) 1996-05-30
FR2645380B1 (fr) 1991-05-24
CN1047774A (zh) 1990-12-12
JP2873044B2 (ja) 1999-03-24
HK144296A (en) 1996-08-09
FI104868B (fi) 2000-04-14
FR2645380A1 (fr) 1990-10-05
ZA902482B (en) 1991-01-30
PH27324A (en) 1993-06-08
CN1020033C (zh) 1993-03-03
ATE115801T1 (de) 1994-12-15
JPH02288440A (ja) 1990-11-28
AU5211990A (en) 1990-10-04
EP0390015A1 (fr) 1990-10-03
DK0390015T3 (da) 1995-05-29
NO901413L (no) 1990-10-01
EP0390015B1 (fr) 1994-12-14
KR0140387B1 (ko) 1998-07-01
CA2013273A1 (fr) 1990-09-30
AU623506B2 (en) 1992-05-14
FI901560A0 (fi) 1990-03-28
MX172896B (es) 1994-01-19
IL93913A0 (en) 1990-12-23
CA2013273C (fr) 2000-09-05
KR900015498A (ko) 1990-10-27
NO901413D0 (no) 1990-03-28
DE69014949T2 (de) 1995-05-04
BR9001458A (pt) 1991-04-09
NO302329B1 (no) 1998-02-16

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