ES2047286T3 - Circuito integrado mos con tension de umbral ajustable. - Google Patents
Circuito integrado mos con tension de umbral ajustable.Info
- Publication number
- ES2047286T3 ES2047286T3 ES90402010T ES90402010T ES2047286T3 ES 2047286 T3 ES2047286 T3 ES 2047286T3 ES 90402010 T ES90402010 T ES 90402010T ES 90402010 T ES90402010 T ES 90402010T ES 2047286 T3 ES2047286 T3 ES 2047286T3
- Authority
- ES
- Spain
- Prior art keywords
- threshold voltage
- circuit
- adjustable threshold
- cell
- mos circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
- G11C11/5635—Erasing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5692—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency read-only digital stores using storage elements with more than two stable states
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Read Only Memory (AREA)
- Non-Volatile Memory (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Semiconductor Memories (AREA)
Abstract
LA CELULA MOS CON TENSION DE UMBRAL AJUSTABLE ES UNA CELULA DE DEMORIA, PROGRAMABLE Y BORRABLE ELECTRICAMENTE POR ALMACENAMIENTO DE CARGAS POR EFECTO TUNEL BAJO UNA REJILLA FLOTANTE. PARA LA OBTENCION DE UN CIRCUITO CON TENSION DE UMBRAL AJUSTABLE, LA CELULA SE "PROGRAMA" EN PRIMER LUGAR A CERO DE FORMA QUE TODAS LAS CARGAS ALMACENADAS SEAN EVACUADAS, DESPUES "BORRADA" CON FUENTE DE LA MASA, DRENAJE LLEVADO A FUERTE POTENCIAL Y REJILLA DE CONTROL LLEVADA AL POTENCIAL DESEADO PARA LA TENSION DE UMBRAL VT DEL CIRCUITO. AL FINAL DE ESTA FASE SE AJUSTA LA TENSION DE UMBRAL. APLICACION EN ESPECIAL EN CIRCUITOS DE TECNILOGIA MOS, REFERENCIAS DE TENSION PRECISAS, CIRCUITO DE TIPO DETECTOR O CONVERTIDOR ANALOGICO NUMERICO.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR8909780A FR2650109B1 (fr) | 1989-07-20 | 1989-07-20 | Circuit integre mos a tension de seuil ajustable |
Publications (1)
Publication Number | Publication Date |
---|---|
ES2047286T3 true ES2047286T3 (es) | 1994-02-16 |
Family
ID=9383970
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES90402010T Expired - Lifetime ES2047286T3 (es) | 1989-07-20 | 1990-07-12 | Circuito integrado mos con tension de umbral ajustable. |
Country Status (7)
Country | Link |
---|---|
US (1) | US5394359A (es) |
EP (1) | EP0409697B1 (es) |
JP (1) | JP2860308B2 (es) |
CA (1) | CA2021585C (es) |
DE (1) | DE69003321T2 (es) |
ES (1) | ES2047286T3 (es) |
FR (1) | FR2650109B1 (es) |
Families Citing this family (53)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5103160A (en) * | 1991-04-25 | 1992-04-07 | Hughes Aircraft Company | Shunt regulator with tunnel oxide reference |
US6222762B1 (en) * | 1992-01-14 | 2001-04-24 | Sandisk Corporation | Multi-state memory |
US5657332A (en) * | 1992-05-20 | 1997-08-12 | Sandisk Corporation | Soft errors handling in EEPROM devices |
JP2848223B2 (ja) * | 1993-12-01 | 1999-01-20 | 日本電気株式会社 | 不揮発性半導体記憶装置の消去方法及び製造方法 |
US5828601A (en) * | 1993-12-01 | 1998-10-27 | Advanced Micro Devices, Inc. | Programmed reference |
US5440505A (en) * | 1994-01-21 | 1995-08-08 | Intel Corporation | Method and circuitry for storing discrete amounts of charge in a single memory element |
CN1147866C (zh) * | 1994-06-02 | 2004-04-28 | 英特尔公司 | 含多级单元的快擦存储器的读出电路 |
US5508958A (en) * | 1994-09-29 | 1996-04-16 | Intel Corporation | Method and apparatus for sensing the state of floating gate memory cells by applying a variable gate voltage |
US5495453A (en) * | 1994-10-19 | 1996-02-27 | Intel Corporation | Low power voltage detector circuit including a flash memory cell |
GB9424598D0 (en) * | 1994-12-06 | 1995-01-25 | Philips Electronics Uk Ltd | Semiconductor memory with non-volatile memory transistor |
US5550772A (en) * | 1995-02-13 | 1996-08-27 | National Semiconductor Corporation | Memory array utilizing multi-state memory cells |
WO1996033496A1 (en) * | 1995-04-21 | 1996-10-24 | Advanced Micro Devices, Inc. | Reference for cmos memory cell having pmos and nmos transistors with a common floating gate |
JP3562043B2 (ja) * | 1995-07-19 | 2004-09-08 | ソニー株式会社 | 不揮発性記憶装置 |
FR2739737B1 (fr) * | 1995-10-09 | 1997-11-21 | Inside Technologies | Perfectionnements aux cartes a memoire |
FR2739706B1 (fr) * | 1995-10-09 | 1997-11-21 | Inside Technologies | Perfectionnements aux cartes a memoire |
US5701266A (en) * | 1995-12-14 | 1997-12-23 | Intel Corporation | Programming flash memory using distributed learning methods |
US5737265A (en) * | 1995-12-14 | 1998-04-07 | Intel Corporation | Programming flash memory using data stream analysis |
US5729489A (en) * | 1995-12-14 | 1998-03-17 | Intel Corporation | Programming flash memory using predictive learning methods |
US5677869A (en) * | 1995-12-14 | 1997-10-14 | Intel Corporation | Programming flash memory using strict ordering of states |
EP0833453B1 (en) * | 1996-09-30 | 2003-05-14 | STMicroelectronics S.r.l. | Current digital-analog converter using insulated gate MOS transistors |
EP0840452B1 (en) * | 1996-10-30 | 2001-07-18 | STMicroelectronics S.r.l. | Voltage comparator including at least an insulated gate MOS transistor and analogic/digital converters using the same |
JP3460170B2 (ja) * | 1997-02-03 | 2003-10-27 | シャープ株式会社 | 薄膜トランジスタ及びその製造方法 |
US5909449A (en) | 1997-09-08 | 1999-06-01 | Invox Technology | Multibit-per-cell non-volatile memory with error detection and correction |
JP4252183B2 (ja) * | 2000-02-17 | 2009-04-08 | 株式会社ルネサステクノロジ | 不揮発性半導体記憶装置、該不揮発性半導体記憶装置からのデータの読み出し方法及び、該不揮発性半導体記憶装置へのデータの書き込み方法 |
US6396744B1 (en) | 2000-04-25 | 2002-05-28 | Multi Level Memory Technology | Flash memory with dynamic refresh |
US6856568B1 (en) | 2000-04-25 | 2005-02-15 | Multi Level Memory Technology | Refresh operations that change address mappings in a non-volatile memory |
US7079422B1 (en) | 2000-04-25 | 2006-07-18 | Samsung Electronics Co., Ltd. | Periodic refresh operations for non-volatile multiple-bit-per-cell memory |
US7055007B2 (en) * | 2003-04-10 | 2006-05-30 | Arm Limited | Data processor memory circuit |
US7012835B2 (en) * | 2003-10-03 | 2006-03-14 | Sandisk Corporation | Flash memory data correction and scrub techniques |
US7173852B2 (en) * | 2003-10-03 | 2007-02-06 | Sandisk Corporation | Corrected data storage and handling methods |
JP4519713B2 (ja) * | 2004-06-17 | 2010-08-04 | 株式会社東芝 | 整流回路とこれを用いた無線通信装置 |
US7315916B2 (en) * | 2004-12-16 | 2008-01-01 | Sandisk Corporation | Scratch pad block |
US7395404B2 (en) * | 2004-12-16 | 2008-07-01 | Sandisk Corporation | Cluster auto-alignment for storing addressable data packets in a non-volatile memory array |
US7886204B2 (en) * | 2006-09-27 | 2011-02-08 | Sandisk Corporation | Methods of cell population distribution assisted read margining |
US7716538B2 (en) * | 2006-09-27 | 2010-05-11 | Sandisk Corporation | Memory with cell population distribution assisted read margining |
US7573773B2 (en) * | 2007-03-28 | 2009-08-11 | Sandisk Corporation | Flash memory with data refresh triggered by controlled scrub data reads |
US7477547B2 (en) * | 2007-03-28 | 2009-01-13 | Sandisk Corporation | Flash memory refresh techniques triggered by controlled scrub data reads |
FR2927732B1 (fr) | 2008-02-19 | 2011-05-27 | Commissariat Energie Atomique | Procede d'ajustement de la tension de seuil d'un transistor par une couche de piegeage enterree |
US8878511B2 (en) * | 2010-02-04 | 2014-11-04 | Semiconductor Components Industries, Llc | Current-mode programmable reference circuits and methods therefor |
US8188785B2 (en) | 2010-02-04 | 2012-05-29 | Semiconductor Components Industries, Llc | Mixed-mode circuits and methods of producing a reference current and a reference voltage |
US8680840B2 (en) * | 2010-02-11 | 2014-03-25 | Semiconductor Components Industries, Llc | Circuits and methods of producing a reference current or voltage |
KR20180015760A (ko) | 2010-09-03 | 2018-02-13 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 전계 효과 트랜지스터 및 반도체 장치의 제조 방법 |
US8687421B2 (en) | 2011-11-21 | 2014-04-01 | Sandisk Technologies Inc. | Scrub techniques for use with dynamic read |
JP5779162B2 (ja) | 2012-09-28 | 2015-09-16 | 株式会社東芝 | 整流回路とこれを用いた無線通信装置 |
US9230689B2 (en) | 2014-03-17 | 2016-01-05 | Sandisk Technologies Inc. | Finding read disturbs on non-volatile memories |
DE102014112001A1 (de) * | 2014-08-21 | 2016-02-25 | Infineon Technologies Austria Ag | Integrierte Schaltung mit einem Eingangstransistor einschließlich einer Ladungsspeicherstruktur |
JP2016058633A (ja) * | 2014-09-11 | 2016-04-21 | 株式会社東芝 | 撮像装置 |
US9552171B2 (en) | 2014-10-29 | 2017-01-24 | Sandisk Technologies Llc | Read scrub with adaptive counter management |
US9978456B2 (en) | 2014-11-17 | 2018-05-22 | Sandisk Technologies Llc | Techniques for reducing read disturb in partially written blocks of non-volatile memory |
US9349479B1 (en) | 2014-11-18 | 2016-05-24 | Sandisk Technologies Inc. | Boundary word line operation in nonvolatile memory |
US9449700B2 (en) | 2015-02-13 | 2016-09-20 | Sandisk Technologies Llc | Boundary word line search and open block read methods with reduced read disturb |
US9653154B2 (en) | 2015-09-21 | 2017-05-16 | Sandisk Technologies Llc | Write abort detection for multi-state memories |
US10446567B2 (en) * | 2017-03-31 | 2019-10-15 | Asahi Kasei Microdevices Corporation | Nonvolatile storage element and reference voltage generation circuit |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2514582C2 (de) * | 1975-04-03 | 1977-05-26 | Siemens Ag | Schaltung zur erzeugung von leseimpulsen |
US4357571A (en) * | 1978-09-29 | 1982-11-02 | Siemens Aktiengesellschaft | FET Module with reference source chargeable memory gate |
IT1224062B (it) * | 1979-09-28 | 1990-09-26 | Ates Componenti Elettron | Metodo di programmazione per una memoria a semiconduttore non volatile elettricamente alterabile |
US4336603A (en) * | 1980-06-18 | 1982-06-22 | International Business Machines Corp. | Three terminal electrically erasable programmable read only memory |
US4542485A (en) * | 1981-01-14 | 1985-09-17 | Tokyo Shibaura Denki Kabushiki Kaisha | Semiconductor integrated circuit |
DE3108726A1 (de) * | 1981-03-07 | 1982-09-16 | Deutsche Itt Industries Gmbh, 7800 Freiburg | Monolithisch integrierte referenzspannungsquelle |
US4495602A (en) * | 1981-12-28 | 1985-01-22 | Mostek Corporation | Multi-bit read only memory circuit |
WO1983003166A1 (en) * | 1982-03-09 | 1983-09-15 | Rca Corp | An electrically alterable, nonvolatile floating-gate memory device |
US4577215A (en) * | 1983-02-18 | 1986-03-18 | Rca Corporation | Dual word line, electrically alterable, nonvolatile floating gate memory device |
JPS5984398A (ja) * | 1982-11-08 | 1984-05-16 | Hitachi Ltd | Eeprom装置 |
JPS6032363A (ja) * | 1983-08-02 | 1985-02-19 | Nec Corp | 不揮発性半導体記憶装置の製造方法 |
JPS6084836A (ja) * | 1983-10-17 | 1985-05-14 | Hitachi Ltd | 半導体装置 |
JPH0638318B2 (ja) * | 1985-02-15 | 1994-05-18 | 株式会社リコー | Epromの書込み方法 |
JPH0772996B2 (ja) * | 1987-01-31 | 1995-08-02 | 株式会社東芝 | 不揮発性半導体メモリ |
JPS63221415A (ja) * | 1987-03-11 | 1988-09-14 | Sony Corp | 基準電圧発生装置 |
JPH01113999A (ja) * | 1987-10-28 | 1989-05-02 | Toshiba Corp | 不揮発性メモリのストレステスト回路 |
US4888630A (en) * | 1988-03-21 | 1989-12-19 | Texas Instruments Incorporated | Floating-gate transistor with a non-linear intergate dielectric |
-
1989
- 1989-07-20 FR FR8909780A patent/FR2650109B1/fr not_active Expired - Fee Related
-
1990
- 1990-07-12 DE DE90402010T patent/DE69003321T2/de not_active Expired - Fee Related
- 1990-07-12 EP EP90402010A patent/EP0409697B1/fr not_active Expired - Lifetime
- 1990-07-12 ES ES90402010T patent/ES2047286T3/es not_active Expired - Lifetime
- 1990-07-19 CA CA002021585A patent/CA2021585C/fr not_active Expired - Fee Related
- 1990-07-20 JP JP19282890A patent/JP2860308B2/ja not_active Expired - Fee Related
-
1992
- 1992-09-14 US US07/944,811 patent/US5394359A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
FR2650109B1 (fr) | 1993-04-02 |
JPH03214779A (ja) | 1991-09-19 |
CA2021585A1 (fr) | 1991-01-21 |
US5394359A (en) | 1995-02-28 |
DE69003321T2 (de) | 1994-01-13 |
JP2860308B2 (ja) | 1999-02-24 |
FR2650109A1 (fr) | 1991-01-25 |
EP0409697B1 (fr) | 1993-09-15 |
DE69003321D1 (de) | 1993-10-21 |
CA2021585C (fr) | 1994-02-22 |
EP0409697A1 (fr) | 1991-01-23 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
FG2A | Definitive protection |
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