ES2029820T3 - Procedimiento para la transmision de datos. - Google Patents

Procedimiento para la transmision de datos.

Info

Publication number
ES2029820T3
ES2029820T3 ES198787115652T ES87115652T ES2029820T3 ES 2029820 T3 ES2029820 T3 ES 2029820T3 ES 198787115652 T ES198787115652 T ES 198787115652T ES 87115652 T ES87115652 T ES 87115652T ES 2029820 T3 ES2029820 T3 ES 2029820T3
Authority
ES
Spain
Prior art keywords
assembly
assemblies
receiving
another
lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES198787115652T
Other languages
English (en)
Inventor
Hans-Jurgen Jakel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Force Computers GmbH
Original Assignee
Force Computers GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Force Computers GmbH filed Critical Force Computers GmbH
Application granted granted Critical
Publication of ES2029820T3 publication Critical patent/ES2029820T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/161—Computing infrastructure, e.g. computer clusters, blade chassis or hardware partitioning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Multi Processors (AREA)
  • Communication Control (AREA)
  • Information Transfer Systems (AREA)
  • Small-Scale Networks (AREA)
  • Hardware Redundancy (AREA)

Abstract

EL INVENTO SE TRATA DE UNA COMPUTADORA CON AL MENOS UN GRUPO DE CONSTRUCCION, TRANSMITIENDO Y AL MENOS DOS, RECIBIENDO, DONDE AL MENOS LOS GRUPOS DE CONSTRUCCION, QUE RECIBEN (16, 20) ESTAN CONECTADOS SOBRE DIRECCIONES CONECTADOS PARALELAMENTE, UNO AL OTRO, Y DONDE HAY PREVISTOS DIRECCIONES DE SEÑAS (A31 A A0), CON CUAL CADA GRUPO DE CONSTRUCCION, QUE RECIBE ES REACCIONABLE INEQUIVOCAMENTE. ADEMAS EL GRUPO DE CONSTRUCCION, QUE REACCIONA A TRAVES DE LA SEÑAL DE DIRECCION HABITUAL, LEE LOS DATOS PREPARADOS EN LA DIRECCION DE DATOS (D31 A D0). EN EL GRUPO DE CONSTRUCCION, QUE TRANSMITE HAY PREVISTO UN DISPOSITIVO DE DESCIFRA, QUE DESCIFRA LAS DIRECCIONES DE SEÑAS, CORRESPONDIENTES A CADA GRUPO DE CONSTRUCCION, QUE RECIBE, DE MANERA QUE ES POSIBLE UNA REACCION, AL MISMO TIEMPO, DE VARIOS GRUPOS DE CONSTRUCCION. LOS GRUPOS DE CONSTRUCCION, QUE RECIBEN (16, 20) ESTAN CONECTADOS, UNO CON OTRO, Y CON LOS GRUPOS DE CONSTRUCCION, QUE TRANSMITEN, A TRAVES DE UN DIRECCION COMUN DE LA RETROALIMENTACION.
ES198787115652T 1987-03-02 1987-10-24 Procedimiento para la transmision de datos. Expired - Lifetime ES2029820T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE3706734A DE3706734C1 (de) 1987-03-02 1987-03-02 Verfahren zur UEbertragung von Daten sowie Computer

Publications (1)

Publication Number Publication Date
ES2029820T3 true ES2029820T3 (es) 1992-10-01

Family

ID=6322134

Family Applications (1)

Application Number Title Priority Date Filing Date
ES198787115652T Expired - Lifetime ES2029820T3 (es) 1987-03-02 1987-10-24 Procedimiento para la transmision de datos.

Country Status (6)

Country Link
US (1) US4969089A (es)
EP (1) EP0280767B1 (es)
JP (1) JPH0724050B2 (es)
AT (1) ATE72708T1 (es)
DE (2) DE3706734C1 (es)
ES (1) ES2029820T3 (es)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69132130T2 (de) * 1990-05-15 2000-09-28 Canon Kk Gerät und Verfahren zur Informationserkennung
US5397861A (en) * 1992-10-21 1995-03-14 Mupac Corporation Electrical interconnection board
US5519877A (en) * 1993-01-12 1996-05-21 Matsushita Electric Industrial Co., Ltd. Apparatus for synchronizing parallel processing among a plurality of processors
US5483458A (en) * 1993-12-09 1996-01-09 Pitney Bowes Inc. Programmable clock module for postage metering control system
US5974402A (en) * 1993-12-09 1999-10-26 Pitney Bowes Inc. Address decoder with memory wait state circuit
DE19541946A1 (de) * 1995-11-10 1997-05-15 Daimler Benz Aerospace Ag Verfahren zur Speicher-Zugriffssteuerung für 32-Bit-Hochleistungs-Mikroprozessoren der 3. Generation
US6665762B2 (en) 2001-01-03 2003-12-16 Force Computers, Inc. Computer having a plurality of plug-in cards
US8645959B2 (en) * 2005-03-30 2014-02-04 Intel Corporaiton Method and apparatus for communication between two or more processing elements

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4141067A (en) * 1977-06-13 1979-02-20 General Automation Multiprocessor system with cache memory
JPS55135925A (en) * 1979-04-09 1980-10-23 Nec Corp Information transfer device
US4479814A (en) * 1980-07-07 1984-10-30 Near Equilibrium Research Associates Recirculation regeneration
US4342995A (en) * 1980-09-15 1982-08-03 Burroughs Corporation Data network employing a single transmission bus for overlapping data transmission and acknowledgment signals
US4394731A (en) * 1980-11-10 1983-07-19 International Business Machines Corporation Cache storage line shareability control for a multiprocessor system
JPS58213321A (ja) * 1982-06-03 1983-12-12 Omron Tateisi Electronics Co デ−タ転送方法
JPS59133624A (ja) * 1983-01-20 1984-08-01 Sharp Corp インタ−フエイス方式
GB8422328D0 (en) * 1984-09-04 1984-10-10 Int Computers Ltd Data processing apparatus
AU4907285A (en) * 1984-11-09 1986-05-15 Spacelabs, Inc. Communications bus broadcasting
US4797815A (en) * 1985-11-22 1989-01-10 Paradyne Corporation Interleaved synchronous bus access protocol for a shared memory multi-processor system
US4791641A (en) * 1986-09-15 1988-12-13 Thinking Machines Corporation Parallel processor error checking
US4785394A (en) * 1986-09-19 1988-11-15 Datapoint Corporation Fair arbitration technique for a split transaction bus in a multiprocessor computer system

Also Published As

Publication number Publication date
JPH0724050B2 (ja) 1995-03-15
ATE72708T1 (de) 1992-03-15
EP0280767A2 (de) 1988-09-07
US4969089A (en) 1990-11-06
DE3776784D1 (de) 1992-03-26
DE3706734C1 (de) 1988-03-17
EP0280767B1 (de) 1992-02-19
JPS63228363A (ja) 1988-09-22
EP0280767A3 (en) 1989-04-05

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