EP4325564A1 - Integrierte schaltungsvorrichtungen mit einer rückseitigen stromverteilungsnetzwerkstruktur und verfahren zu ihrer herstellung - Google Patents
Integrierte schaltungsvorrichtungen mit einer rückseitigen stromverteilungsnetzwerkstruktur und verfahren zu ihrer herstellung Download PDFInfo
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- EP4325564A1 EP4325564A1 EP23189410.6A EP23189410A EP4325564A1 EP 4325564 A1 EP4325564 A1 EP 4325564A1 EP 23189410 A EP23189410 A EP 23189410A EP 4325564 A1 EP4325564 A1 EP 4325564A1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
- H01L21/823425—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
Definitions
- the present disclosure generally relates to the field of integrated circuit devices and, more particularly, to integrated circuit devices including a backside power distribution network (BSPDN) structure.
- BSPDN backside power distribution network
- an integrated circuit device including elements formed in a substrate or on a backside of the substrate has been proposed to simplify the middle-of-line (MOL) portion and/or the back-end-of-line (BEOL) portion of device fabrication.
- MOL middle-of-line
- BEOL back-end-of-line
- An integrated circuit devices may include a transistor including a channel region and a source/drain region contacting the channel region, a power rail that is configured be electrically connected to a power source and is spaced apart from the source/drain region in a first direction, and a power contact that is between the source/drain region and the power rail and contacts both the source/drain region and the power rail.
- the channel region may overlap the power contact in the first direction.
- An integrated circuit devices may include a transistor including a channel region and a source/drain region.
- the source/drain region includes a side surface contacting the channel region.
- the integrated circuit devices may also include a power rail that is configured be electrically connected to a power source and is spaced apart from the source/drain region in a first direction and a power contact that is between the source/drain region and the power rail and contacts both the source/drain region and the power rail.
- a side surface of the power contact may protrude in a second direction beyond the side surface of the source/drain region, and the second direction may be perpendicular to the first direction.
- a method of forming an integrated circuit devices may include etching an upper surface of a substrate to form an opening in the substrate, forming a sacrificial element in the opening of the substrate, and forming a transistor including a channel region and a source/drain region contacting the channel region.
- An upper surface of the sacrificial element faces the source/drain region.
- the methods may also include removing a lower portion of the substrate to expose a lower surface of the sacrificial element, replacing the sacrificial element with a power contact, and forming a power rail that contacts a lower surface of the power contact.
- the source/drain region may contact an upper surface of the power contact.
- an integrated circuit device may include a power contact that may be formed by replacing a placeholder in a substrate.
- the placeholder may be formed before performing the front-end-of-line (FEOL) portion of device fabrication, and thus the power contact may be formed without increasing the complexity of the MOL and/or BEOL portions of device fabrication.
- FEOL front-end-of-line
- a BSPDN structure may be formed on the power contact. The BSPDN structure may simplify the MOL portion and/or the BEOL portion of device fabrication.
- FIG. 1 is a cross-sectional view of a first integrated circuit device 110 according to some embodiments.
- the first integrated circuit device 110 may include a first transistor and a second transistor on a substrate 12 that includes an upper surface 12U and a lower surface 12L.
- the surface 12U may be opposite to the lower surface 12L in a first direction Z (also referred to as a vertical direction).
- the upper surface 12U of the substrate 12 may extend in a second direction X (also referred to as a first horizontal direction) and a third direction Y (also referred to as a second horizontal direction).
- the upper surface 12U of the substrate 12 may be parallel to the lower surface 12L of the substrate 12.
- the second direction X and the third direction Y may be parallel to the upper surface 12U and the lower surface 12L of the substrate 12.
- the second direction X may be perpendicular to the third direction Y.
- the substrate 12 may include semiconductor material(s), for example, Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC and/or InP or may include insulating material(s), for example, silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride and/or a low-k material.
- the substrate 12 may be a bulk substrate (e.g., a bulk silicon substrate) or a semiconductor on insulator (SOI) substrate.
- the substrate 12 may be a silicon wafer or may be a single insulating layer.
- a thickness of the substrate 12 in the first direction Z may be in a range of 50 nm to 100 nm.
- the first direction Z may be perpendicular to the second direction X.
- the low-k material may include fluorine-doped silicon oxide, organosilicate glass, carbon-doped oxide, porous silicon dioxide, porous organosilicate glass, spin-on organic polymeric dielectrics and/or spin-on silicon based polymeric dielectric.
- the first integrated circuit device 110 may further include a first interlayer 14 that may be provided on the upper surface 12U of the substrate 12.
- the first interlayer 14 may extend between the substrate 12 and the first and second transistors and may contact the upper surface 12U of the substrate 12 and the first and second transistors.
- the first interlayer 14 may include insulating material(s) (e.g., silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride and/or a low-k material).
- the first transistor may include a first channel region 22_1.
- the first transistor may include multiple first channel regions 22_1 stacked in the first direction Z, and the first channel regions 22_1 may be spaced apart from each other in the first direction Z, as illustrated in FIG. 1 .
- the first transistor may also include a first gate structure that may include a first gate insulator 23_1 and a first gate electrode 24_1.
- the first channel region 22_1 may extend through the first gate electrode 24_1 in the second direction X, and the first gate insulator 23_1 may be provided between the first gate electrode 24_1 and the first channel region 22_1.
- the first gate insulator 23_1 may contact the first gate electrode 24_1 and the first channel region 22_1.
- the second transistor may include a second channel region 22_2.
- the second transistor may include multiple second channel regions 22_2 stacked in the first direction Z, and the second channel regions 22_2 may be spaced apart from each other in the first direction Z, as illustrated in FIG. 1 .
- the second transistor may also include a second gate structure that may include a second gate insulator 23_2 and a second gate electrode 24_2.
- the second channel region 22_2 may extend through the second gate electrode 24_2 in the second direction X, and the second gate insulator 23_2 may be provided between the second gate electrode 24_2 and the second channel region 22_2.
- the second gate insulator 23_2 may contact the second gate electrode 24_2 and the second channel region 22_2.
- the first transistor may include first and second source/drain regions 26_2 and 26_1 that may be spaced apart from each other in the second direction X, and the first gate structure may be provided between the first and second source/drain regions 26_2 and 26_1.
- the first and second source/drain regions 26_2 and 26_1 may contact opposing side surfaces of the first channel region 22_1, respectively, as illustrated in FIG. 1 .
- the second transistor may include the first source/drain region 26_2 and a third source/drain region 26_3 that may be spaced apart from each other in the second direction X, and the second gate structure may be provided between the first and third source/drain regions 26_2 and 26_3.
- the first and third source/drain regions 26_2 and 26_3 may contact opposing side surfaces of the second channel region 22_2, respectively, as illustrated in FIG. 1 .
- the first source/drain region 26_2 may also be referred to as a common source/drain region, as the first source/drain region 26_2 is shared by the first and second transistors.
- Each of the first and second channel regions 22_1 and 22_2 may include semiconductor material(s) (e.g., Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC and/or InP).
- the first and second channel regions 22_1 and 22_2 may include the same material(s).
- each of the first and second channel regions 22_1 and 22_2 may be a nanosheet that may have a thickness in a range of from 1 nm to 100 nm in the first direction Z or may be a nanowire that may have a circular cross-section with a diameter in a range of from 1 nm to 100 nm.
- Each of the first and second gate insulators 23_1 and 23_2 may include a single layer or multiple layers (e.g., a silicon oxide layer and/or a high-k material layer).
- the high-k material layer may include Al 2 O 3 , HfO 2 , ZrO 2 , HfZrO 4 , TiO 2 , Sc 2 O 3 Y 2 O 3 , La 2 O 3 , Lu 2 O 3 , Nb 2 O 5 and/or Ta 2 O 5 .
- each of the first and second gate insulators 23_1 and 23_2 may include the same material(s).
- each of the first and second gate electrodes 24_1 and 24_2 may include a single layer or multiple layers.
- each of the first and second gate electrodes 24_1 and 24_2 may include a metallic layer that includes, for example, tungsten (W), aluminum (Al), copper (Cu), molybdenum (Mo) and/or ruthenium (Ru) and may additionally include work function layer(s) (e.g., a TiN layer, a TaN layer, a TiAl layer, a TiC layer, a TiAlC layer, a TiAlN layer and/or a WN layer).
- the first and second gate electrodes 24_1 and 24_2 may include the same material(s).
- the work function layer(s) may be provided between the metallic layer and the gate insulator (i.e., one of the first and second gate insulators 23_1 and 23_2). In some embodiments, the work function layer(s) may separate the metallic layer from the gate insulator.
- Each of the first, second and third source/drain regions 26_2, 26_1 and 26_3 may include a semiconductor layer (e.g., a silicon layer and/or a silicon germanium layer) and may additionally include dopants in the semiconductor layer.
- each of the first, second and third source/drain regions 26_2, 26_1 and 26_3 may include a metal layer that includes, for example, W, Al, Cu, Mo and/or Ru.
- the first and second transistors may also respectively include first and second insulating spacers 25_1 and 25_2 (also referred to as a gate spacer or an inner gate spacer).
- the first insulating spacer 25_1 may be provided between the first gate electrode 24_1 and the first and second source/drain regions 26_2 and 26_1 and/or may be provided between the first gate electrode 24_1 and the first interlayer 14.
- opposing surfaces of the first insulating spacer 25_1 may respectively contact the first gate electrode 24_1 and one of the first and second source/drain regions 26_2 and 26_1 and may respectively contact the first gate electrode 24_1 and the first interlayer 14, as illustrated in FIG. 1 .
- the first channel region 22_1 may extend through the first insulating spacer 25_1 in the second direction X, as illustrated in FIG. 1 .
- the second insulating spacer 25_2 may be provided between the second gate electrode 24_2 and the first and third source/drain regions 26_2 and 26_3 and/or may be provided between the second gate electrode 24_2 and the first interlayer 14. In some embodiments, opposing surfaces of the second insulating spacer 25_2 may respectively contact the second gate electrode 24_2 and one of the first and third source/drain regions 26_2 and 26_3 and may respectively contact the second gate electrode 24_2 and the first interlayer 14, as illustrated in FIG. 1 .
- the second channel region 22_2 may extend through the second insulating spacer 25_2 in the second direction X, as illustrated in FIG. 1 .
- Each of the first and second insulating spacers 25_1 and 25_2 may include, for example, silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride and/or a low-k material.
- a second interlayer 41 may be provided on the first interlayer 14, and the first and second transistors may be provided in the second interlayer 41.
- FIG. 1 illustrates the second interlayer 41 as a single layer, in some embodiments, the second interlayer 41 may include multiple layers.
- a source/drain contact 42 may be provided in the second interlayer 41 on the second source/drain region 26_1.
- the source/drain contact 42 may contact an upper surface of the second source/drain region 26_1.
- the source/drain contact 42 may electrically connect the second source/drain region 26_1 to a conductive element (e.g., a conductive wire or a conductive via plug) of a BEOL structure 50 that is formed through the BEOL portion of device fabrication.
- a conductive element e.g., a conductive wire or a conductive via plug
- a lower surface refers to a surface facing the substrate 12
- an upper surface refers to a surface opposite the lower surface.
- a lower portion refers to a portion that is closer than “an upper portion” to the substrate 12 and thus is between the upper portion and the substrate 12.
- the BEOL structure 50 may include a BEOL insulating layer, conductive wires (e.g., metal wires) that are provided in the BEOL insulating layer and are stacked in the first direction Z, and conductive via plugs (e.g., metal via plugs), each of which may electrically connect two conductive wires that are spaced apart from each other in the first direction Z.
- conductive wires e.g., metal wires
- conductive via plugs e.g., metal via plugs
- Each of the first and second interlayers 14 and 41 and the BEOL insulating layer may include, for example, silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride and/or a low-k material.
- the first integrated circuit device 110 may further include a power contact 62 and a BSPDN structure 70.
- the power contact 62 may include an upper portion in the first interlayer 14 and a lower portion in the substrate 12. In some embodiments, the power contact 62 may extend through the first interlayer 14 and the substrate 12 in the first direction Z, and the power contact 62 (e.g., an upper surface of the power contact 62) may contact the first source/drain region 26_2 (e.g., a lower surface of the first source/drain region 26_2), as illustrated in FIG. 1 . Further, the power contact 62 (e.g., the upper surface of the power contact 62) may contact the first and second insulating spacers 25_1 and 25_2, as illustrated in FIG. 1 . In some embodiments, the power contact 62 may contact only one of the first and second insulating spacers 25_1 and 25_2.
- the power contact 62 includes a first portion that the first channel region 22_1 overlaps in the first direction Z and a second portion that the second channel region 22_2 overlaps in the first direction Z.
- the power contact 62 may include only one of the first and second portions.
- each of the first and second gate electrodes 24_1 and 24_2 may overlap a portion of the power contact 62 in the first direction Z.
- "an element A overlapping an element B in a direction X" means that there is at least one line that extends in the direction X and intersects both the elements A and B.
- the upper surface of the power contact 62 may have a width in the second direction X, which is wider than a width of the lower surface of the first source/drain region 26_2 in the second direction X, as illustrated in FIG. 1 .
- a side surface 62ss of the power contact 62 may protrude in the second direction X beyond a side surface 26_2ss of the first source/drain region 26_2, as illustrated in FIG. 1 .
- a width of the power contact 62 in the second direction X may decrease with increasing distance from the first source/drain region 26_2 in the first direction Z, as illustrated in FIG. 1 .
- a width of the power contact 62 in the third direction Y may also decrease with increasing distance from the first source/drain region 26_2 in the first direction Z.
- the power contact 62 may electrically connect the first source/drain region 26_2 to a conductive element (e.g., a conductive wire or a conductive via plug) of the BSPDN structure 70.
- the BSPDN structure 70 may include, for example, a power rail 72 and a backside insulator 74 in which the power rail 72 is provided.
- the power rail 72 may be electrically connected to a power source with a predetermined voltage (e.g., a drain voltage or a source voltage), and thus the first source/drain region 26_2 may be electrically connected to the power source through the power contact 62 and the power rail 72.
- the power contact 62 may contact both the first source/drain region 26_2 and the power rail 72.
- the backside insulator 74 is illustrated as a single layer, in some embodiments, the backside insulator 74 may include multiple layers stacked on the lower surface 12L of the substrate 12. Further, although the BSPDN structure 70 is illustrated as contacting the lower surface 12L of the substrate 12, in some embodiments, an intervening structure may be provided between the substrate 12 and the BSPDN structure 70 and may separate the substrate 12 from the BSPDN structure 70.
- Each of the power contact 62 and the power rail 72 may include, for example, metal element(s) (e.g., W, Al, Cu, Mo and/or Ru), and the backside insulator 74 may include, for example, silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride and/or a low-k material.
- metal element(s) e.g., W, Al, Cu, Mo and/or Ru
- the backside insulator 74 may include, for example, silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride and/or a low-k material.
- FIG. 2 is a cross-sectional view of a second integrated circuit device 120 according to some embodiments.
- the second integrated circuit device 120 is similar to the first integrated circuit device 110.
- the second integrated circuit device 120 may be different from the first integrated circuit device 110, in that the first source/drain region 26_2 may have a first center 26_2c in the second direction X, and the first center 26_2c may be offset from a center 62c of a power contact 62o in the second direction X, as illustrated in FIG. 2 .
- the second channel region 22_2 and a portion of the first source/drain region 26_2 may not overlap the power contact 62o in the first direction Z, as illustrated in FIG. 2 but, in some other embodiments, the second channel region 22_2 and an entirety of the first source/drain region 26_2 may overlap the power contact 62o.
- a center may be interchangeable with "a center point.”
- FIG. 3 is a cross-sectional view of a third integrated circuit device 130 according to some embodiments.
- the third integrated circuit device 130 is similar to the first integrated circuit device 110.
- the third integrated circuit device 130 may differ from the first integrated circuit device 110, in that the third integrated circuit device 130 includes a power contact 62n that has an upper surface having a width in the second direction X, and that width of the power contact 62n is narrower than a width of the lower surface of the first source/drain region 26_2 in second direction X.
- opposing edge portions of the first source/drain region 26_2 may not overlap the power contact 62n in the first direction Z.
- the power contact 62n may have a second center 62nc in the second direction X, and the first center 26_2c of the first source/drain region 26_2 may be aligned with the second center 62nc of the power contact 62n in the first direction Z, as illustrated in FIG. 3 .
- the first center 26_2c and the second center 62nc may be offset in the second direction X.
- FIG. 4 is a cross-sectional view of a fourth integrated circuit device 140 according to some embodiments.
- the fourth integrated circuit device 140 is similar to the first integrated circuit device 110.
- the fourth integrated circuit device 140 may differ from the first integrated circuit device 110, in that the fourth integrated circuit device 140 includes a power contact 62a including an upper surface that has a width in the second direction X, and that width of the power contact 62a is the same as the width of the lower surface of the first source/drain region 26_2 in the second direction X.
- FIG. 5 is a cross-sectional view of a fifth integrated circuit device 150 according to some embodiments.
- the fifth integrated circuit device 150 is similar to the first integrated circuit device 110.
- the fifth integrated circuit device 150 may differ from the first integrated circuit device 110, in that the fifth integrated circuit device 150 includes a power contact 62m contacting both the first and second source/drain regions 26_2 and 26_1 (e.g., lower surfaces of the first and second source/drain regions 26_2 and 26_1), and a source/drain contact (e.g., the source/drain contact 42 in FIG. 1 ) may be omitted.
- a source/drain contact e.g., the source/drain contact 42 in FIG. 1
- the first transistor including the first and second source/drain regions 26_2 and 26_1 may be a dummy transistor that does not function as a transistor.
- the first gate electrode 24_1 may not be electrically connected to any conductive element when the first transistor is a dummy transistor.
- FIG. 6 is a cross-sectional view of a sixth integrated circuit device 160 according to some embodiments.
- the sixth integrated circuit device 160 is similar to the first integrated circuit device 110.
- the sixth integrated circuit device 160 may differ from the first integrated circuit device 110, in that each of the first and second transistors includes a single channel region (e.g., a first channel region 22_1' or a second channel region 22_2').
- the single channel region may be referred to as a fin-shaped channel region, and each of the first and second transistors may be referred to as a fin field-effect transistor (FinFET).
- FinFET fin field-effect transistor
- first to fifth integrated circuit devices 110, 120, 130, 140 and 150 may include the first and second transistors, each of which includes a single fin-shaped channel region and is a FinFET.
- FIG. 7 is a cross-sectional view of a seventh integrated circuit device 170 according to some embodiments.
- the seventh integrated circuit device 170 is similar to the first integrated circuit device 110.
- the seventh integrated circuit device 170 may differ from the first integrated circuit device 110, in that the seventh integrated circuit device 170 further includes a first upper transistor and a second upper transistor.
- the first upper transistor may be provided on the first transistor, and thus the first transistor may be between the substrate 12 and the first upper transistor.
- the first upper transistor may include a first upper channel region 22_1U.
- the first upper transistor may include multiple first upper channel regions 22_1U stacked in the first direction Z, and the first upper channel regions 22_1U may be spaced apart from each other in the first direction Z, as illustrated in FIG. 7 .
- the first transistor may also include a first upper gate structure that may include a first upper gate insulator 23_1U and a first upper gate electrode 24_1U.
- the first upper channel region 22_1U may extend through the first upper gate electrode 24_1U in the second direction X, and the first upper gate insulator 23_1U may be provided between the first upper gate electrode 24_1U and the first upper channel region 22_1U.
- the first upper gate insulator 23_1U may contact first upper gate electrode 24_1U and the first upper channel region 22_1U.
- the second upper transistor may be provided on the second transistor, and thus the second transistor may be between the substrate 12 and the second upper transistor.
- the second upper transistor may include a second upper channel region 22_2U.
- the upper second transistor may include multiple second upper channel regions 22_2U stacked in the first direction Z, and the second upper channel regions 22_2U may be spaced apart from each other in the first direction Z, as illustrated in FIG. 7 .
- the second upper transistor may also include a second upper gate structure that may include a second upper gate insulator 23_2U and a second upper gate electrode 24_2U.
- the second upper channel region 22_2U may extend through the second upper gate electrode 24_2U in the second direction X, and the second upper gate insulator 23_2U may be provided between the second upper gate electrode 24_2U and the second upper channel region 22_2U.
- the second upper gate insulator 23_2U may contact the second upper gate electrode 24_2U and the second upper channel region 22_2U.
- the first upper transistor may include first and second upper source/drain regions 26_2U and 26_1U that may be spaced apart from each other in the second direction X, and the first upper gate structure may be provided between the first and second upper source/drain regions 26_2U and 26_1U.
- the first and second upper source/drain regions 26_2U and 26_1U may contact opposing side surfaces of the first upper channel region 22_1U, respectively, as illustrated in FIG. 7 .
- the second upper transistor may include the first upper source/drain region 26_2U and a third upper source/drain region 26_3U that may be spaced apart from each other in the second direction X, and the second upper gate structure may be provided between the second and third upper source/drain regions 26_2U and 26_3U.
- the second and third upper source/drain regions 26_2U and 26_3U may contact opposing side surfaces of the second upper channel region 22_2U, respectively, as illustrated in FIG. 7 .
- the first upper source/drain region 26_2U may also be referred to as a common upper source/drain region, as the first upper source/drain region 26_2U is shared by the first and second upper transistors.
- the seventh integrated circuit device 170 may also include a third interlayer 31 that is provided between the first transistor and the first upper transistor and between the second transistor and the second upper transistor.
- the third interlayer 31 may be between and may contact the second source/drain region 26_1 and the second upper source/drain region 26_1U, may be between and may contact the first source/drain region 26_2 and the first upper source/drain region 26_2U, and may be between and may contact the third source/drain region 26_3 and the third upper source/drain region 26_3U, as illustrated in FIG. 7 .
- the third interlayer 31 may include, for example, silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride and/or a low-k material.
- a source/drain contact 42' may be provided on the second upper source/drain region 26_1U and may contact an upper surface of the second upper source/drain region 26_1U.
- the first transistor and the first upper transistor may have different conductivity types and may collectively form a first complementary metal-oxide-semiconductor (CMOS) structure
- CMOS complementary metal-oxide-semiconductor
- the second transistor and the second upper transistor may have different conductivity types and may collectively form a second CMOS structure.
- CMOS complementary metal-oxide-semiconductor
- each of the first transistor, the first upper transistor, the second transistor and the second upper transistor may include a single fin-shaped channel region and may be a FinFET.
- Each of the elements of the first and second upper transistors may include material(s) the same as the material(s) of a corresponding element of the first and second transistors.
- the second upper source/drain region 26_1U may include material(s) the same as the material(s) of the second source/drain region 26_1
- the second upper gate electrode 24_2U may include material(s) the same as the material(s) of the second gate electrode 24_2.
- FIG. 8 is a flow chart of methods of forming the first integrated circuit device 110 according to some embodiments
- FIGS. 9 through 14 are cross-sectional views illustrating those methods according to some embodiments.
- the methods may include etching an upper surface 10U of a preliminary substrate 10 (also referred to as a substrate) to form an opening 15 in the preliminary substrate 10 and then forming a placeholder 16 (e.g., a sacrificial layer or a sacrificial element) in the opening 15 of the preliminary substrate 10 (Block 210).
- a first interlayer 14 may be formed on the upper surface 10U of the preliminary substrate 10 before forming the opening 15, and the opening 15 may be formed in the first interlayer 14 and the preliminary substrate 10. The opening 15 may not extend completely through the preliminary substrate 10 in the first direction Z.
- the preliminary substrate 10 may include one or more semiconductor materials, for example, Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC and/or InP or may include insulating material, for example, silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride and/or a low-k material.
- the preliminary substrate 10 may be a bulk substrate (e.g., a bulk silicon substrate) or a semiconductor on insulator (SOI) substrate.
- the preliminary substrate 10 may be a silicon wafer or may be an insulating layer.
- the placeholder 16 may have a width in the second direction X decreasing in a depth direction of the opening 15, as illustrated in FIG. 10 .
- An upper surface 16U of the placeholder 16 may be coplanar with an upper surface of the first interlayer 14.
- a lower surface 16L of the placeholder 16 may be in the preliminary substrate 10.
- the placeholder 16 may include, for example, a semiconductor material and/or an insulating material (e.g., SiGe, SiN or SiBCN).
- the placeholder 16 may include a SiGe layer including about 25 at% of germanium (e.g., from 15 at% to 25 at%).
- a source/drain region e.g., the second source/drain region 26_1 or the first source/drain region 26_2 in FIG.
- a germanium concentration of the source/drain region may be higher than the germanium concentration of the SiGe layer of the placeholder 16.
- the germanium concentration of the source/drain region may be about 55 at% (e.g., from 40 at% to 70 at%).
- a transistor (e.g., the first transistor or the second transistor discussed with reference to FIG. 1 ) may be formed on the placeholder 16 (Block 220).
- a first source/drain region 26_2 (e.g., a lower surface of the first source/drain region 26_2) may contact the placeholder 16 (e.g., the upper surface of the placeholder 16).
- a second interlayer 41 may be formed on the transistor and a source/drain contact 42 may be formed on a second source/drain region 26_1.
- a BEOL structure 50 may be formed on the second interlayer 41.
- the preliminary substrate 10 may be removed by performing process(es) (e.g., a grinding process, a wet etching process, a dry etching process and/or a Chemical Mechanical Polishing (CMP) process) on a preliminary lower surface 10L of the preliminary substrate 10, and a lower portion, including the lower surface 16L, of the placeholder 16 may be exposed (Block 230).
- process(es) e.g., a grinding process, a wet etching process, a dry etching process and/or a Chemical Mechanical Polishing (CMP) process
- CMP Chemical Mechanical Polishing
- a substrate 12 may be formed on the placeholder 16 and the first interlayer 14.
- the placeholder 16 may be provided in the substrate 12 and may contact the substrate 12.
- the lower surface 16L of the placeholder 16 may be coplanar with the lower surface 12L of the substrate 12.
- the placeholder 16 may be replaced with a power contact 62 (Block 240).
- the power contact 62 may have a lower surface 62L that is coplanar with the lower surface 12L of the substrate 12.
- a power rail 72 of a BSPDN structure 70 may be formed (Block 250) on the power contact 62 and on the lower surface 12L of the substrate 12.
- the power rail 72 may contact the lower surface 62L of the power contact 62.
- second, third, fourth, fifth, sixth and seventh integrated circuit devices 120, 130, 140, 150, 160 and 170 can be formed by methods similar to those described with reference to FIGS. 9 -15 with appropriate modification thereto.
- Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments and intermediate structures of example embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments herein should not be construed as limited to the particular shapes illustrated herein but may include deviations in shapes that result, for example, from manufacturing.
- spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
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Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US202263371928P | 2022-08-19 | 2022-08-19 | |
US18/147,739 US20240063122A1 (en) | 2022-08-19 | 2022-12-29 | Integrated circuit devices including a back side power distribution network structure and methods of forming the same |
Publications (1)
Publication Number | Publication Date |
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EP4325564A1 true EP4325564A1 (de) | 2024-02-21 |
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EP23189410.6A Pending EP4325564A1 (de) | 2022-08-19 | 2023-08-03 | Integrierte schaltungsvorrichtungen mit einer rückseitigen stromverteilungsnetzwerkstruktur und verfahren zu ihrer herstellung |
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US (1) | US20240063122A1 (de) |
EP (1) | EP4325564A1 (de) |
KR (1) | KR20240026078A (de) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20220139911A1 (en) * | 2020-10-30 | 2022-05-05 | Intel Corporation | Use of a placeholder for backside contact formation for transistor arrangements |
US20220238659A1 (en) * | 2021-01-27 | 2022-07-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Backside Contact With Air Spacer |
-
2022
- 2022-12-29 US US18/147,739 patent/US20240063122A1/en active Pending
-
2023
- 2023-06-12 KR KR1020230075056A patent/KR20240026078A/ko unknown
- 2023-08-03 EP EP23189410.6A patent/EP4325564A1/de active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20220139911A1 (en) * | 2020-10-30 | 2022-05-05 | Intel Corporation | Use of a placeholder for backside contact formation for transistor arrangements |
US20220238659A1 (en) * | 2021-01-27 | 2022-07-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Backside Contact With Air Spacer |
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Publication number | Publication date |
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KR20240026078A (ko) | 2024-02-27 |
US20240063122A1 (en) | 2024-02-22 |
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