EP4091197A1 - Method for manufacturing an image sensor - Google Patents

Method for manufacturing an image sensor

Info

Publication number
EP4091197A1
EP4091197A1 EP21719689.8A EP21719689A EP4091197A1 EP 4091197 A1 EP4091197 A1 EP 4091197A1 EP 21719689 A EP21719689 A EP 21719689A EP 4091197 A1 EP4091197 A1 EP 4091197A1
Authority
EP
European Patent Office
Prior art keywords
semiconductor layer
layer
substrate
transferred
donor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP21719689.8A
Other languages
German (de)
French (fr)
Inventor
Walter Schwarzenbach
David HERISSON
Alain DELPY
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Publication of EP4091197A1 publication Critical patent/EP4091197A1/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/1469—Assemblies, i.e. hybrid integration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14687—Wafer level processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14689—MOS based technologies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14698—Post-treatment for the devices, e.g. annealing, impurity-gettering, shor-circuit elimination, recrystallisation

Definitions

  • the invention relates to a method of manufacturing an image sensor.
  • the manufacture of an image sensor by three-dimensional (3D) integration involves a successive stacking of different layers comprising in particular photodiodes each defining a pixel of the image sensor, components of the pixel reading circuit and interconnections between said components. and pixels.
  • Figure 1 is a schematic sectional view of an image sensor.
  • Said sensor comprises successively:
  • each pixel comprises a doped region 12 adapted to collect the electric charges generated in each pixel; the pixels are separated from each other by electrically insulating trenches 13,
  • dielectric or electrically insulating layers 14 for example silicon nitride or silicon oxide
  • a silicon layer 22 which comprises components 25 of the pixel reading circuit.
  • Interconnects 26 extend through layer 14 to electrically connect components 25 and pixels 11.
  • a 3D integration process has significant constraints.
  • the method bears the cost of consuming such a substrate.
  • the thermal budget of the successive steps must be controlled so as not to damage the active zones or the components previously formed.
  • too high a thermal budget is likely to generate an abnormal diffusion of the doped regions configured to collect the photo-generated electric charges in the pixel, which can affect performance. of said sensor.
  • metallic connections between elements of the sensor are liable to be damaged by too high a thermal budget.
  • An aim of the invention is to design a method of manufacturing an image sensor according to a 3D integration technology, in which the thickness control of the transferred layer is compatible with a substrate of the FDSOI type, which is rapidly industrializable and inexpensive while avoiding the diffusion of dopants present in the regions for collecting electric charges and in the doped layer of amorphous silicon.
  • An SOI substrate (acronym for the English term “Semiconductor On Insulator”) is a substrate comprising a semiconductor layer, for example made of silicon, on a substrate, an electrically insulating layer being interposed between the semiconductor layer and the substrate .
  • the semiconductor layer In an FDSOI substrate (acronym for the English term “Fully Depleted Semiconductor On Insulator”), the semiconductor layer has a sufficiently thin thickness to allow complete depletion of the conduction channel of a transistor formed in said layer. Such a layer typically has a thickness of a few tens of nanometers.
  • the invention provides a method of manufacturing an image sensor, comprising:
  • a receiver substrate comprising a base substrate and an active layer comprising pixels, each pixel comprising a doped region for collecting the electrical charges generated in the pixel, said receiver substrate being devoid of metal interconnections,
  • finishing treatment comprising (i) thinning of the transferred layer by sacrificial oxidation followed by chemical etching and (ii) smoothing of the semiconductor layer transferred by means of at least one rapid annealing.
  • rapid annealing is meant in the present text a heat treatment exhibiting a rise in temperature at a rate greater than 10 ° C per second, preferably of the order of 50 ° C per second or even more.
  • the receiving substrate only comprises doped zones but no metallic interconnection makes certain heat treatments acceptable for smoothing the transferred semiconductor layer, said heat treatments having to however present a sufficiently moderate thermal budget for not to cause diffusion of the dopants present in the receiving substrate. Rapid annealing as implemented in the present invention meets this constraint.
  • controlled chemical etching provides the uniformity of thickness required for the intended application.
  • This thickness uniformity is similar to that of FDSOI substrates, for which the uniformity criterion can be expressed, on the one hand, by the variability of the thickness of the layer transferred within the same substrate or plate. , said intra-plate variability being typically less than or equal to 10 A, and, on the other hand, by the variability of the average thickness of the layer transferred between different plates, said plate-to-plate variability typically being of the order ⁇ 2 A maximum.
  • each rapid annealing is controlled to avoid diffusion of dopants from the doped regions of the pixels.
  • each rapid annealing can be carried out at a temperature of between 1100 and 1250 ° C. for a period of between 15 and 60 s.
  • the sacrificial oxidation and chemical etching are controlled to thin the transferred single crystal semiconductor layer to a thickness between 10 and 100nm.
  • the chemical etching of thinning of the transferred monocrystalline semiconductor layer can be carried out by means of wet etching, dry plasma etching, dry etching by ion beam, or dry etching. by ion beam in aggregates.
  • the method further comprises, after finishing the transferred single crystal semiconductor layer, forming components of a pixel readout circuit in or on said transferred semiconductor layer.
  • the method further comprises, after finishing the transferred single crystal semiconductor layer, forming interconnections between the pixels and said components of the pixel read circuit.
  • the method includes forming the weakening layer by implanting atomic species into the donor substrate.
  • the finishing treatment successively comprises:
  • the donor substrate further comprises, on the monocrystalline semiconductor layer, a layer of silicon oxide, preferably deposited from tetraethyl orthosilicate (TEOS).
  • TEOS tetraethyl orthosilicate
  • the donor substrate may further include one or more electrically insulating or semiconducting layers (or a stack of these two types of layers) on the silicon oxide layer.
  • a semiconductor layer it can be crystalline or amorphous, doped (N + or P +) or undoped.
  • the silicon oxide layer is deposited on the donor substrate prior to implantation.
  • the receiver substrate further comprises one or more electrically insulating or semiconducting layers (or a stack of these two types of layers) on the active layer.
  • at least one electrically insulating layer is a silicon oxide layer and the semiconductor layer can be crystalline or amorphous, doped (N + or P +) or undoped.
  • each rapid annealing has a temperature rise rate greater than 10 ° C. per second, preferably greater than or equal to 50 ° C. per second.
  • the smoothing does not include any heat treatment having a temperature rise rate of less than 10 ° C. per second.
  • the smoothing is implemented individually for each structure comprising the semiconductor layer and the receiver substrate.
  • FIG. 1 is a schematic sectional view of an image sensor
  • FIG. 2 is a schematic sectional view of a recipient substrate and a donor substrate used in a method of manufacturing an image sensor according to one embodiment of the invention
  • FIG. 3 is a schematic sectional view of the recipient substrate and the donor substrate of Figure 2 after detachment of the donor substrate according to the weakening zone;
  • FIG. 4 is a schematic sectional view of the image sensor formed from the donor and recipient substrates of FIG. 3, after finishing the transferred semiconductor layer and forming the circuit for reading the pixels and the interconnections;
  • FIG. 5 is a SIMS profile of the phosphorus concentration within an SOI structure comprising a layer doped with phosphorus at the end of a rapid annealing as implemented in the present invention and of a heat treatment as implemented during the manufacture of an FDSOI substrate.
  • the invention proposes to manufacture an image sensor by transferring a thin layer from a donor substrate to a recipient substrate.
  • the receiver substrate includes a base substrate and an active layer comprising a plurality of pixels.
  • the base substrate is generally a semiconductor substrate, for example of silicon. Said base substrate has in particular a function of mechanical support of the image sensor.
  • the active layer is a monocrystalline semiconductor layer, for example of silicon or of silicon-germanium.
  • the pixels are separated from each other by electrically insulating trenches. These trenches are known by the acronym DTI from the Anglo-Saxon term “Deep Trench Isolation” or CDTI from the Anglo-Saxon term “Capacitor Deep Trench Isolation”.
  • Each pixel comprises a doped region adapted to collect the electrical charges generated in each pixel.
  • the receiving substrate does not include any metallic interconnection between its components.
  • the donor substrate comprises an embrittlement zone which delimits a monocrystalline semiconductor thin layer.
  • the donor substrate can be a solid substrate, made from a single monocrystalline semiconductor material.
  • the donor substrate can be a composite substrate made up of at least two layers of different materials, comprising at least one monocrystalline semiconductor layer.
  • the monocrystalline thin film can be a layer of silicon, or of another semiconductor material.
  • the weakening zone is advantageously formed by implantation of atomic species, such as hydrogen and / or helium, in the donor substrate. The determination of the dose and of the implantation energy to form the weakening zone at a given depth of the donor substrate is within the abilities of those skilled in the art.
  • the surface of the donor substrate may optionally be protected by a dielectric layer, such as a layer of silicon oxide (S1O2). Said layer can then be removed, for example by selective etching.
  • the donor substrate is then bonded to the recipient substrate.
  • the bonding can be accomplished through a dielectric layer, such as a silicon oxide layer.
  • a fracture of the donor substrate is initiated at the area of weakness, leading to detachment of the donor substrate along the area of weakness. After this detachment, the semiconductor thin film was transferred to the recipient substrate.
  • This process is well known as the Smart Cut TM process.
  • the final product comprising the receiving substrate and the thin semiconductor layer will be referred to as a wafer in the present text.
  • the transferred semiconductor thin layer exhibits a certain roughness
  • a finishing treatment is carried out on the plate in order to smooth said layer while ensuring the required uniformity of thickness.
  • the target thickness for the transferred semiconductor layer is between 10 nm and 100 nm, with a maximum variation of ⁇ 5 ⁇ from the target value, within each wafer and between the different wafers made by the process.
  • This uniformity criterion is generally required for the manufacture of FDSOI substrates, but cannot be obtained for the targeted image sensor with the usual finishing treatment for FDSOI substrates which has an excessively high thermal budget.
  • the finishing treatment of FDSOI substrates typically comprises a so-called “batch anneal” process, which is a long smoothing process, at high temperature, advantageously carried out in an oven making it possible to treat a plurality of substrates at the same time (from where the term "batch").
  • Such a “batch anneal” is typically carried out at a temperature of between 1150 and 1200 ° C., for a period of several minutes, generally greater than 15 minutes.
  • the rise in temperature in the oven is relatively slow, with a ramp of the order of a few ° C. per minute, which contributes to increasing the thermal budget suffered by the substrate.
  • This smoothing makes it possible to bring the transferred semiconductor layer to a surface roughness level compatible with the manufacture of transistors.
  • the finishing treatment implemented in the invention comprises on the one hand a thinning of the layer transferred by sacrificial oxidation followed by a chemical etching and on the other hand a smoothing by means of one or more annealing ( s) fast (s) which provide a lower thermal budget than that of a “batch anneal”, said thermal budget being adapted to preserve the integrity of the pixels.
  • the treatment first comprises oxidation of the transferred layer so as to form a thin oxide layer on the surface of said layer.
  • This oxide is preferably formed by thermal oxidation of the material of the semiconductor layer, during which the transferred semiconductor layer is subjected to a heat treatment in an oxidizing atmosphere comprising oxygen and / or vapor. water, which has the effect of consuming a surface part of said layer.
  • an oxidizing atmosphere comprising oxygen and / or vapor. water, which has the effect of consuming a surface part of said layer.
  • the duration of the oxidation is chosen according to the thickness of oxide to be formed, which depends on the initial thickness of the transferred layer and on the target thickness of said layer. Such oxidation can be carried out simultaneously on one or more batches of plates.
  • the thickness of the transferred layer covered with the oxide layer is then measured at a number of points distributed over the surface of the plate.
  • an ellipsometric or reflectometry measurement provides the thickness of the semiconductor layer.
  • a thickness map of said layer obtained by ellipsometry or reflectometry is used. From the thicknesses measured at different points on the plate, we can also determine the average thickness of the semiconductor layer.
  • This thickness map and / or this average thickness make it possible to determine one or more regions of the transferred layer having excess thicknesses. relative to a target thickness and therefore to be subject to thinning in order to improve the uniformity of the thickness of the transferred semiconductor layer.
  • the measured thickness is compared at each point with the target thickness of the desired end product, said target thickness being less than or equal to the average thickness.
  • the region or regions to be thinned are therefore the region or regions in which the thickness of the semiconductor layer is greater than the target thickness, the extra thickness (s) corresponding to the difference between the measured thickness and the thickness. target thickness. This is therefore one or more "local" thicknesses of the plate.
  • the average of the thicknesses of the semiconductor layer measured at the different measurement points is compared with a target average thickness.
  • a wafer to be thinned is a wafer for which the average thickness of the semiconductor layer is greater than the target average thickness, the extra thickness corresponding to the difference between these two average thicknesses. This is therefore an "overall" extra thickness of the plate.
  • a selective etching of the sacrificial oxide layer is first implemented.
  • An etching agent suitable for etching the sacrificial oxide without attacking the semiconductor material of the layer is used for this purpose.
  • a solution of hydrofluoric acid (HF) is used as the etchant.
  • HF hydrofluoric acid
  • the etching is wet etching, that is, in which the transferred semiconductor layer is exposed to an etching solution.
  • the exposure can be carried out by immersing the plate in said solution, or by spraying the etching solution on the surface of the plate by means of a nozzle, which can make it possible to locate the etch at regions to be thinned out. compared to other regions of the plaque.
  • This etching can be carried out at room temperature, that is to say of the order of 20 to 25 ° C, or at a higher temperature but generally less than 80 ° C.
  • the etching may be dry plasma etching, dry etching by ion beam ("Reactive Ion Etching” according to English terminology), dry etching by ion beam in aggregates (GCIB, acronym of the Anglo-Saxon term “Gas Cluster Ion Beam”). These steps do not involve a significant thermal budget.
  • each annealing is typically carried out at a temperature of between 1100 and 1250 ° C for a period of between 15 and 60 s, which allows a reorganization of the atoms on the surface of the transferred semiconductor layer and thus to smooth it.
  • RTA rapid Thermal Annealing
  • each rapid anneal is carried out with a rapid rise in temperature, of the order of a few tens of ° C per second.
  • rapid annealing is carried out individually on each plate.
  • the thermal budget implemented during this (these) annealing (s) is low enough to avoid diffusion of dopants within the plate.
  • the process comprises two rapid anneals, in order to obtain an optimum surface condition of the transferred layer.
  • the smoothing implemented in the present invention does not include any “batch anneal”. More generally, said smoothing does not include any slow heat treatment, that is to say having a temperature rise rate of less than 10 ° C per second. The integrity of the pixels is therefore preserved during smoothing.
  • the method comprises two sacrificial oxidation steps, implemented respectively between the first and the second rapid annealing and after the second rapid annealing when two rapid annealing are implemented.
  • the first sacrificial oxidation advantageously makes it possible to remove the defects linked to the implantation of embrittlement by oxidizing a surface region of the layer transferred and removing said oxidized region, while the second sacrificial oxidation, which is followed by chemical etching of the transferred layer, uniformly thin the transferred layer to the target thickness.
  • the rapid anneals are preferably carried out before the thinning of the transferred layer, in order to preserve the stability of said layer. It would be possible to do without the first rapid annealing but at the cost of degradation of the roughness.
  • Said components are moreover electrically connected to the pixels by interconnections.
  • Said interconnections may be metallic but, insofar as they are formed after the finishing treatment of the transferred semiconductor layer, they are not liable to be damaged by it.
  • the image sensor it may be useful to insert one or more additional semiconductor and / or electrically insulating layers between the active layer and the semiconductor layer comprising the components of the read circuit.
  • said additional layers can be formed on the active layer of the recipient substrate, before the bonding of the donor substrate.
  • These layers can be formed, for example, by deposition. Whatever training method is chosen, it does not involve a thermal budget likely to diffuse the dopants from the active layer.
  • At least one of said additional layers can be formed by deposition on the active layer of the recipient substrate and at least another of said additional layers is formed by deposition on the monocrystalline semiconductor layer of the donor substrate, before coating. bonding of said substrates.
  • the deposition of each additional layer on the active layer of the receiving substrate must be carried out with a sufficiently low thermal budget so as not to generate diffusion of the dopants.
  • said additional layers are formed on the donor substrate.
  • said layers are formed by deposition before implantation of the atomic species making it possible to form the weakening zone.
  • the thermal budget of these deposits does not risk causing a premature fracture of the donor substrate along the weakening zone. If said additional layers are deposited after the formation of the weakening zone, the thermal budget applied will have to be limited in order to avoid such a premature fracture.
  • FIG. 2 is a schematic sectional view of the donor substrate and of the recipient substrate before their bonding in one embodiment of the invention.
  • the receiving substrate 1 successively comprises:
  • an active layer comprising a plurality of pixels 11, each pixel comprising a doped region 12 adapted to collect the electric charges generated in each pixel; the pixels are separated from each other by electrically insulating trenches 13,
  • first additional layer 15 for example semiconductor
  • the donor substrate 2 comprises a weakening zone 200 delimiting a thin semiconductor layer 201.
  • the layer 16, and possibly the layer 15, could be formed on the donor substrate 2 instead of the recipient substrate 1.
  • each layer concerned is intended to be transferred onto the recipient substrate with the layer 201. .
  • the donor substrate is bonded to the recipient substrate, then the donor substrate is detached along the weakening zone, so as to transfer the semiconductor layer 201 onto the recipient substrate 1.
  • the surface S of the layer 201 after detachment is rough.
  • components of the read circuit are formed in or on said layer (see Figure 4).
  • Interconnections 26 are also formed between the components 25 and the pixels 11.
  • FIG. 5 is an SI MS profile (acronym of the English term “Secondary ion mass spectrometry”, that is to say secondary ion mass spectrometry) of the phosphorus concentration within an SOI structure comprising successively from its surface a layer of undoped monocrystalline silicon 42 nm thick, a silicon oxide layer 190 nm thick, a layer of phosphorus doped silicon extending to a depth of 3500 nm, and an unintentionally doped silicon base substrate, after two rapid anneals at 1200 ° C for 30 seconds, as implemented in the present invention (curve a) and a heat treatment (" batch anneal ”) at 1200 ° C for 5 minutes, as used during the manufacture of an FDSOI substrate (curve b).
  • SI MS profile as acronym of the English term “Secondary ion mass spectrometry”, that is to say secondary ion mass spectrometry
  • the x-axis indicates the depth (in nm) from the surface of the SOI structure
  • the y-axis indicates the phosphorus concentration (in at / cm 2 ).
  • the clear transition (substantially vertical slope) between the doped layer and the base substrate visible on curve a shows that there was substantially no diffusion of the dopants during the rapid annealing.
  • the more gradual transition visible on curve b reflects a phenomenon of diffusion of dopants from the doped layer towards the base substrate.
  • Mansoorian 2009 Mansoorian, B., and D. Shaver, with Suntharalingam, V. et al.,

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Element Separation (AREA)

Abstract

The invention relates to a method for manufacturing an image sensor, comprising: - providing a receiver substrate (1) comprising a base substrate (10) and an active layer comprising pixels (11), each pixel comprising a doped region (12) for collecting the electric charge generated in the pixel, said receiver substrate (1) being devoid of metal interconnects; - providing a donor substrate (2) comprising a weakened region (200) bounding a single-crystal semiconductor layer (201); - bonding the donor substrate (2) to the receiver substrate (1); - detaching the donor substrate (2) along the weakened region (200), so as to transfer the semiconductor layer (201) to the receiver substrate (1); - implementing a treatment for finishing the transfer semiconductor layer (201), said finishing treatment comprising (i) thinning the transferred layer by sacrificial oxidation followed by chemical etching and (ii) smoothing the transferred semiconductor layer by means of at least one rapid anneal.

Description

PROCEDE DE FABRICATION D’UN CAPTEUR D’IMAGE PROCESS FOR MANUFACTURING AN IMAGE SENSOR
Domaine technique Technical area
L’invention concerne un procédé de fabrication d’un capteur d’image. The invention relates to a method of manufacturing an image sensor.
Etat de la technique State of the art
La fabrication d’un capteur d’image par intégration tridimensionnelle (3D) implique un empilement successif de différentes couches comprenant notamment des photodiodes définissant chacune un pixel du capteur d’image, des composants du circuit de lecture des pixels et des interconnexions entre lesdits composants et les pixels. The manufacture of an image sensor by three-dimensional (3D) integration involves a successive stacking of different layers comprising in particular photodiodes each defining a pixel of the image sensor, components of the pixel reading circuit and interconnections between said components. and pixels.
On pourra se référer par exemple à [Mansoorian 2009] pour la description d’un capteur d’image formé par intégration 3D. Reference may be made, for example, to [Mansoorian 2009] for the description of an image sensor formed by 3D integration.
La figure 1 est une vue schématique en coupe d’un capteur d’image. Figure 1 is a schematic sectional view of an image sensor.
Ledit capteur comprend successivement : Said sensor comprises successively:
- un substrat de base 10, - a base substrate 10,
- une couche active comprenant une pluralité de pixels 11 ; chaque pixel comprend une région dopée 12 adaptée pour collecter les charges électriques générées dans chaque pixel ; les pixels sont séparés les uns des autres par des tranchées électriquement isolantes 13, an active layer comprising a plurality of pixels 11; each pixel comprises a doped region 12 adapted to collect the electric charges generated in each pixel; the pixels are separated from each other by electrically insulating trenches 13,
- une ou des couches diélectriques ou électriquement isolantes 14, par exemple du nitrure de silicium ou de l’oxyde de silicium, - one or more dielectric or electrically insulating layers 14, for example silicon nitride or silicon oxide,
- une couche de silicium 22, qui comprend des composants 25 du circuit de lecture des pixels. a silicon layer 22, which comprises components 25 of the pixel reading circuit.
Des interconnexions 26 s’étendent au travers de la couche 14 pour relier électriquement les composants 25 et les pixels 11. Interconnects 26 extend through layer 14 to electrically connect components 25 and pixels 11.
Toutefois, un procédé d’intégration 3D présente des contraintes importantes. Ainsi, dans une approche conventionnelle de collage et de consommation d’un substrat sacrificiel, le procédé supporte le coût de la consommation d’un tel substrat. Dans une approche comportant un transfert de couche, par exemple par le procédé SmartCut™, le budget thermique des étapes successives doit être contrôlé pour ne pas endommager les zones actives ou les composants précédemment formés. D’une façon générale, et suivant les références disponibles dans la littérature, un budget thermique trop élevé est susceptible d’engendrer une diffusion anormale des régions dopées configurées pour collecter les charges électriques photo-générées dans le pixel, ce qui peut affecter les performances dudit capteur. De même, des connexions métalliques entre des éléments du capteur sont susceptibles d’être endommagées par un budget thermique trop élevé. However, a 3D integration process has significant constraints. Thus, in a conventional approach to bonding and consuming a sacrificial substrate, the method bears the cost of consuming such a substrate. In an approach comprising a layer transfer, for example by the SmartCut ™ process, the thermal budget of the successive steps must be controlled so as not to damage the active zones or the components previously formed. In general, and according to the references available in the literature, too high a thermal budget is likely to generate an abnormal diffusion of the doped regions configured to collect the photo-generated electric charges in the pixel, which can affect performance. of said sensor. Likewise, metallic connections between elements of the sensor are liable to be damaged by too high a thermal budget.
Cependant, la mise en oeuvre d’étapes à faible budget thermique peut être pénalisante notamment en termes de durée et/ou de coût du procédé. Résumé de l’invention However, the implementation of steps with a low thermal budget can be penalizing in particular in terms of the duration and / or cost of the process. Summary of the invention
Un but de l’invention est de concevoir un procédé de fabrication d’un capteur d’image selon une technologie d’intégration 3D, dont le contrôle d’épaisseur de la couche reportée soit compatible avec un substrat de type FDSOI, qui soit rapidement industrialisable et peu onéreux tout en évitant la diffusion des dopants présents dans les régions de collecte des charges électriques et dans la couche dopée de silicium amorphe. An aim of the invention is to design a method of manufacturing an image sensor according to a 3D integration technology, in which the thickness control of the transferred layer is compatible with a substrate of the FDSOI type, which is rapidly industrializable and inexpensive while avoiding the diffusion of dopants present in the regions for collecting electric charges and in the doped layer of amorphous silicon.
Un substrat SOI (acronyme du terme anglo-saxon « Semiconductor On Insulator ») est un substrat comprenant une couche semi-conductrice, par exemple en silicium, sur un substrat, une couche électriquement isolante étant intercalée entre la couche semi-conductrice et le substrat. Dans un substrat FDSOI (acronyme du terme anglo-saxon « Fully Depleted Semiconductor On Insulator »), la couche semi- conductrice présente une épaisseur suffisamment fine pour permettre une déplétion complète du canal de conduction d’un transistor formé dans ladite couche. Une telle couche présente typiquement une épaisseur de quelques dizaines de nanomètres. An SOI substrate (acronym for the English term “Semiconductor On Insulator”) is a substrate comprising a semiconductor layer, for example made of silicon, on a substrate, an electrically insulating layer being interposed between the semiconductor layer and the substrate . In an FDSOI substrate (acronym for the English term "Fully Depleted Semiconductor On Insulator"), the semiconductor layer has a sufficiently thin thickness to allow complete depletion of the conduction channel of a transistor formed in said layer. Such a layer typically has a thickness of a few tens of nanometers.
A cet effet, l’invention propose un procédé de fabrication d’un capteur d’image, comprenant : To this end, the invention provides a method of manufacturing an image sensor, comprising:
- la fourniture d’un substrat receveur comprenant un substrat de base et une couche active comprenant des pixels, chaque pixel comprenant une région dopée de collecte des charges électriques générées dans le pixel, ledit substrat receveur étant dépourvu d’interconnexions métalliques, - the provision of a receiver substrate comprising a base substrate and an active layer comprising pixels, each pixel comprising a doped region for collecting the electrical charges generated in the pixel, said receiver substrate being devoid of metal interconnections,
- la fourniture d’un substrat donneur comprenant une zone de fragilisation délimitant une couche semi-conductrice monocristalline, - the supply of a donor substrate comprising an embrittlement zone delimiting a monocrystalline semiconductor layer,
- le collage du substrat donneur sur le substrat receveur, - the bonding of the donor substrate on the recipient substrate,
- le détachement du substrat donneur le long de la zone de fragilisation, de sorte à transférer la couche semi-conductrice sur le substrat receveur, - the detachment of the donor substrate along the weakening zone, so as to transfer the semiconductor layer to the recipient substrate,
- la mise en oeuvre d’un traitement de finition de la couche semi-conductrice transférée, ledit traitement de finition comprenant (i) un amincissement de la couche transférée par oxydation sacrificielle suivie d’une gravure chimique et (ii) un lissage de la couche semi-conductrice transférée au moyen d’au moins un recuit rapide. - the implementation of a finishing treatment of the transferred semiconductor layer, said finishing treatment comprising (i) thinning of the transferred layer by sacrificial oxidation followed by chemical etching and (ii) smoothing of the semiconductor layer transferred by means of at least one rapid annealing.
Par « recuit rapide », on entend dans le présent texte un traitement thermique présentant une montée en température à une vitesse supérieure à 10°C par seconde, de préférence de l’ordre de 50°C par seconde voire davantage. By "rapid annealing" is meant in the present text a heat treatment exhibiting a rise in temperature at a rate greater than 10 ° C per second, preferably of the order of 50 ° C per second or even more.
Le fait que le substrat receveur comprenne uniquement des zones dopées mais aucune interconnexion métallique rend acceptable certains traitements thermiques permettant de lisser la couche semi-conductrice transférée, lesdits traitements thermiques devant toutefois présenter un budget thermique suffisamment modéré pour ne pas engendrer de diffusion des dopants présents dans le substrat receveur. Un recuit rapide tel que mis en oeuvre dans la présente invention répond à cette contrainte. The fact that the receiving substrate only comprises doped zones but no metallic interconnection makes certain heat treatments acceptable for smoothing the transferred semiconductor layer, said heat treatments having to however present a sufficiently moderate thermal budget for not to cause diffusion of the dopants present in the receiving substrate. Rapid annealing as implemented in the present invention meets this constraint.
Par ailleurs, la gravure chimique contrôlée procure l’uniformité d’épaisseur requise pour l’application visée. Cette uniformité d’épaisseur est similaire à celle des substrats FDSOI, pour lesquels le critère d’uniformité peut s’exprimer, d’une part, par la variabilité de l’épaisseur de la couche transférée au sein d’un même substrat ou plaque, ladite variabilité intra-plaque étant typiquement inférieure ou égale à 10 A, et, d’autre part, par la variabilité de l’épaisseur moyenne de la couche transférée entre différentes plaques, ladite variabilité de plaque à plaque étant typiquement de l’ordre de ± 2 A au maximum. In addition, controlled chemical etching provides the uniformity of thickness required for the intended application. This thickness uniformity is similar to that of FDSOI substrates, for which the uniformity criterion can be expressed, on the one hand, by the variability of the thickness of the layer transferred within the same substrate or plate. , said intra-plate variability being typically less than or equal to 10 A, and, on the other hand, by the variability of the average thickness of the layer transferred between different plates, said plate-to-plate variability typically being of the order ± 2 A maximum.
De manière particulièrement avantageuse, chaque recuit rapide est contrôlé pour éviter une diffusion des dopants des régions dopées des pixels. In a particularly advantageous manner, each rapid annealing is controlled to avoid diffusion of dopants from the doped regions of the pixels.
A cet effet, chaque recuit rapide peut être mis en oeuvre à une température comprise entre 1100 et 1250°C pendant une durée comprise entre 15 et 60 s. To this end, each rapid annealing can be carried out at a temperature of between 1100 and 1250 ° C. for a period of between 15 and 60 s.
Dans certains modes de réalisation, l’oxydation sacrificielle et la gravure chimique sont contrôlées pour amincir la couche semi-conductrice monocristalline transférée jusqu’à une épaisseur comprise entre 10 et 100 nm. In some embodiments, the sacrificial oxidation and chemical etching are controlled to thin the transferred single crystal semiconductor layer to a thickness between 10 and 100nm.
La gravure chimique d’amincissement de la couche semi-conductrice monocristalline transférée peut être mise en oeuvre au moyen d’une gravure humide, d’une gravure sèche par plasma, d’une gravure sèche par faisceau ionique, ou d’une gravure sèche par faisceau d’ions en agrégats. The chemical etching of thinning of the transferred monocrystalline semiconductor layer can be carried out by means of wet etching, dry plasma etching, dry etching by ion beam, or dry etching. by ion beam in aggregates.
Dans certains modes de réalisation, le procédé comprend en outre, après la finition de la couche semi-conductrice monocristalline transférée, la formation de composants d’un circuit de lecture des pixels dans ou sur ladite couche semi- conductrice transférée. In some embodiments, the method further comprises, after finishing the transferred single crystal semiconductor layer, forming components of a pixel readout circuit in or on said transferred semiconductor layer.
Dans certains modes de réalisation, le procédé comprend en outre, après la finition de la couche semi-conductrice monocristalline transférée, la formation d’interconnexions entre les pixels et lesdits composants du circuit de lecture des pixels. In some embodiments, the method further comprises, after finishing the transferred single crystal semiconductor layer, forming interconnections between the pixels and said components of the pixel read circuit.
Dans certains modes de réalisation, le procédé comprend la formation de la couche de fragilisation par implantation d’espèces atomiques dans le substrat donneur. In some embodiments, the method includes forming the weakening layer by implanting atomic species into the donor substrate.
Dans certains modes de réalisation, le traitement de finition comprend successivement : In some embodiments, the finishing treatment successively comprises:
(i) un premier recuit rapide, (i) a first rapid annealing,
(ii) un retrait de défauts liés à l’implantation par oxydation sacrificielle de la couche transférée, (ii) removal of defects associated with implantation by sacrificial oxidation of the transferred layer,
(iii) un second recuit rapide, et (iii) a second rapid annealing, and
(iv) l’amincissement de la couche transférée. Dans certains modes de réalisation, le substrat donneur comprend en outre, sur la couche semi-conductrice monocristalline, une couche d’oxyde de silicium, préférentiellement déposée à partir d’orthosilicate de tétraéthyle (TEOS). (iv) thinning of the transferred layer. In certain embodiments, the donor substrate further comprises, on the monocrystalline semiconductor layer, a layer of silicon oxide, preferably deposited from tetraethyl orthosilicate (TEOS).
Le substrat donneur peut en outre comprendre une ou plusieurs couches électriquement isolantes ou semi-conductrices (ou un empilement de ces deux types de couches) sur la couche d’oxyde de silicium. Dans le cas d’une couche semi-conductrice, celle-ci peut être cristalline ou amorphe, dopée (N+ ou P+) ou non dopée. The donor substrate may further include one or more electrically insulating or semiconducting layers (or a stack of these two types of layers) on the silicon oxide layer. In the case of a semiconductor layer, it can be crystalline or amorphous, doped (N + or P +) or undoped.
Dans certains modes de réalisation, la couche d’oxyde de silicium, respectivement la couche ou l’empilement de couches disposé sur la couche d’oxyde de silicium, est déposée sur le substrat donneur avant l’implantation. In some embodiments, the silicon oxide layer, respectively the layer or stack of layers disposed on the silicon oxide layer, is deposited on the donor substrate prior to implantation.
Dans certains modes de réalisation, le substrat receveur comprend en outre une ou plusieurs couches électriquement isolantes ou semi-conductrices (ou un empilement de ces deux types de couches) sur la couche active. Préférentiellement au moins une couche électriquement isolante est une couche d’oxyde de silicium et la couche semi- conductrice peut être cristalline ou amorphe, dopée (N+ ou P+) ou non dopée. In certain embodiments, the receiver substrate further comprises one or more electrically insulating or semiconducting layers (or a stack of these two types of layers) on the active layer. Preferably at least one electrically insulating layer is a silicon oxide layer and the semiconductor layer can be crystalline or amorphous, doped (N + or P +) or undoped.
De manière particulièrement avantageuse, chaque recuit rapide présente une vitesse de montée en température supérieure à 10°C par seconde, de préférence supérieure ou égale à 50°C par seconde. In a particularly advantageous manner, each rapid annealing has a temperature rise rate greater than 10 ° C. per second, preferably greater than or equal to 50 ° C. per second.
De préférence, le lissage ne comprend aucun traitement thermique présentant une vitesse de montée en température inférieure à 10°C par seconde. Preferably, the smoothing does not include any heat treatment having a temperature rise rate of less than 10 ° C. per second.
Dans certains modes de réalisation, le lissage est mis en oeuvre individuellement pour chaque structure comprenant la couche semi-conductrice et le substrat receveur. In some embodiments, the smoothing is implemented individually for each structure comprising the semiconductor layer and the receiver substrate.
Brève description des dessins Brief description of the drawings
D’autres caractéristiques et avantages de l’invention ressortiront de la description détaillée qui va suivre, en référence aux dessins annexés, sur lesquels : Other characteristics and advantages of the invention will emerge from the detailed description which follows, with reference to the accompanying drawings, in which:
- la figure 1 est une vue schématique en coupe d’un capteur d’image ; - Figure 1 is a schematic sectional view of an image sensor;
- la figure 2 est une vue schématique en coupe d’un substrat receveur et d’un substrat donneur utilisés dans un procédé de fabrication d’un capteur d’image selon un mode de réalisation de l’invention ; - Figure 2 is a schematic sectional view of a recipient substrate and a donor substrate used in a method of manufacturing an image sensor according to one embodiment of the invention;
- la figure 3 est une vue schématique en coupe du substrat receveur et du substrat donneur de la figure 2 après détachement du substrat donneur selon la zone de fragilisation ; - Figure 3 is a schematic sectional view of the recipient substrate and the donor substrate of Figure 2 after detachment of the donor substrate according to the weakening zone;
- la figure 4 est une vue schématique en coupe du capteur d’image formé à partir des substrats donneur et receveur de la figure 3, après finition de la couche semi- conductrice transférée et formation du circuit de lecture des pixels et des interconnexions ; - la figure 5 est un profil SIMS de la concentration en phosphore au sein d’une structure SOI comprenant une couche dopée en phosphore à l’issue d’un recuit rapide tel que mis en oeuvre dans la présente invention et d’un traitement thermique tel que mis en oeuvre lors de la fabrication d’un substrat FDSOI. FIG. 4 is a schematic sectional view of the image sensor formed from the donor and recipient substrates of FIG. 3, after finishing the transferred semiconductor layer and forming the circuit for reading the pixels and the interconnections; FIG. 5 is a SIMS profile of the phosphorus concentration within an SOI structure comprising a layer doped with phosphorus at the end of a rapid annealing as implemented in the present invention and of a heat treatment as implemented during the manufacture of an FDSOI substrate.
Les signes de référence identiques d’une figure à l’autre désignent des éléments identiques ou remplissant une même fonction. Identical reference signs from one figure to another designate elements that are identical or perform the same function.
Pour des raisons de lisibilité des figures, les différents éléments n’ont pas nécessairement été représentés à l’échelle. For reasons of legibility of the figures, the various elements have not necessarily been shown to scale.
Description détaillée de modes de réalisation Detailed description of embodiments
L’invention propose de fabriquer un capteur d’image par transfert d’une couche mince d’un substrat donneur sur un substrat receveur. The invention proposes to manufacture an image sensor by transferring a thin layer from a donor substrate to a recipient substrate.
Le substrat receveur comprend un substrat de base et une couche active comprenant une pluralité de pixels. The receiver substrate includes a base substrate and an active layer comprising a plurality of pixels.
Le substrat de base est généralement un substrat semi-conducteur, par exemple de silicium. Ledit substrat de base a notamment une fonction de support mécanique du capteur d’image. The base substrate is generally a semiconductor substrate, for example of silicon. Said base substrate has in particular a function of mechanical support of the image sensor.
La couche active est une couche semi-conductrice monocristalline, par exemple de silicium ou de silicium-germanium. The active layer is a monocrystalline semiconductor layer, for example of silicon or of silicon-germanium.
Les pixels sont séparés les uns des autres par des tranchées électriquement isolantes. Ces tranchées sont connues sous l’acronyme DTI du terme anglo-saxon « Deep Trench Isolation » ou CDTI du terme anglo-saxon « Capacitor Deep Trench Isolation ». The pixels are separated from each other by electrically insulating trenches. These trenches are known by the acronym DTI from the Anglo-Saxon term "Deep Trench Isolation" or CDTI from the Anglo-Saxon term "Capacitor Deep Trench Isolation".
Chaque pixel comprend une région dopée adaptée pour collecter les charges électriques générées dans chaque pixel. Each pixel comprises a doped region adapted to collect the electrical charges generated in each pixel.
De manière particulièrement avantageuse, le substrat receveur ne comprend aucune interconnexion métallique entre ses composants. In a particularly advantageous manner, the receiving substrate does not include any metallic interconnection between its components.
La fabrication d’un tel substrat receveur est à la portée de l’homme du métier. Le procédé de fabrication du substrat receveur ne sera donc pas décrit en détail dans le présent texte. The manufacture of such a recipient substrate is within the abilities of those skilled in the art. The process for manufacturing the recipient substrate will therefore not be described in detail in the present text.
Le substrat donneur comprend une zone de fragilisation qui délimite une couche mince semi-conductrice monocristalline. Dans certains modes de réalisation, le substrat donneur peut être un substrat massif, constitué d’un seul matériau semi-conducteur monocristallin. De manière alternative, le substrat donneur peut être un substrat composite constitué d’au moins deux couches de matériaux différents, comprenant au moins une couche semi-conductrice monocristalline. La couche mince monocristalline peut être une couche de silicium, ou d’un autre matériau semi-conducteur. La zone de fragilisation est avantageusement formée par implantation d’espèces atomiques, telles que de l’hydrogène et/ou de l’hélium, dans le substrat donneur. La détermination de la dose et de l’énergie d’implantation pour former la zone de fragilisation à une profondeur donnée du substrat donneur est à la portée de l’homme du métier. Pendant l’implantation, la surface du substrat donneur peut éventuellement être protégée par une couche diélectrique, telle qu’une couche d’oxyde de silicium (S1O2). Ladite couche peut ensuite être retirée, par exemple par gravure sélective. The donor substrate comprises an embrittlement zone which delimits a monocrystalline semiconductor thin layer. In some embodiments, the donor substrate can be a solid substrate, made from a single monocrystalline semiconductor material. Alternatively, the donor substrate can be a composite substrate made up of at least two layers of different materials, comprising at least one monocrystalline semiconductor layer. The monocrystalline thin film can be a layer of silicon, or of another semiconductor material. The weakening zone is advantageously formed by implantation of atomic species, such as hydrogen and / or helium, in the donor substrate. The determination of the dose and of the implantation energy to form the weakening zone at a given depth of the donor substrate is within the abilities of those skilled in the art. During implantation, the surface of the donor substrate may optionally be protected by a dielectric layer, such as a layer of silicon oxide (S1O2). Said layer can then be removed, for example by selective etching.
Le substrat donneur est ensuite collé sur le substrat receveur. Dans certains modes de réalisation, le collage peut être réalisé par l’intermédiaire d’une couche diélectrique, telle qu’une couche d’oxyde de silicium. The donor substrate is then bonded to the recipient substrate. In some embodiments, the bonding can be accomplished through a dielectric layer, such as a silicon oxide layer.
Une fracture du substrat donneur est initiée au niveau de la zone de fragilisation, conduisant au détachement du substrat donneur le long de la zone de fragilisation. A l’issue de ce détachement, la couche mince semi-conductrice a été transférée sur le substrat receveur. A fracture of the donor substrate is initiated at the area of weakness, leading to detachment of the donor substrate along the area of weakness. After this detachment, the semiconductor thin film was transferred to the recipient substrate.
Ce procédé est bien connu sous le nom de procédé Smart Cut™. This process is well known as the Smart Cut ™ process.
Le produit final comprenant le substrat receveur et la couche mince semi- conductrice sera qualifié de plaque (ou « wafer » en anglais) dans le présent texte. The final product comprising the receiving substrate and the thin semiconductor layer will be referred to as a wafer in the present text.
La couche mince semi-conductrice transférée présentant une certaine rugosité, un traitement de finition est mis en oeuvre sur la plaque afin de lisser ladite couche tout en assurant l’uniformité d’épaisseur requise. Since the transferred semiconductor thin layer exhibits a certain roughness, a finishing treatment is carried out on the plate in order to smooth said layer while ensuring the required uniformity of thickness.
Pour ne pas provoquer la diffusion des dopants de la couche active, l’ensemble de ce traitement de finition est mis en oeuvre avec un budget thermique modéré, inférieur à celui mis en oeuvre habituelle pour fabriquer des substrats FDSOI. Cependant, dans la mesure où le substrat receveur ne comprend pas de métal, il n’est pas nécessaire de recourir à un traitement à basse température, tel que décrit par exemple dans [Schwarzenbach 2019], qui présente l’inconvénient d’être long et complexe. In order not to cause the diffusion of dopants from the active layer, all of this finishing treatment is carried out with a moderate thermal budget, lower than that used customarily to manufacture FDSOI substrates. However, insofar as the recipient substrate does not include a metal, it is not necessary to resort to a low temperature treatment, as described for example in [Schwarzenbach 2019], which has the drawback of being long. and complex.
L’épaisseur cible pour la couche semi-conductrice transférée est comprise entre 10 nm et 100 nm, avec une variation maximale de ± 5 Â par rapport à la valeur cible, au sein de chaque plaque et entre les différentes plaques fabriquées par le procédé. Ce critère d’uniformité est généralement requis pour la fabrication des substrats FDSOI, mais ne peut pas être obtenu pour le capteur d’image visé avec le traitement habituel de finition des substrats FDSOI qui présente un budget thermique trop élevé. En effet, le traitement de finition des substrats FDSOI comprend typiquement un procédé dit « batch anneal », qui est un procédé de lissage long, à haute température, avantageusement réalisé dans un four permettant de traiter une pluralité de substrats en même temps (d’où le terme de « batch »). Un tel « batch anneal » est typiquement mis en oeuvre à une température comprise entre 1150 et 1200°C, pendant une durée de plusieurs minutes, généralement supérieure à 15 minutes. De plus, la montée en température dans le four est relativement lente, avec une rampe de l’ordre de quelques °C par minute, ce qui contribue à augmenter le budget thermique subi par le substrat. Ce lissage permet d’amener la couche semi-conductrice transférée à un niveau de rugosité de surface compatible avec la fabrication des transistors. Cependant, il a été démontré qu’un tel « batch anneal » avait pour effet de dégrader l’uniformité de l’épaisseur de la couche semi-conductrice transférée au sein d’une même plaque. The target thickness for the transferred semiconductor layer is between 10 nm and 100 nm, with a maximum variation of ± 5 Å from the target value, within each wafer and between the different wafers made by the process. This uniformity criterion is generally required for the manufacture of FDSOI substrates, but cannot be obtained for the targeted image sensor with the usual finishing treatment for FDSOI substrates which has an excessively high thermal budget. Indeed, the finishing treatment of FDSOI substrates typically comprises a so-called “batch anneal” process, which is a long smoothing process, at high temperature, advantageously carried out in an oven making it possible to treat a plurality of substrates at the same time (from where the term "batch"). Such a “batch anneal” is typically carried out at a temperature of between 1150 and 1200 ° C., for a period of several minutes, generally greater than 15 minutes. In addition, the rise in temperature in the oven is relatively slow, with a ramp of the order of a few ° C. per minute, which contributes to increasing the thermal budget suffered by the substrate. This smoothing makes it possible to bring the transferred semiconductor layer to a surface roughness level compatible with the manufacture of transistors. However, it has been demonstrated that such a “batch anneal” had the effect of degrading the uniformity of the thickness of the semiconductor layer transferred within the same wafer.
Concrètement, le traitement de finition mis en oeuvre dans l’invention comprend d’une part un amincissement de la couche transférée par oxydation sacrificielle suivie d’une gravure chimique et d’autre part un lissage au moyen d’un ou de plusieurs recuit(s) rapide(s) qui procurent un budget thermique plus faible que celui d’un « batch anneal », ledit budget thermique étant adapté pour préserver l’intégrité des pixels. Concretely, the finishing treatment implemented in the invention comprises on the one hand a thinning of the layer transferred by sacrificial oxidation followed by a chemical etching and on the other hand a smoothing by means of one or more annealing ( s) fast (s) which provide a lower thermal budget than that of a “batch anneal”, said thermal budget being adapted to preserve the integrity of the pixels.
En ce qui concerne l’amincissement, le traitement comprend tout d’abord une oxydation de la couche transférée de sorte à former une fine couche d’oxyde à la surface de ladite couche. Cet oxyde est de préférence formé par oxydation thermique du matériau de la couche semi-conductrice, lors de laquelle la couche semi-conductrice transférée est soumise à un traitement thermique dans une atmosphère oxydante comprenant de l’oxygène et/ou de la vapeur d’eau, qui a pour effet de consommer une partie superficielle de ladite couche. En ajustant les conditions de cette oxydation thermique (notamment sa durée, son atmosphère (sèche ou humide), sa pression et sa température), on peut ajuster l’épaisseur de la couche transférée consommée, et par conséquent la mesure dans laquelle ladite couche est amincie. Ladite oxydation est mise en oeuvre à une température inférieure à 1000°C et préférentiellement inférieure ou égale à 950°C pour ne pas engendrer de diffusion des dopants au sein de la plaque. La durée de l’oxydation est choisie en fonction de l’épaisseur d’oxyde à former, qui dépend de l’épaisseur initiale de la couche transférée et de l’épaisseur cible de ladite couche. Une telle oxydation peut être mise en oeuvre simultanément sur un ou plusieurs lots de plaques. With regard to thinning, the treatment first comprises oxidation of the transferred layer so as to form a thin oxide layer on the surface of said layer. This oxide is preferably formed by thermal oxidation of the material of the semiconductor layer, during which the transferred semiconductor layer is subjected to a heat treatment in an oxidizing atmosphere comprising oxygen and / or vapor. water, which has the effect of consuming a surface part of said layer. By adjusting the conditions of this thermal oxidation (in particular its duration, its atmosphere (dry or wet), its pressure and its temperature), it is possible to adjust the thickness of the transferred layer consumed, and consequently the extent to which said layer is thinned. Said oxidation is carried out at a temperature below 1000 ° C. and preferably below or equal to 950 ° C so as not to cause diffusion of the dopants within the plate. The duration of the oxidation is chosen according to the thickness of oxide to be formed, which depends on the initial thickness of the transferred layer and on the target thickness of said layer. Such oxidation can be carried out simultaneously on one or more batches of plates.
On effectue ensuite une mesure de l’épaisseur de la couche transférée recouverte de la couche d’oxyde en un certain nombre de points répartis sur la surface de la plaque. Ainsi, une mesure par ellipsométrie ou par réflectométrie fournit l’épaisseur de la couche semi-conductrice. The thickness of the transferred layer covered with the oxide layer is then measured at a number of points distributed over the surface of the plate. Thus, an ellipsometric or reflectometry measurement provides the thickness of the semiconductor layer.
Pour définir le traitement à appliquer à la couche semi-conductrice transférée pour uniformiser son épaisseur, on utilise une cartographie d’épaisseur de ladite couche obtenue par ellipsométrie ou par réflectométrie. A partir des épaisseurs mesurées en différents points de la plaque, on peut également déterminer l’épaisseur moyenne de la couche semi-conductrice. To define the treatment to be applied to the transferred semiconductor layer to standardize its thickness, a thickness map of said layer obtained by ellipsometry or reflectometry is used. From the thicknesses measured at different points on the plate, we can also determine the average thickness of the semiconductor layer.
Cette cartographie d’épaisseur et/ou cette épaisseur moyenne permettent de déterminer une ou des régions de la couche transférée présentant des surépaisseurs par rapport à une épaisseur cible et devant par conséquent faire l’objet d’un amincissement afin d’améliorer l’uniformité de l’épaisseur de la couche semi-conductrice transférée. This thickness map and / or this average thickness make it possible to determine one or more regions of the transferred layer having excess thicknesses. relative to a target thickness and therefore to be subject to thinning in order to improve the uniformity of the thickness of the transferred semiconductor layer.
Selon les cas, on s’intéresse à l’uniformité dite « intra-plaque » (c’est-à-dire sur la surface d’une même structure, ladite structure se présentant généralement sous la forme d’une plaque circulaire) et/ou à l’uniformité dite « de plaque à plaque » (c’est-à- dire entre l’ensemble des structures appartenant à l’ensemble des lots de production). Depending on the case, we are interested in the so-called “intra-plate” uniformity (that is to say on the surface of the same structure, said structure generally in the form of a circular plate) and / or to the so-called “plate to plate” uniformity (that is to say between all the structures belonging to all the production batches).
Dans le cas de l’uniformité intra-plaque, on compare en chaque point l’épaisseur mesurée avec l’épaisseur cible du produit final souhaité, ladite épaisseur cible étant inférieure ou égale à l’épaisseur moyenne. Dans ce cas, la ou les régions à amincir sont donc la ou les régions dans lesquelles l’épaisseur de la couche semi-conductrice est supérieure à l’épaisseur cible, la ou les surépaisseurs correspondant à la différence entre l’épaisseur mesurée et l’épaisseur cible. Il s’agit donc là d’une ou de surépaisseurs « locales » de la plaque. In the case of intra-plate uniformity, the measured thickness is compared at each point with the target thickness of the desired end product, said target thickness being less than or equal to the average thickness. In this case, the region or regions to be thinned are therefore the region or regions in which the thickness of the semiconductor layer is greater than the target thickness, the extra thickness (s) corresponding to the difference between the measured thickness and the thickness. target thickness. This is therefore one or more "local" thicknesses of the plate.
Dans le cas de l’uniformité de plaque à plaque, on compare la moyenne des épaisseurs de la couche semi-conductrice mesurées aux différents points de mesure avec une épaisseur moyenne cible. Dans ce cas, une plaque à amincir est une plaque pour laquelle l’épaisseur moyenne de la couche semi-conductrice est supérieure à l’épaisseur moyenne cible, la surépaisseur correspondant à la différence entre ces deux épaisseurs moyennes. Il s’agit donc là d’une surépaisseur « globale » de la plaque. In the case of plate-to-plate uniformity, the average of the thicknesses of the semiconductor layer measured at the different measurement points is compared with a target average thickness. In this case, a wafer to be thinned is a wafer for which the average thickness of the semiconductor layer is greater than the target average thickness, the extra thickness corresponding to the difference between these two average thicknesses. This is therefore an "overall" extra thickness of the plate.
Naturellement, on peut combiner ces impératifs d’uniformité. Of course, one can combine these imperatives of uniformity.
Pour amincir ces régions de manière localisée au sein d’une plaque et/ou amincir la plaque de manière globale, on met tout d’abord en oeuvre une gravure sélective de la couche d’oxyde sacrificiel. On utilise à cet effet un agent de gravure adapté pour graver l’oxyde sacrificiel sans attaquer le matériau semi-conducteur de la couche. Typiquement, si la couche d’oxyde sacrificiel est en oxyde de silicium et la couche transférée en silicium, on utilise comme agent de gravure une solution d’acide fluorhydrique (HF). Naturellement, l’homme du métier pourra sélectionner tout autre agent de gravure approprié en fonction des matériaux respectifs de la couche d’oxyde sacrificiel et de la couche semi-conductrice. To thin these regions locally within a wafer and / or to thin the wafer overall, a selective etching of the sacrificial oxide layer is first implemented. An etching agent suitable for etching the sacrificial oxide without attacking the semiconductor material of the layer is used for this purpose. Typically, if the sacrificial oxide layer is silicon oxide and the transferred layer is silicon, a solution of hydrofluoric acid (HF) is used as the etchant. Naturally, those skilled in the art will be able to select any other suitable etchant depending on the respective materials of the sacrificial oxide layer and of the semiconductor layer.
Une fois la couche d’oxyde sacrificiel retirée, on met en oeuvre une gravure chimique de la couche semi-conductrice elle-même. Once the sacrificial oxide layer has been removed, a chemical etching of the semiconductor layer itself is performed.
Dans certains modes de réalisation, la gravure est une gravure humide, c’est-à- dire dans laquelle on expose la couche semi-conductrice transférée à une solution de gravure. L’exposition peut être réalisée par immersion de la plaque dans ladite solution, ou bien en projetant la solution de gravure sur la surface de la plaque au moyen d’une buse, ce peut qui permettre de localiser la gravure à des régions devant être amincies par rapport à d’autres régions de la plaque. Cette gravure peut être mise en œuvre à température ambiante, c’est-à-dire de l’ordre de 20 à 25°C, ou à une température plus élevée mais généralement inférieure à 80°C. In some embodiments, the etching is wet etching, that is, in which the transferred semiconductor layer is exposed to an etching solution. The exposure can be carried out by immersing the plate in said solution, or by spraying the etching solution on the surface of the plate by means of a nozzle, which can make it possible to locate the etch at regions to be thinned out. compared to other regions of the plaque. This etching can be carried out at room temperature, that is to say of the order of 20 to 25 ° C, or at a higher temperature but generally less than 80 ° C.
Dans d’autres modes de réalisation, la gravure peut être une gravure sèche par plasma, une gravure sèche par faisceau ionique (« Reactive Ion Etching » selon la terminologie anglo-saxonne), gravure sèche par faisceau d’ions en agrégats (GCIB, acronyme du terme anglo-saxon « Gas Cluster Ion Beam »). Ces étapes n’impliquent pas un budget thermique significatif. In other embodiments, the etching may be dry plasma etching, dry etching by ion beam ("Reactive Ion Etching" according to English terminology), dry etching by ion beam in aggregates (GCIB, acronym of the Anglo-Saxon term “Gas Cluster Ion Beam”). These steps do not involve a significant thermal budget.
Les paramètres de mise en œuvre de ces différents types de gravures permettent d’amincir la couche semi-conductrice transférée de manière globale et/ou localisée. The implementation parameters of these different types of etchings make it possible to thin the semiconductor layer transferred globally and / or localized.
Un tel procédé d’amincissement / uniformisation d’un substrat FDSOI, qui permet de remédier à la dégradation de l’uniformité d’épaisseur de la couche semi-conductrice transférée engendrée par le lissage par « batch anneal », est décrit dans le brevet FR 2 991 099 au nom de la demanderesse. Such a method of thinning / standardizing an FDSOI substrate, which makes it possible to remedy the degradation of the uniformity of thickness of the transferred semiconductor layer generated by the smoothing by “batch anneal”, is described in the patent. FR 2 991 099 in the name of the applicant.
En ce qui concerne le lissage, il est réalisé, dans la présente invention, au moyen d’un ou deux recuit(s) rapide(s) à haute température (RTA, acronyme du terme anglo- saxon Rapid Thermal Annealing). Chaque recuit est typiquement mis en œuvre à une température comprise entre 1100 et 1250°C pendant une durée comprise entre 15 et 60 s, qui permet une réorganisation des atomes à la surface de la couche semi-conductrice transférée et ainsi de la lisser. Par opposition au « batch anneal », chaque recuit rapide est mis en œuvre avec une montée en température rapide, de l’ordre de quelques dizaines de °C par seconde. Par ailleurs, alors qu’un « batch anneal » est mis en œuvre simultanément sur une pluralité de plaques, un recuit rapide est mis en œuvre individuellement sur chaque plaque. As regards the smoothing, it is carried out, in the present invention, by means of one or two rapid annealing (s) at high temperature (RTA, acronym for the English term Rapid Thermal Annealing). Each annealing is typically carried out at a temperature of between 1100 and 1250 ° C for a period of between 15 and 60 s, which allows a reorganization of the atoms on the surface of the transferred semiconductor layer and thus to smooth it. As opposed to "batch anneal", each rapid anneal is carried out with a rapid rise in temperature, of the order of a few tens of ° C per second. Furthermore, while a "batch anneal" is carried out simultaneously on a plurality of plates, rapid annealing is carried out individually on each plate.
Le budget thermique mis en œuvre lors de ce(s) recuit(s) est suffisamment faible pour éviter une diffusion des dopants au sein de la plaque. The thermal budget implemented during this (these) annealing (s) is low enough to avoid diffusion of dopants within the plate.
De préférence, le procédé comprend deux recuits rapides, afin d’obtenir un état de surface optimal de la couche transférée. Preferably, the process comprises two rapid anneals, in order to obtain an optimum surface condition of the transferred layer.
Ainsi, contrairement au procédé connu de fabrication des substrats FDSOI, le lissage mis en œuvre dans la présente invention ne comprend aucun « batch anneal ». De manière plus générale, ledit lissage ne comprend aucun traitement thermique lent, c’est-à-dire présentant une vitesse de montée en température inférieure à 10°C par seconde. L’intégrité des pixels est donc préservée pendant le lissage. Thus, unlike the known process for manufacturing FDSOI substrates, the smoothing implemented in the present invention does not include any “batch anneal”. More generally, said smoothing does not include any slow heat treatment, that is to say having a temperature rise rate of less than 10 ° C per second. The integrity of the pixels is therefore preserved during smoothing.
Selon un mode de réalisation préféré, le procédé comprend deux étapes d’oxydation sacrificielle, mises en œuvre respectivement entre le premier et le second recuit rapide et après le second recuit rapide lorsque deux recuits rapides sont mis en œuvre. La première oxydation sacrificielle permet avantageusement de retirer les défauts liés à l’implantation de fragilisation en oxydant une région superficielle de la couche transférée et en retirant ladite région oxydée, tandis que la seconde oxydation sacrificielle, qui est suivie d’une gravure chimique de la couche transférée, permet d’amincir uniformément la couche transférée à l’épaisseur cible. Les recuits rapides sont de préférence mis en oeuvre avant l’amincissement de la couche transférée, afin de préserver la stabilité de ladite couche. Il serait envisageable de s’affranchir du premier recuit rapide mais au prix d’une dégradation de la rugosité. According to a preferred embodiment, the method comprises two sacrificial oxidation steps, implemented respectively between the first and the second rapid annealing and after the second rapid annealing when two rapid annealing are implemented. The first sacrificial oxidation advantageously makes it possible to remove the defects linked to the implantation of embrittlement by oxidizing a surface region of the layer transferred and removing said oxidized region, while the second sacrificial oxidation, which is followed by chemical etching of the transferred layer, uniformly thin the transferred layer to the target thickness. The rapid anneals are preferably carried out before the thinning of the transferred layer, in order to preserve the stability of said layer. It would be possible to do without the first rapid annealing but at the cost of degradation of the roughness.
Après la finition de la couche semi-conductrice transférée, il est possible de fabriquer dans ou sur cette couche des composants du circuit de lecture des pixels. After finishing the transferred semiconductor layer, it is possible to manufacture in or on this layer components of the pixel read circuit.
Lesdits composants sont par ailleurs connectés électriquement aux pixels par des interconnexions. Lesdites interconnexions peuvent être métalliques mais, dans la mesure où elles sont formées après le traitement de finition de la couche semi- conductrice transférée, elles ne risquent pas d’être endommagées par celui-ci. Said components are moreover electrically connected to the pixels by interconnections. Said interconnections may be metallic but, insofar as they are formed after the finishing treatment of the transferred semiconductor layer, they are not liable to be damaged by it.
Pour la réalisation du capteur d’image, il peut être utile d’intercaler une ou plusieurs couches additionnelles semi-conductrices et/ou électriquement isolantes entre la couche active et la couche semi-conductrice comprenant les composants du circuit de lecture. For the realization of the image sensor, it may be useful to insert one or more additional semiconductor and / or electrically insulating layers between the active layer and the semiconductor layer comprising the components of the read circuit.
L’intégration de ces couches additionnelles dans le capteur d’image peut être réalisée de différentes manières. The integration of these additional layers in the image sensor can be achieved in different ways.
Selon un mode de réalisation, lesdites couches additionnelles peuvent être formées sur la couche active du substrat receveur, avant le collage du substrat donneur. Ces couches peuvent être formées par exemple par dépôt. Quel que soit le procédé de formation choisi, il n’implique pas un budget thermique susceptible de faire diffuser les dopants de la couche active. According to one embodiment, said additional layers can be formed on the active layer of the recipient substrate, before the bonding of the donor substrate. These layers can be formed, for example, by deposition. Whatever training method is chosen, it does not involve a thermal budget likely to diffuse the dopants from the active layer.
Selon un autre mode de réalisation, au moins une desdites couches additionnelles peut être formée par dépôt sur la couche active du substrat receveur et au moins une autre desdites couches additionnelles est formée par dépôt sur la couche semi- conductrice monocristalline du substrat donneur, avant le collage desdits substrats. Comme indiqué précédemment, le dépôt de chaque couche additionnelle sur la couche active du substrat receveur doit être réalisé avec un budget thermique suffisamment faible pour ne pas générer de diffusion des dopants. According to another embodiment, at least one of said additional layers can be formed by deposition on the active layer of the recipient substrate and at least another of said additional layers is formed by deposition on the monocrystalline semiconductor layer of the donor substrate, before coating. bonding of said substrates. As indicated above, the deposition of each additional layer on the active layer of the receiving substrate must be carried out with a sufficiently low thermal budget so as not to generate diffusion of the dopants.
Selon encore un autre mode de réalisation, lesdites couches additionnelles sont formées sur le substrat donneur. De préférence, lesdites couches sont formées par dépôt avant l’implantation des espèces atomiques permettant de former la zone de fragilisation. Ainsi, le budget thermique de ces dépôts ne risque pas de provoquer une fracture prématurée du substrat donneur le long de la zone de fragilisation. Si lesdites couches additionnelles sont déposées après la formation de la zone de fragilisation, le budget thermique appliqué devra être limité afin d’éviter une telle fracture prématurée. La figure 2 est une vue en coupe schématique du substrat donneur et du substrat receveur avant leur collage dans une forme d’exécution de l’invention. According to yet another embodiment, said additional layers are formed on the donor substrate. Preferably, said layers are formed by deposition before implantation of the atomic species making it possible to form the weakening zone. Thus, the thermal budget of these deposits does not risk causing a premature fracture of the donor substrate along the weakening zone. If said additional layers are deposited after the formation of the weakening zone, the thermal budget applied will have to be limited in order to avoid such a premature fracture. FIG. 2 is a schematic sectional view of the donor substrate and of the recipient substrate before their bonding in one embodiment of the invention.
Le substrat receveur 1 comprend successivement : The receiving substrate 1 successively comprises:
- un substrat de base 10, - a base substrate 10,
- une couche active comprenant une pluralité de pixels 11, chaque pixel comprenant une région dopée 12 adaptée pour collecter les charges électriques générées dans chaque pixel ; les pixels sont séparés les uns des autres par des tranchées électriquement isolantes 13, an active layer comprising a plurality of pixels 11, each pixel comprising a doped region 12 adapted to collect the electric charges generated in each pixel; the pixels are separated from each other by electrically insulating trenches 13,
- une première couche additionnelle 15, par exemple semi-conductrice, et - a first additional layer 15, for example semiconductor, and
- une seconde couche additionnelle 16, par exemple électriquement isolante- a second additional layer 16, for example electrically insulating
Le substrat donneur 2 comprend une zone de fragilisation 200 délimitant une couche mince semi-conductrice 201. The donor substrate 2 comprises a weakening zone 200 delimiting a thin semiconductor layer 201.
Comme indiqué plus haut, la couche 16, et éventuellement la couche 15, pourraient être formées sur le substrat donneur 2 au lieu du substrat receveur 1. Dans ce cas, chaque couche concernée est destinée à être transférée sur le substrat receveur avec la couche 201. As indicated above, the layer 16, and possibly the layer 15, could be formed on the donor substrate 2 instead of the recipient substrate 1. In this case, each layer concerned is intended to be transferred onto the recipient substrate with the layer 201. .
En référence à la figure 3, on colle le substrat donneur sur le substrat receveur, puis on détache le substrat donneur le long de la zone de fragilisation, de sorte à transférer la couche semi-conductrice 201 sur le substrat receveur 1. With reference to FIG. 3, the donor substrate is bonded to the recipient substrate, then the donor substrate is detached along the weakening zone, so as to transfer the semiconductor layer 201 onto the recipient substrate 1.
Comme représenté schématiquement, la surface S de la couche 201 à l’issue du détachement est rugueuse. As shown schematically, the surface S of the layer 201 after detachment is rough.
On met donc en oeuvre le traitement de finition décrit plus haut. The finishing treatment described above is therefore implemented.
Une fois que la couche semi-conductrice monocristalline transférée a été amincie de manière uniforme à l’épaisseur cible, on forme dans ou sur ladite couche des composants 25 du circuit de lecture (cf. figure 4). On forme également des interconnexions 26 entre les composants 25 et les pixels 11. Once the transferred monocrystalline semiconductor layer has been uniformly thinned to the target thickness, components of the read circuit are formed in or on said layer (see Figure 4). Interconnections 26 are also formed between the components 25 and the pixels 11.
La figure 5 est un profil SI MS (acronyme du terme anglo-saxon « Secondary ion mass spectrometry », c’est-à-dire spectrométrie de masse aux ions secondaires) de la concentration en phosphore au sein d’une structure SOI comprenant successivement à partir de sa surface une couche de silicium monocristallin non dopé de 42 nm d’épaisseur, une couche d’oxyde de silicium de 190 nm d’épaisseur, une couche de silicium dopée en phosphore s’étendant jusqu’à une profondeur de 3500 nm, et un substrat de base en silicium non intentionnellement dopé, à l’issue de deux recuits rapides à 1200°C pendant 30 secondes, tels que mis en oeuvre dans la présente invention (courbe a) et d’un traitement thermique (« batch anneal ») à 1200°C pendant 5 minutes, tel que mis en oeuvre lors de la fabrication d’un substrat FDSOI (courbe b). L’axe des abscisses indique la profondeur (en nm) à partir de la surface de la structure SOI, l’axe des ordonnées indique la concentration en phosphore (en at/cm2). La transition nette (pente sensiblement verticale) entre la couche dopée et le substrat de base visible sur la courbe a montre qu’il n’y a sensiblement pas eu de diffusion des dopants lors des recuits rapides. En revanche, la transition plus progressive visible sur la courbe b traduit un phénomène de diffusion des dopants de la couche dopée vers le substrat de base. FIG. 5 is an SI MS profile (acronym of the English term “Secondary ion mass spectrometry”, that is to say secondary ion mass spectrometry) of the phosphorus concentration within an SOI structure comprising successively from its surface a layer of undoped monocrystalline silicon 42 nm thick, a silicon oxide layer 190 nm thick, a layer of phosphorus doped silicon extending to a depth of 3500 nm, and an unintentionally doped silicon base substrate, after two rapid anneals at 1200 ° C for 30 seconds, as implemented in the present invention (curve a) and a heat treatment (" batch anneal ”) at 1200 ° C for 5 minutes, as used during the manufacture of an FDSOI substrate (curve b). The x-axis indicates the depth (in nm) from the surface of the SOI structure, the y-axis indicates the phosphorus concentration (in at / cm 2 ). The clear transition (substantially vertical slope) between the doped layer and the base substrate visible on curve a shows that there was substantially no diffusion of the dopants during the rapid annealing. On the other hand, the more gradual transition visible on curve b reflects a phenomenon of diffusion of dopants from the doped layer towards the base substrate.
Ces courbes montrent donc l’effet protecteur du(des) recuit(s) rapide(s) par rapport au traitement thermique classique vis-à-vis des régions dopées. These curves therefore show the protective effect of the rapid annealing (s) compared to the conventional heat treatment vis-à-vis the doped regions.
Références [Mansoorian 2009] : Mansoorian, B., and D. Shaver, with Suntharalingam, V. et al.,References [Mansoorian 2009]: Mansoorian, B., and D. Shaver, with Suntharalingam, V. et al.,
Lin Ping Ang. “A 4-side Tileable Back llluminated 3D-integrated Mpixel CMOS Image Sensor.” Solid-State Circuits Conférence - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International. 2009. 38-39, 39a. Lin Ping Ang. “A 4-side Tileable Back llluminated 3D-integrated Mpixel CMOS Image Sensor.” Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International. 2009. 38-39, 39a.
[Schwarzenbach 2019] : W. Schwarzenbach et al, “Low Température SmartCut™ enables High Density 3D SoC Applications”, Proc. ICICDT Conf., 17-19 June 2019[Schwarzenbach 2019]: W. Schwarzenbach et al, “Low Temperature SmartCut ™ enables High Density 3D SoC Applications”, Proc. ICICDT Conf., 17-19 June 2019
FR 2 991 099 FR 2 991 099

Claims

Revendications Claims
1. Procédé de fabrication d’un capteur d’image, comprenant : 1. A method of manufacturing an image sensor, comprising:
- la fourniture d’un substrat receveur (1) comprenant un substrat de base (10) et une couche active comprenant des pixels (11), chaque pixel comprenant une région dopée (12) de collecte des charges électriques générées dans le pixel, ledit substrat receveur (1) étant dépourvu d’interconnexions métalliques, - the provision of a receiver substrate (1) comprising a base substrate (10) and an active layer comprising pixels (11), each pixel comprising a doped region (12) for collecting the electrical charges generated in the pixel, said receiving substrate (1) being devoid of metallic interconnections,
- la fourniture d’un substrat donneur (2) comprenant une zone de fragilisation (200) délimitant une couche semi-conductrice monocristalline (201), - the supply of a donor substrate (2) comprising a weakening zone (200) delimiting a monocrystalline semiconductor layer (201),
- le collage du substrat donneur (2) sur le substrat receveur (1 ), - the bonding of the donor substrate (2) on the recipient substrate (1),
- le détachement du substrat donneur (2) le long de la zone de fragilisation (200), de sorte à transférer la couche semi-conductrice (201) sur le substrat receveur (1),- the detachment of the donor substrate (2) along the weakening zone (200), so as to transfer the semiconductor layer (201) onto the recipient substrate (1),
- la mise en oeuvre d’un traitement de finition de la couche semi-conductrice (201) transférée, ledit traitement de finition comprenant (i) un amincissement de la couche transférée par oxydation sacrificielle suivie d’une gravure chimique et (ii) un lissage de la couche semi-conductrice transférée au moyen d’au moins un recuit rapide. - the implementation of a finishing treatment of the transferred semiconductor layer (201), said finishing treatment comprising (i) thinning of the transferred layer by sacrificial oxidation followed by chemical etching and (ii) a smoothing of the transferred semiconductor layer by means of at least one rapid annealing.
2. Procédé selon la revendication 1, dans lequel chaque recuit rapide est contrôlé pour éviter une diffusion des dopants des régions dopées (12) des pixels (11 ). 2. Method according to claim 1, wherein each rapid annealing is controlled to avoid diffusion of dopants from the doped regions (12) of the pixels (11).
3. Procédé selon l’une des revendications 1 ou 2, dans lequel chaque recuit rapide est mis en oeuvre à une température comprise entre 1100 et 1250°C pendant une durée comprise entre 15 et 60 s. 3. Method according to one of claims 1 or 2, wherein each rapid annealing is carried out at a temperature between 1100 and 1250 ° C for a period of between 15 and 60 s.
4. Procédé selon l’une des revendications 1 à 3, dans lequel l’oxydation sacrificielle et la gravure chimique sont contrôlées pour amincir la couche semi- conductrice monocristalline transférée (201) jusqu’à une épaisseur comprise entre 10 et 100 nm. 4. Method according to one of claims 1 to 3, wherein the sacrificial oxidation and chemical etching are controlled to thin the transferred single crystal semiconductor layer (201) to a thickness between 10 and 100 nm.
5. Procédé selon l’une des revendications 1 à 4, dans lequel la gravure chimique d’amincissement de la couche semi-conductrice monocristalline transférée (201) est mise en oeuvre au moyen d’une gravure humide, d’une gravure sèche par plasma, d’une gravure sèche par faisceau ionique, ou d’une gravure sèche par faisceau d’ions en agrégats. 5. Method according to one of claims 1 to 4, wherein the chemical etching of thinning of the transferred monocrystalline semiconductor layer (201) is implemented by means of wet etching, dry etching by plasma, dry etching by ion beam, or dry etching by ion beam in aggregates.
6. Procédé selon l’une des revendications 1 à 5, comprenant en outre, après la finition de la couche semi-conductrice monocristalline transférée (201), la formation de composants (25) d’un circuit de lecture des pixels dans ou sur ladite couche semi- conductrice transférée (201). 6. Method according to one of claims 1 to 5, further comprising, after finishing the transferred monocrystalline semiconductor layer (201), the formation of components (25) of a circuit for reading pixels in or on said transferred semiconductor layer (201).
7. Procédé selon la revendication 6, comprenant en outre, après la finition de la couche semi-conductrice monocristalline transférée (201), la formation d’interconnexions (26) entre les pixels (11 ) et lesdits composants (25) du circuit de lecture des pixels. 7. The method of claim 6, further comprising, after finishing the transferred single crystal semiconductor layer (201), forming interconnections (26) between the pixels (11) and said components (25) of the circuit. pixel reading.
8. Procédé selon l’une des revendications 1 à 7, comprenant la formation de la zone de fragilisation (200) par implantation d’espèces atomiques dans le substrat donneur (2). 8. Method according to one of claims 1 to 7, comprising forming the weakening zone (200) by implanting atomic species in the donor substrate (2).
9. Procédé selon la revendication 8, dans lequel le traitement de finition comprend successivement : 9. The method of claim 8, wherein the finishing treatment successively comprises:
(i) un premier recuit rapide, (i) a first rapid annealing,
(ii) un retrait de défauts liés à l’implantation par oxydation sacrificielle de la couche transférée, (ii) removal of defects associated with implantation by sacrificial oxidation of the transferred layer,
(iii) un second recuit rapide, et (iii) a second rapid annealing, and
(iv) l’amincissement de la couche transférée. (iv) thinning of the transferred layer.
10. Procédé selon l’une des revendications 1 à 9, dans lequel le substrat donneur (2) comprend en outre au moins une couche (23) électriquement isolante sur la couche semi-conductrice monocristalline (201). 10. Method according to one of claims 1 to 9, wherein the donor substrate (2) further comprises at least one electrically insulating layer (23) on the monocrystalline semiconductor layer (201).
11. Procédé selon l’une des revendications 1 à 10, dans lequel le substrat donneur (2) comprend en outre au moins une couche (24) semi-conductrice sur la couche semi-conductrice monocristalline (201). 11. Method according to one of claims 1 to 10, wherein the donor substrate (2) further comprises at least one semiconductor layer (24) on the monocrystalline semiconductor layer (201).
12. Procédé selon l’une des revendications 10 à 11 en combinaison avec la revendication 8, dans lequel la couche (23) électriquement isolante, respectivement la couche (24) semi-conductrice, est déposée sur le substrat donneur avant l’implantation. 12. Method according to one of claims 10 to 11 in combination with claim 8, wherein the electrically insulating layer (23), respectively the semiconductor layer (24), is deposited on the donor substrate before implantation.
13. Procédé selon l’une des revendications 1 à 9, dans lequel le substrat receveur (1) comprend en outre une couche (15) semi-conductrice sur la couche active. 13. Method according to one of claims 1 to 9, wherein the receiver substrate (1) further comprises a semiconductor layer (15) on the active layer.
14. Procédé selon l’une des revendications 1 à 9 et 13, dans lequel le substrat receveur (1) comprend en outre une couche (16) électriquement isolante sur la couche active. 14. Method according to one of claims 1 to 9 and 13, wherein the receiving substrate (1) further comprises an electrically insulating layer (16) on the active layer.
15. Procédé selon l’une des revendications 1 à 14, dans lequel chaque recuit rapide présente une vitesse de montée en température supérieure à 10°C par seconde, de préférence supérieure ou égale à 50°C par seconde. 15. Method according to one of claims 1 to 14, wherein each rapid annealing has a temperature rise rate greater than 10 ° C per second, preferably greater than or equal to 50 ° C per second.
16. Procédé selon l’une des revendications 1 à 15, dans laquelle le lissage ne comprend aucun traitement thermique présentant une vitesse de montée en température inférieure à 10°C par seconde. 16. Method according to one of claims 1 to 15, wherein the smoothing does not include any heat treatment having a temperature rise rate of less than 10 ° C per second.
17. Procédé selon l’une des revendications 1 à 16, dans lequel le lissage est mis en oeuvre individuellement pour chaque structure comprenant la couche semi- conductrice (201) et le substrat receveur (1). 17. Method according to one of claims 1 to 16, wherein the smoothing is implemented individually for each structure comprising the semiconductor layer (201) and the receiving substrate (1).
EP21719689.8A 2020-01-15 2021-01-14 Method for manufacturing an image sensor Pending EP4091197A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR2000345A FR3106236B1 (en) 2020-01-15 2020-01-15 Manufacturing process of an image sensor
PCT/FR2021/050059 WO2021144534A1 (en) 2020-01-15 2021-01-14 Method for manufacturing an image sensor

Publications (1)

Publication Number Publication Date
EP4091197A1 true EP4091197A1 (en) 2022-11-23

Family

ID=70804696

Family Applications (1)

Application Number Title Priority Date Filing Date
EP21719689.8A Pending EP4091197A1 (en) 2020-01-15 2021-01-14 Method for manufacturing an image sensor

Country Status (8)

Country Link
US (1) US20230039295A1 (en)
EP (1) EP4091197A1 (en)
JP (1) JP2023510285A (en)
KR (1) KR20220127279A (en)
CN (1) CN115039226A (en)
FR (1) FR3106236B1 (en)
TW (1) TW202135146A (en)
WO (1) WO2021144534A1 (en)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040060899A1 (en) * 2002-10-01 2004-04-01 Applied Materials, Inc. Apparatuses and methods for treating a silicon film
FR2978603B1 (en) * 2011-07-28 2013-08-23 Soitec Silicon On Insulator METHOD FOR TRANSFERRING A MONOCRYSTALLINE SEMICONDUCTOR LAYER TO A SUPPORT SUBSTRATE
FR2991099B1 (en) 2012-05-25 2014-05-23 Soitec Silicon On Insulator PROCESS FOR PROCESSING A SEMICONDUCTOR STRUCTURE ON AN INSULATION FOR THE UNIFORMIZATION OF THE THICKNESS OF THE SEMICONDUCTOR LAYER
US9570431B1 (en) * 2015-07-28 2017-02-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor wafer for integrated packages

Also Published As

Publication number Publication date
CN115039226A (en) 2022-09-09
FR3106236B1 (en) 2021-12-10
KR20220127279A (en) 2022-09-19
FR3106236A1 (en) 2021-07-16
US20230039295A1 (en) 2023-02-09
TW202135146A (en) 2021-09-16
JP2023510285A (en) 2023-03-13
WO2021144534A1 (en) 2021-07-22

Similar Documents

Publication Publication Date Title
EP1923912B1 (en) Method of manufacturing a mixed microtechnology structure
EP1344249A1 (en) Method for making a stacked structure comprising a thin film adhering to a target substrate
FR2888400A1 (en) Film producing method for e.g. optic application, involves selectively implanting atomic species via face of wafer for forming implanted zone at predefined depth, and forming protective layer in horizontal walls of step
EP2840589B1 (en) Improved separation method between an active area of a substrate and the rear surface thereof or a portion of the rear surface thereof
FR2907966A1 (en) Substrate e.g. silicon on insulator substrate, manufacturing method, involves forming superficial amorphous layer in part of thin layer by implantation of atomic species in thin layer, and recrystallizing amorphous layer
FR3094573A1 (en) PROCESS FOR PREPARING A THIN LAYER OF FERROELECTRIC MATERIAL
WO2020053306A1 (en) Method for producing an advanced substrate for hybrid integration
EP1631982B1 (en) Method for production of a very thin layer with thinning by means of induced self-support
FR3080486A1 (en) METHOD FOR FORMING A MICROELECTRONIC DEVICE
EP4030467B1 (en) Method for direct hydrophilic bonding of substrates
EP4091197A1 (en) Method for manufacturing an image sensor
EP4000090B1 (en) Process for hydrophilically bonding substrates
EP4006955A1 (en) Low-temperature method for manufacturing a semiconductor substrate on an insulator
FR3120737A1 (en) METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE BASED ON SILICON CARBIDE AND INTERMEDIATE COMPOSITE STRUCTURE
FR2933235A1 (en) GOOD-WAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME
EP3903341B1 (en) Method for manufacturing a substrate for a front-facing image sensor
WO2023186595A1 (en) Method for transferring a thin film onto a support substrate
FR3120736A1 (en) METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE BASED ON SILICON CARBIDE AND INTERMEDIATE COMPOSITE STRUCTURE
FR3108439A1 (en) MANUFACTURING PROCESS OF A STACKED STRUCTURE
WO2023144495A1 (en) Process for fabricating a double semiconductor-on-insulator structure
EP4256606A2 (en) Donor substrate for the transfer of a thin layer and associated transfer method
FR3110282A1 (en) Manufacturing process of a semiconductor-on-insulator substrate for radiofrequency applications
EP2107602A1 (en) Process of making a microelectronic structure of the type semiconductor on insulator with differentiated patterns
FR3079659A1 (en) METHOD FOR MANUFACTURING DONOR SUBSTRATE FOR CARRYING OUT A THREE-DIMENSIONAL INTEGRATED STRUCTURE, AND METHOD FOR MANUFACTURING SUCH AN INTEGRATED STRUCTURE

Legal Events

Date Code Title Description
STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: UNKNOWN

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADE

PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE

17P Request for examination filed

Effective date: 20220722

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

DAV Request for validation of the european patent (deleted)
DAX Request for extension of the european patent (deleted)