EP3913662A4 - Verpackungssubstrat und verfahren zur herstellung davon - Google Patents
Verpackungssubstrat und verfahren zur herstellung davon Download PDFInfo
- Publication number
- EP3913662A4 EP3913662A4 EP20768931.6A EP20768931A EP3913662A4 EP 3913662 A4 EP3913662 A4 EP 3913662A4 EP 20768931 A EP20768931 A EP 20768931A EP 3913662 A4 EP3913662 A4 EP 3913662A4
- Authority
- EP
- European Patent Office
- Prior art keywords
- packaging substrate
- manufacturing same
- packaging
- manufacturing
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
- 238000004806 packaging method and process Methods 0.000 title 1
- 239000000758 substrate Substances 0.000 title 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/15—Ceramic or glass substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201962816984P | 2019-03-12 | 2019-03-12 | |
US201962816972P | 2019-03-12 | 2019-03-12 | |
US201962825945P | 2019-03-29 | 2019-03-29 | |
US201962825966P | 2019-03-29 | 2019-03-29 | |
PCT/KR2020/003483 WO2020185023A1 (ko) | 2019-03-12 | 2020-03-12 | 패키징 기판 및 이의 제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
EP3913662A1 EP3913662A1 (de) | 2021-11-24 |
EP3913662A4 true EP3913662A4 (de) | 2022-11-02 |
Family
ID=72427145
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP20768931.6A Pending EP3913662A4 (de) | 2019-03-12 | 2020-03-12 | Verpackungssubstrat und verfahren zur herstellung davon |
Country Status (6)
Country | Link |
---|---|
US (1) | US20220059421A1 (de) |
EP (1) | EP3913662A4 (de) |
JP (2) | JP2022523898A (de) |
KR (2) | KR102622608B1 (de) |
CN (1) | CN113261093B (de) |
WO (1) | WO2020185023A1 (de) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114340225B (zh) * | 2021-12-23 | 2024-02-23 | 江苏普诺威电子股份有限公司 | 适用于镭射盲孔的多层封装基板对准方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020180015A1 (en) * | 2001-05-31 | 2002-12-05 | Yoshihide Yamaguchi | Semiconductor module |
WO2009005462A1 (en) * | 2007-07-05 | 2009-01-08 | ÅAC Microtec AB | Low resistance through-wafer via |
WO2018101468A1 (ja) * | 2016-12-02 | 2018-06-07 | 凸版印刷株式会社 | 電子部品及び電子部品製造方法 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004311919A (ja) * | 2003-02-21 | 2004-11-04 | Shinko Electric Ind Co Ltd | スルーホールフィル方法 |
JP5654471B2 (ja) * | 2008-10-15 | 2015-01-14 | オー・アー・セー・マイクロテック・アクチボラゲット | ビア配線を作るための方法 |
KR101058685B1 (ko) * | 2009-02-26 | 2011-08-22 | 삼성전기주식회사 | 패키지 기판 및 이의 제조 방법 |
US8584354B2 (en) * | 2010-08-26 | 2013-11-19 | Corning Incorporated | Method for making glass interposer panels |
US9117730B2 (en) * | 2011-12-29 | 2015-08-25 | Ibiden Co., Ltd. | Printed wiring board and method for manufacturing printed wiring board |
JP2014139963A (ja) * | 2013-01-21 | 2014-07-31 | Ngk Spark Plug Co Ltd | ガラス基板の製造方法 |
KR101468680B1 (ko) | 2013-05-09 | 2014-12-04 | (주)옵토레인 | 인터포저 기판의 관통전극 형성 방법 및 인터포저 기판을 포함하는 반도체 패키지 |
JP2015070189A (ja) * | 2013-09-30 | 2015-04-13 | 凸版印刷株式会社 | インターポーザーおよびその製造方法、並びにインターポーザーを備える半導体装置およびその製造方法 |
JP6201663B2 (ja) * | 2013-11-13 | 2017-09-27 | 大日本印刷株式会社 | 貫通電極基板の製造方法、貫通電極基板、および半導体装置 |
WO2015116749A1 (en) | 2014-01-31 | 2015-08-06 | Corning Incorporated | Methods and apparatus for providing an interposer for interconnecting semiconductor chips |
WO2015183915A1 (en) * | 2014-05-27 | 2015-12-03 | The University Of Florida Research Foundation, Inc. | Glass interposer integrated high quality electronic components and systems |
US20160111380A1 (en) * | 2014-10-21 | 2016-04-21 | Georgia Tech Research Corporation | New structure of microelectronic packages with edge protection by coating |
JP2016111221A (ja) * | 2014-12-08 | 2016-06-20 | 日本特殊陶業株式会社 | 配線基板の製造方法及び配線基板 |
KR102450599B1 (ko) * | 2016-01-12 | 2022-10-07 | 삼성전기주식회사 | 패키지기판 |
JP6747063B2 (ja) * | 2016-06-01 | 2020-08-26 | 凸版印刷株式会社 | ガラス回路基板 |
JP6871095B2 (ja) | 2017-07-14 | 2021-05-12 | 株式会社ディスコ | ガラスインターポーザの製造方法 |
-
2020
- 2020-03-12 EP EP20768931.6A patent/EP3913662A4/de active Pending
- 2020-03-12 US US17/434,906 patent/US20220059421A1/en active Pending
- 2020-03-12 KR KR1020237016450A patent/KR102622608B1/ko active IP Right Grant
- 2020-03-12 WO PCT/KR2020/003483 patent/WO2020185023A1/ko unknown
- 2020-03-12 KR KR1020217015660A patent/KR102537004B1/ko active IP Right Grant
- 2020-03-12 CN CN202080007185.2A patent/CN113261093B/zh active Active
- 2020-03-12 JP JP2021534595A patent/JP2022523898A/ja active Pending
-
2023
- 2023-05-10 JP JP2023078227A patent/JP2023103353A/ja active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020180015A1 (en) * | 2001-05-31 | 2002-12-05 | Yoshihide Yamaguchi | Semiconductor module |
WO2009005462A1 (en) * | 2007-07-05 | 2009-01-08 | ÅAC Microtec AB | Low resistance through-wafer via |
WO2018101468A1 (ja) * | 2016-12-02 | 2018-06-07 | 凸版印刷株式会社 | 電子部品及び電子部品製造方法 |
US20190269013A1 (en) * | 2016-12-02 | 2019-08-29 | Toppan Printing Co., Ltd. | Electronic component and method of producing electronic component |
Non-Patent Citations (1)
Title |
---|
See also references of WO2020185023A1 * |
Also Published As
Publication number | Publication date |
---|---|
JP2022523898A (ja) | 2022-04-27 |
CN113261093A (zh) | 2021-08-13 |
CN113261093B (zh) | 2024-04-16 |
WO2020185023A1 (ko) | 2020-09-17 |
EP3913662A1 (de) | 2021-11-24 |
KR20210071075A (ko) | 2021-06-15 |
KR20230074611A (ko) | 2023-05-30 |
KR102537004B1 (ko) | 2023-05-26 |
KR102622608B1 (ko) | 2024-01-08 |
US20220059421A1 (en) | 2022-02-24 |
JP2023103353A (ja) | 2023-07-26 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADE |
|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE |
|
17P | Request for examination filed |
Effective date: 20210819 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR |
|
RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: ABSOLICS INC. |
|
DAV | Request for validation of the european patent (deleted) | ||
DAX | Request for extension of the european patent (deleted) | ||
A4 | Supplementary search report drawn up and despatched |
Effective date: 20221005 |
|
RIC1 | Information provided on ipc code assigned before grant |
Ipc: H01L 23/538 20060101ALI20220928BHEP Ipc: H01L 23/50 20060101ALI20220928BHEP Ipc: H01L 23/525 20060101ALI20220928BHEP Ipc: H01L 23/528 20060101ALI20220928BHEP Ipc: H01L 23/485 20060101ALI20220928BHEP Ipc: H01L 23/498 20060101ALI20220928BHEP Ipc: H01L 23/48 20060101ALI20220928BHEP Ipc: H01L 23/15 20060101AFI20220928BHEP |