EP3841610A4 - Processor module with integrated packaged power converter - Google Patents
Processor module with integrated packaged power converter Download PDFInfo
- Publication number
- EP3841610A4 EP3841610A4 EP18932165.6A EP18932165A EP3841610A4 EP 3841610 A4 EP3841610 A4 EP 3841610A4 EP 18932165 A EP18932165 A EP 18932165A EP 3841610 A4 EP3841610 A4 EP 3841610A4
- Authority
- EP
- European Patent Office
- Prior art keywords
- power converter
- processor module
- packaged power
- integrated packaged
- integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0254—High voltage adaptations; Electrical insulation details; Overvoltage or electrostatic discharge protection ; Arrangements for regulating voltages or for using plural voltages
- H05K1/0262—Arrangements for regulating voltages or for using plural voltages
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10431—Details of mounted components
- H05K2201/10507—Involving several components
- H05K2201/10545—Related components mounted on both sides of the PCB
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US2018/048290 WO2020046276A1 (en) | 2018-08-28 | 2018-08-28 | Processor module with integrated packaged power converter |
Publications (2)
Publication Number | Publication Date |
---|---|
EP3841610A1 EP3841610A1 (en) | 2021-06-30 |
EP3841610A4 true EP3841610A4 (en) | 2022-04-06 |
Family
ID=69643088
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP18932165.6A Pending EP3841610A4 (en) | 2018-08-28 | 2018-08-28 | Processor module with integrated packaged power converter |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP3841610A4 (en) |
TW (1) | TWI720367B (en) |
WO (1) | WO2020046276A1 (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080116589A1 (en) * | 2006-11-17 | 2008-05-22 | Zong-Fu Li | Ball grid array package assembly with integrated voltage regulator |
US20170236809A1 (en) * | 2016-02-16 | 2017-08-17 | Xilinx, Inc. | Chip package assembly with power management integrated circuit and integrated circuit die |
US20180190635A1 (en) * | 2016-12-30 | 2018-07-05 | Samsung Electronics Co., Ltd. | Electronic device package |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080164605A1 (en) * | 2007-01-08 | 2008-07-10 | United Microelectronics Corp. | Multi-chip package |
US8168490B2 (en) * | 2008-12-23 | 2012-05-01 | Intersil Americas, Inc. | Co-packaging approach for power converters based on planar devices, structure and method |
US9177944B2 (en) * | 2010-12-03 | 2015-11-03 | Xilinx, Inc. | Semiconductor device with stacked power converter |
US9331587B2 (en) * | 2013-01-22 | 2016-05-03 | Power Integrations, Inc. | Power converter controller with multiple power sources |
EP2775523A1 (en) * | 2013-03-04 | 2014-09-10 | Dialog Semiconductor GmbH | Chip on chip attach (passive IPD and PMIC) flip chip BGA using new cavity BGA substrate |
JP5756500B2 (en) * | 2013-08-07 | 2015-07-29 | 太陽誘電株式会社 | Circuit module |
US20150255411A1 (en) * | 2014-03-05 | 2015-09-10 | Omkar G. Karhade | Die-to-die bonding and associated package configurations |
KR102287396B1 (en) * | 2014-10-21 | 2021-08-06 | 삼성전자주식회사 | SYSTEM ON PACKAGE (SoP) MODULE AND MOBILE COMPUTING DEVICE HAVING THE SoP |
-
2018
- 2018-08-28 EP EP18932165.6A patent/EP3841610A4/en active Pending
- 2018-08-28 WO PCT/US2018/048290 patent/WO2020046276A1/en unknown
- 2018-11-20 TW TW107141297A patent/TWI720367B/en active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080116589A1 (en) * | 2006-11-17 | 2008-05-22 | Zong-Fu Li | Ball grid array package assembly with integrated voltage regulator |
US20170236809A1 (en) * | 2016-02-16 | 2017-08-17 | Xilinx, Inc. | Chip package assembly with power management integrated circuit and integrated circuit die |
US20180190635A1 (en) * | 2016-12-30 | 2018-07-05 | Samsung Electronics Co., Ltd. | Electronic device package |
Non-Patent Citations (1)
Title |
---|
See also references of WO2020046276A1 * |
Also Published As
Publication number | Publication date |
---|---|
WO2020046276A1 (en) | 2020-03-05 |
TWI720367B (en) | 2021-03-01 |
EP3841610A1 (en) | 2021-06-30 |
TW202010091A (en) | 2020-03-01 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADE |
|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE |
|
17P | Request for examination filed |
Effective date: 20210324 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR |
|
DAV | Request for validation of the european patent (deleted) | ||
DAX | Request for extension of the european patent (deleted) | ||
A4 | Supplementary search report drawn up and despatched |
Effective date: 20220309 |
|
RIC1 | Information provided on ipc code assigned before grant |
Ipc: H01L 23/538 20060101ALI20220302BHEP Ipc: H05K 1/18 20060101ALI20220302BHEP Ipc: H05K 1/02 20060101ALI20220302BHEP Ipc: H01L 23/528 20060101ALI20220302BHEP Ipc: H05K 1/14 20060101ALI20220302BHEP Ipc: H01L 23/498 20060101AFI20220302BHEP |
|
RAP3 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: FERRIC INC. |