EP3241245A1 - Optoelectronic device with light-emitting diodes - Google Patents

Optoelectronic device with light-emitting diodes

Info

Publication number
EP3241245A1
EP3241245A1 EP15823720.6A EP15823720A EP3241245A1 EP 3241245 A1 EP3241245 A1 EP 3241245A1 EP 15823720 A EP15823720 A EP 15823720A EP 3241245 A1 EP3241245 A1 EP 3241245A1
Authority
EP
European Patent Office
Prior art keywords
optoelectronic device
face
light
substrate
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP15823720.6A
Other languages
German (de)
French (fr)
Inventor
Xavier Hugon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Aledia
Original Assignee
Aledia
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Aledia filed Critical Aledia
Publication of EP3241245A1 publication Critical patent/EP3241245A1/en
Pending legal-status Critical Current

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Classifications

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    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/1336—Illuminating devices
    • G02F1/133602—Direct backlight
    • G02F1/133603—Direct backlight with LEDs
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Definitions

  • the present application relates to an opto ⁇ electronic device emitting diodes, in particular LEDs in inorganic materials, for example a display screen or an image projection device.
  • optoelectronic devices in particular display screens or projection devices, comprising light-emitting diodes based on semiconductor materials, comprising a stack of semiconductor layers predominantly comprising at least one group III element and a group V element.
  • III-V compound in particular gallium nitride (GaN), gallium indium nitride (GalnN) and gallium aluminum nitride (GaAIN).
  • a pixel of an image corresponds to the unitary element of the image displayed by a display screen or projected by a projection device.
  • the optoelectronic device is a monochrome image display screen or a monochrome image projection device, it generally comprises only one light source for displaying each pixel of the image.
  • the optoelectronic device is a color image display screen or a color image projection device, it generally comprises for the display of each image pixel at least three emission and / or regulation components luminous intensity, also called sub-display pixels, which each emit light radiation substantially in a single color (for example, red, green and blue). The superposition of the radiation emitted by these three sub-display pixels provides the observer with the color sensation corresponding to the pixel of the displayed image.
  • the display pixel of the display screen or the projection device the assembly formed by the three display sub-pixels used for the display of an image pixel.
  • FIG. 1 represents an example of an optoelectronic device 10 with inorganic light-emitting diodes, such as a display screen or a projection device.
  • the optoelectronic device 10 successively comprises from bottom to top in FIG. 1:
  • lower electrodes 14 corresponding for example to parallel conductive strips
  • inorganic light-emitting diodes 16 resting on the lower electrodes 14 and separated from each other by insulating portions 18;
  • a transparent protective layer 22 covering the entire structure.
  • Phosphor layers and / or color filters may be provided on the protective layer 22.
  • Each inorganic light-emitting diode 16 comprises a stack of semiconductor portions comprising successively from bottom to top in FIG. a semiconductor portion 24 doped with a first type of conductivity, for example N type, in contact with one of the electrodes 14;
  • an active zone 26 that is to say the zone of the light-emitting diode emitting the majority of the light radiation provided by the light-emitting diode in operation, corresponding to a monolayer or multilayer structure comprising, for example, an undoped semiconductor portion, a single quantum well or multiple quantum wells; and a doped semiconductor portion 28 of a second conductivity type, opposite the first type of conductivity, for example of the P type, in contact with one of the electrodes 20.
  • Each display subpixel P of the optoelectronic device 10 comprises a light-emitting diode 16, an insulating portion 18 surrounding the light-emitting diode 16 and portions of one of the electrodes 14 and one of the electrodes 20 in contact with the diode
  • the area occupied by each display subpixel P may correspond to a square whose side is between 100 p and 1 mm.
  • FIGS. 2A to 2C show the structures obtained at successive stages of an exemplary method of manufacturing the optoelectronic device 10.
  • FIG. 2A shows the structure obtained after having formed the lower electrodes 14 on the support 12 and after having deposited on the whole of the structure a stack 30 of successive semiconductor layers 32, 34, 36.
  • FIG. 2B shows the structure obtained after etching apertures 38 in stack 30 to delimit the semiconductor portions 24, 26, 28 for each light-emitting diode 16.
  • FIG. 2C represents the structure obtained after having formed the insulating portions 18 in the openings 38 between the 16. This can be achieved by depositing an insulating layer on the entire structure shown in FIG. 2B, this insulating layer covering the light-emitting diodes 16 and filling the openings 38 and etching the insulating layer until reaching the portions 28. electroluminescent diodes 16.
  • the maximum light intensity that can be emitted by each display subpixel P depends on the area occupied by the light-emitting diode 16 relative to the surface of the display subpixel P and can not be greater than the total area subpixel display.
  • the minimum distance between two adjacent LEDs 16 is imposed by the method of etching the layers 32, 34, 36 and the method of forming the insulating portions 18 and is generally greater than 3 ⁇ m, or even 5 ⁇ m. This reduces the maximum area that can be occupied by each light-emitting diode 16.
  • the lower electrodes 14 may be made by a continuous electrode layer.
  • the electrode layer 14 has the drawbacks of being resistive and of conducting light.
  • the resistivity of the lower electrode layer 14 strongly limits the maximum size of the optoelectronic device because the voltage drop between the edge and the center can quickly exceed the correction capabilities of the electronic control system.
  • the conduction of the light has the effect of reinjecting a portion of the light emitted by a sub-pixel in the neighboring sub-pixels strongly limiting the contrast and color saturation of the optoelectronic device.
  • the lower electrodes 14 are made by separate bands, the necessary distance between sub-pixels is even greater.
  • Another disadvantage of the manufacturing method described above is that the etching steps of the layers 32, 34, 36 can cause a deterioration of the lateral flanks of the active zone 26 of each light-emitting diode 16 and disturb the light radiation emitted by the active zone 26 so that he It is difficult to produce sub-pixels smaller than 15 ⁇ m by 15 ⁇ m and of good quality.
  • An object of an embodiment is to overcome all or part of the disadvantages of inorganic light emitting diode optoelectronic devices described above, including display screens or projection devices.
  • Another object of an embodiment is to increase the maximum light intensity that can be provided by each display subpixel.
  • Another object of an embodiment is that the manufacturing method of the light-emitting diodes does not include a step of etching the active layers of the light-emitting diodes.
  • an embodiment provides an optoelectronic device comprising a substrate comprising opposite first and second faces, lateral electrical insulation elements extending from the first face to the second face and delimiting in the support of the first semiconductor or conductive portions. electrically insulated from each other, the optoelectronic device further comprising, for each first portion, a first conductive pad on the second face in contact with the first portion and a light emitting diode or a set of light-emitting diodes resting on the first face and electrically connected to the first portion, the optoelectronic device further comprising a conductive and at least partially transparent electrode layer covering all the light emitting diodes, an insulative and at least partially transparent encapsulating layer covering the layer. electrode, and at least one second conductive pad electrically connected to the electrode layer.
  • each diode electro ⁇ phosphor comprises at least one wire semiconductor element, conical or frustoconical, incorporating or coated at the top and / or at least over a part of its side faces by a cover, comprising at least one active layer adapted to provide the majority of the radiation of the light-emitting diode.
  • the opto electronic ⁇ further comprises a conductive layer overlying the electrode layer around the light emitting diodes of each set.
  • the lateral electrical insulation elements comprise at least one insulating wall extending in the substrate from the first face to the second face.
  • the lateral electrical insulation elements delimit, in addition, in the support, a second semiconductor or conductive portion electrically insulated from the first semiconductor or conductive portions and electrically connected to the electrode layer.
  • the second conductive pad is in electrical contact with the second semiconductive or conductive portion on the side of the second face.
  • the second conductive pad is located on the side of the first face.
  • the substrate is silicon, germanium, silicon carbide, a compound III-V, such as GaN or GaAs, or ZnO.
  • the substrate is made of monocrystalline silicon and comprises a dopant concentration of between 5 10 atoms / cm 2 and 2 10 10 atoms / cm 2.
  • each semiconductor element is orally in a compound III-V, in particular gallium nitride, or in a compound II-VI.
  • the optoelectronic device comprises lenses on the encapsulation layer.
  • the optoelectronic device is a display screen or a projection device.
  • One embodiment also relates to a method of manufacturing an optoelectronic device comprising the following steps:
  • step a) comprises the following steps:
  • step b) before step b), forming, in the substrate, lateral electrical insulation elements extending from the first face over a portion of the depth of the substrate; and after step c), thinning the substrate to form the second face and exposing the lateral electrical insulators on the second face.
  • the method further comprises the deposition of phosphor on at least some light-emitting diodes, in particular by techniques of photolithography or printing ⁇ graphy.
  • each light emitting diode comprises at least one semiconductor element wire, conical or frustoconical, incorporating or covered at the top and / or at least on a portion of its lateral faces by a shell comprising at least one active layer adapted to provide the majority of the radiation of the light emitting diode.
  • FIG. 1, previously described, is a sectional, partial and diagrammatic view of an example of an optoelectronic device with inorganic light-emitting diodes;
  • FIGS. 2A to 2C previously described, are sectional, partial and schematic views of structures obtained at successive stages of an exemplary method of manufacturing the optoelectronic device of FIG. 1;
  • FIGS. 3A, 3B and 3C are respectively a top view, a front view with section and a view from below, partial and schematic, of an embodiment of an optoelectronic device with light-emitting diodes;
  • FIGS. 4A to 4C are respectively a top view, a front view with section and a bottom view, partial and schematic, of another embodiment of an optoelectronic device with light-emitting diodes; and FIGS. 5A and 5B are respectively a top view and a sectional front view, partial and schematic, of another embodiment of an optoelectronic light-emitting diode device.
  • the embodiments described hereinafter relate to optoelectronic devices, in particular of affi ⁇ drying screens or projection devices, including light emitting diodes formed from three dimensional semiconductor elements, for example micro-wires, nanowires, elements conical or frustoconical elements.
  • three dimensional semiconductor elements for example micro-wires, nanowires, elements conical or frustoconical elements.
  • embodiments are described for light-emitting diodes formed from microfilts or nanowires.
  • these embodiments can be implemented for three-dimensional elements other than microwires or nanowires, for example three-dimensional pyramid-shaped elements.
  • embodiments are described for light emitting diodes each comprising a shell which at least partially surrounds the microfil or nanowire. However, these embodiments may be implemented for light-emitting diodes for which the active area is located in the height or at the top of the microfilament or nanowire.
  • microfil or "nanowire” denotes a three-dimensional structure of elongated shape in a preferred direction, of which at least two dimensions, called minor dimensions, are between 5 nm and 2.5 ⁇ m, preferably between 50 nm and 2.5 ⁇ m. um, the third dimension, called major dimension, being at least equal to 1 time, preferably at least 5 times and even more preferably at least 10 times, the largest of the minor dimensions.
  • the minor dimensions may be less than or equal to about 1 ⁇ m, preferably between 100 nm and 1 ⁇ m, more preferably between 100 nm and 300 nm.
  • the height of each microfil or nanowire may be greater than or equal to 500 nm, preferably between 1 ⁇ m and 50 ⁇ m.
  • the term “wire” is used to mean “microfil or nanowire”.
  • the average line of the wire which passes through the barycenters of the straight sections, in planes perpendicular to the preferred direction of the wire is substantially rectilinear and is hereinafter called “axis" of the wire.
  • an optoelectronic device in particular a display screen or a projection device, comprising an integrated circuit comprising a substrate, for example a conductive or semiconductor substrate, divided into electrically isolated portions of the substrate. others and comprising, for each display subpixel, sets of light-emitting diodes formed on the front face of the substrate.
  • Each set of light-emitting diodes comprises a light-emitting diode or a plurality of light-emitting diodes connected in parallel.
  • By connecting light-emitting diodes in parallel it is meant that the anodes of the light-emitting diodes are connected together and that the cathodes of the light-emitting diodes are connected together.
  • Each set of elementary light-emitting diodes is equivalent to a global light-emitting diode comprising an anode and a cathode.
  • FIGS. 3A to 3C show an embodiment of an optoelectronic device 40, in particular a display screen or a projection device, comprising:
  • a conductive or semiconductor substrate 42 comprising a lower face 44 and an opposite upper face 46, the upper face 46 preferably being flat at least at the level of the light-emitting diode assemblies;
  • electrical isolation elements 48 which extend in the substrate 42 between the faces 44 and 46 and which divide the substrate 42 into conductive or semiconducting portions 50; conductive pads 52 in contact with the lower face 44, each portion 50 being in contact with one of the conductive pads 52;
  • each germination stud 54 being in contact with the face
  • each wire 56 being in contact with one of the seed pads 54, each wire 56 comprising a lower portion 58 in contact with the seed pad 54 and an upper portion 60, extending the lower portion 58;
  • an insulating layer 62 extending on the face 46 of the substrate 42 and extending on the lateral flanks of the lower portion 58 of each wire 56;
  • a shell 64 comprising a stack of semiconductor layers covering the upper portion 60 of each wire 56;
  • a conductive and at least partially transparent layer 66 forming an electrode covering each shell 64, and extending on the insulating layer 62 between the wires 56;
  • a conductive layer 68 covering the electrode layer 66 between the wires 56 but not extending on the wires 56, the conductive layer 68 being, in addition, in contact with one of the semiconductor portions 50 through an opening
  • a transparent encapsulation layer 70 covering the entire structure.
  • the optoelectronic device 40 may, in addition, comprise a phosphor layer, not shown, and / or colored filters, not shown, in the encapsulation layer.
  • luminophores are distributed among the wires 56.
  • Each wire 56 and the shell 64 associated constitute an elementary light emitting diode.
  • Diodes electro ⁇ elementary luminescent located on the same semiconductor portion 50 form a set D of light emitting diodes.
  • Each set D thus comprises several elementary light-emitting diodes connected in parallel.
  • the number of elementary light-emitting diodes per set D can vary from 1 to several thousand, typically from 25 to 100.
  • the number of elementary light-emitting diodes per set D can vary from one set to another.
  • Each pixel display pixel Pix of the optoelectronic device 40 comprises one of the conductive or semiconducting portions 50 and the set D of light-emitting diodes resting on this portion 50.
  • Figure 3A there is shown schematically the separation between the Pixel subpixels with dashed lines 72.
  • the area occupied by each pixel Pix in a view from above can vary from 3 ⁇ m by 3 ⁇ m to several nm and typically from 10 ⁇ m to 10 ⁇ m. at 100 ⁇ m.
  • Each elemental light-emitting diode is formed of a shell at least partially covering a wire.
  • the developed surface of the active layers of the elementary light-emitting diodes of a set D is greater than the surface of the sub-display pixel comprising this set D.
  • the maximum light intensity that can be provided by the sub-display pixel can therefore be to be greater than that of a display subpixel made with a two-dimensional inorganic light emitting diode technology.
  • the substrate 42 corresponds to a monolithic semiconductor substrate.
  • the semiconductor substrate 42 is, for example, a substrate made of silicon, germanium, or a III-V compound such as GaAs.
  • the substrate 42 is a monocrystalline silicon substrate.
  • the semiconductor substrate 42 is doped so as to lower the electrical resistivity to a resistivity close to that of metals, preferably less than a few mohm.cm.
  • the substrate 42 is preferably a highly doped semiconductor substrate with a dopant concentration of between 5 * 10 ⁇ atoms / cm ⁇ and 2 * 10 ⁇ 0 atoms / cm ⁇ , preferably between 1 * 10 ⁇ atoms / and 2 * 10 ⁇ 0 atoms / cm 2, for example 5 * 10 -3 atoms / cm 2.
  • the substrate 42 has a thickness of between 275 ⁇ m and 1500 ⁇ m, preferably 725 ⁇ m.
  • the substrate 42 has a thickness of between 1 ⁇ m and 100 ⁇ m.
  • examples of P type dopants are boron (B) or indium (In) and examples of N type dopants are phosphorus (P), arsenic ( As), or antimony (Sb).
  • the substrate 42 is N-doped with phosphorus.
  • the face 44 of the silicon substrate 42 may be a face (100).
  • the germination pads 54 are made of a material that promotes the growth of the yarns 56.
  • a treatment can be provided to protect the lateral flanks of the seedlings and the surface of the parts of the substrate that are not covered by the bumps. germination to prevent growth of the yarns on the lateral flanks of the seed pads and on the surface of the parts of the substrate not covered by the seed pads.
  • the treatment may comprise forming a dielectric region on the lateral flanks of the seed pads and extending on and / or in the substrate and connecting, for each pair of pads, one of the pads of the pair to the other stud of the pair, the wires not growing on the dielectric region. Said dielectric region can overflow over the seed pads 54.
  • the seed pads 54 can be replaced by a seed layer covering the face 46 of the substrate 42. A dielectric region can then be formed above of the seed layer to prevent growth of threads in unwanted locations.
  • the material constituting the seed pads 54 may be a transition metal of column IV, V or VI of the periodic table of the elements or a nitride, a carbide or a boride of a transition metal of the column IV, V or VI of the periodic table of elements or a combination of these compounds.
  • the seed pads 54 may be made of aluminum nitride (AIN), boron (B), boron nitride (BN), titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), hafnium (Hf), hafnium nitride (HfN), niobium (Nb), niobium nitride (NbN), zirconium (Zr), zirconium borate (ZrB 2), of zirconium nitride (ZrN), silicon carbide (SiC), nitride and tantalum carbide (TaCN), magnesium nitride in the form Mg x Ny, where x is approximately equal to 3 and y is approximately equal to 2, for example magnesium nitride according to the form 3 ⁇ 4 ⁇ 2 or gallium and magnesium nitride (MgGaN), tungsten (W), tungsten nitride (WN)
  • the insulating layer 62 may be a dielectric material, such as silicon oxide (S1O2) f silicon nitride (Si x N y, where x is approximately equal to 3 and y is equal to about 4, e.g., S13N4) , in silicon oxynitride (SiO x Ny where x may be about 1/2 and y may be about 1, eg S12ON2), aluminum oxide (Al2O3), hafnium oxide (HfC > 2) or diamond.
  • the thickness of the insulating layer 62 is between 5 nm and 800 nm, for example equal to about 30 nm.
  • the wires 56 are at least partly formed from at least one semiconductor material.
  • the semiconductor material may be silicon, germanium, silicon carbide, a III-V compound, a II-VI compound or a combination thereof.
  • the wires 56 may be, at least in part, formed from semiconducting materials, typically having a III-V compound, for example III-N compounds.
  • III-V compounds include gallium (Ga), indium (In) or aluminum (Al).
  • III-N compounds are GaN, AlN, InN, InGaN, AlGaN or AlInGaN.
  • Other group V elements may also be used, for example, phosphorus or arsenic. In general, the elements in compound III-V can be combined with different mole fractions.
  • the wires 56 may be, at least in part, formed from semiconductor materials having a compound II-VI.
  • Group II elements include Group IIA elements, including beryllium (Be) and magnesium (Mg) and Group IIB elements, including zinc (Zn) and cadmium (Cd).
  • Group VI elements include elements of the VIA group, including oxygen (O) and tellurium (Te).
  • compounds II-VI are ZnO, ZnMgO, CdZnO or CdZnMgO. In general, the elements in II-VI can be combined with different mole fractions.
  • the wires 56 may comprise a dopant.
  • the dopant may be chosen from the group comprising a group II P dopant, for example magnesium (Mg), zinc (Zn), cadmium (Cd ) or mercury (Hg), a group IV P-type dopant, for example carbon (C) or a group IV N-type dopant, for example silicon (Si), germanium (Ge), selenium (Se), sulfur (S), terbium (Tb) or tin (Sn).
  • a group II P dopant for example magnesium (Mg), zinc (Zn), cadmium (Cd ) or mercury (Hg)
  • a group IV P-type dopant for example carbon (C) or a group IV N-type dopant, for example silicon (Si), germanium (Ge), selenium (Se), sulfur (S), terbium (Tb) or tin (Sn).
  • the cross section of the yarns 56 may have different shapes, such as, for example, an oval, circular or polygonal shape, in particular triangular, rectangular, square or hexagonal.
  • the wires are represented with a hexagonal cross-section.
  • cross section corresponding, for example, to the diameter of the disk having the same surface as the cross section of the wire.
  • the diameter average of each wire 56 may be between 50 nm and 5 um.
  • the height of each wire 56 may be between 250 nm and 50 ⁇ m.
  • Each wire 56 may have an elongate semiconductor structure along an axis substantially perpendicular to the face 46.
  • Each wire 56 may have a generally cylindrical shape.
  • the axes of two adjacent yarns 56 may be spaced from 0.5 ⁇ m to 10 ⁇ m and preferably from 1.5 ⁇ m to 5 ⁇ m.
  • the wires 56 may be regularly distributed, in particular along a hexagonal network.
  • each wire 56 is preferably composed of the compound III-N, for example doped gallium nitride of the same type as the substrate 42, for example N-type, for example silicon .
  • the lower portion 58 extends over a height which may be between 100 nm and 25 ⁇ m.
  • the upper portion 60 of each wire 56 is at least partially made of a III-N compound, for example GaN.
  • the upper portion 60 may be N-type doped, possibly less strongly doped than the lower portion 58 or not be intentionally doped.
  • the upper portion 60 extends over a height that can be between
  • the shell 64 may comprise a stack of several layers including:
  • the active layer is the layer from which the majority of the radiation provided by the elementary light emitting diode is emitted.
  • the active layer may include means for confining electric charge carriers, such as multiple quantum wells. She is, for example, consisting of an alternation of GaN and InGaN layers having respective thicknesses of 5 to 20 nm (for example 8 nm) and 1 to 15 nm (for example 2.5 nm).
  • the GaN layers may be doped, for example of the N or P type.
  • the active layer may comprise a single layer of InGaN, for example with a thickness greater than 10 nm.
  • the intermediate layer for example doped P-type, may correspond to a semiconductor layer or a stack of semiconductor layers and allows the formation of a PN or PIN junction, the active layer being between the intermediate layer of type P and the N-type upper portion 60 of the PN or PIN junction.
  • the bonding layer may correspond to a semiconductor layer or a stack of semiconductor layers and allows the formation of an ohmic contact between the intermediate layer and the electrode 66.
  • the bonding layer may be doped very thinly. strongly of the type opposite to the lower portion 58 of each wire 56, until degenerate the semiconductor layer or layers, for example doped P type at a concentration greater than or equal to 10 ⁇ 0 atoms / cm- ⁇ .
  • the semiconductor layer stack may comprise an electron blocking layer formed of a ternary alloy, for example gallium aluminum nitride (AlGaN) or indium aluminum nitride (AlInN) in contact with each other. with the active layer and the intermediate layer, to ensure a good distribution of the electric carriers in the active layer.
  • a ternary alloy for example gallium aluminum nitride (AlGaN) or indium aluminum nitride (AlInN) in contact with each other. with the active layer and the intermediate layer, to ensure a good distribution of the electric carriers in the active layer.
  • the electrode 66 is adapted to polarize the active layer of each wire 56 and to let the electromagnetic radiation emitted by the light-emitting diodes.
  • the material forming the electrode 66 may be a transparent and conductive material such as indium tin oxide (ITO), zinc oxide doped with aluminum, gallium or indium, or graphene.
  • ITO indium tin oxide
  • the electrode layer 66 has a thickness of between 5 nm and 200 nm, preferably between 20 nm and 50 nm.
  • the conductive layer 68 preferably corresponds to a metal layer, for example aluminum, copper, gold, ruthenium or silver, or to a stack of metal layers, for example titanium-aluminum, silicon-aluminum, titanium-nickel-silver, copper or zinc.
  • the conductive layer 68 has a thickness of between 20 nm and 1500 nm, preferably between 400 nm and 800 nm.
  • the conductive layer 68 is present only between the son and does not cover the emissive surface thereof.
  • the conductive layer 68 makes it possible to reduce the resistive losses during the flow of the current. It also has a reflector role to send out the rays emitted by the light-emitting diodes in the direction of the substrate.
  • the encapsulation layer 70 is made of at least partially transparent insulating material.
  • the minimum thickness of the encapsulation layer 70 is between 250 nm and 50 ⁇ m so that the encapsulation layer 70 completely covers the electrode layer 66 at the top of the sets D of light emitting diodes.
  • the encapsulation layer 70 may be made of at least partially transparent inorganic material.
  • the inorganic material is chosen from the group comprising silicon oxides of the SiO x type where x is a real number between 1 and 2 or SiOyN z where y and z are real numbers between 0 and 1 and aluminum oxides, for example Al2O3.
  • the encapsulation layer 70 may be made of at least partially transparent organic material.
  • the encapsulation layer 70 is a silicone polymer, an epoxy polymer, an acrylic polymer or a polycarbonate.
  • the electrical insulation elements 48 may comprise trenches extending over the entire thickness of the substrate 42 and filled with an insulating material, for example an oxide, in particular silicon oxide, or an insulating polymer. Alternatively, the walls of each trench 48 are covered with an insulating layer, the remainder of the trench being filled with a semiconductor or conductive material, for example polycrystalline silicon. According to another variant, the electrical insulation elements 48 comprise doped regions of a type of polarity opposite to the substrate 42 and extending over the entire depth of the substrate 42. For example, each trench 48 has a width greater than 1 ⁇ m, which varies in particular from 1 ⁇ m to 10 ⁇ m, for example about 2 ⁇ m.
  • an insulating material for example an oxide, in particular silicon oxide, or an insulating polymer.
  • the walls of each trench 48 are covered with an insulating layer, the remainder of the trench being filled with a semiconductor or conductive material, for example polycrystalline silicon.
  • the electrical insulation elements 48 comprise doped regions of a type of polarity opposite to the substrate
  • the electrical insulation elements 48 comprise pairs of adjacent trenches 48 which delimit the portions 50 of the substrate 42.
  • a single trench 48 may be provided to electrically isolate each portion 50.
  • trenches so fine can be made with a limited depth, between ten micrometers and a hundred micrometers according to the chosen etching and insulation technique. It is therefore advisable to thin the substrate 42 until the electrical insulation elements 48 are flush.
  • a handle made of a rigid material can be fixed temporarily or permanently to the encapsulation layer 70.
  • the handle is made of a material at least partially transparent. It may be glass, especially a borosilicate glass, for example glass known under the name pyrex, or sapphire. After thinning the rear face 44 of the substrate can be treated, and if the gluing is temporary, the handle can be peeled off.
  • Each conductive pad 52 may correspond to a layer or a stack of layers covering the face 44.
  • an insulating layer may partially cover the face 44, each conductive pad 52 being in contact with the associated semiconducting portion 50 openings etched in this insulating layer.
  • the optoelectronic device 40 is fixed to another circuit by fusible conductive elements, not shown, for example solder balls or indium balls fixed to the conductive pads 52.
  • the assembly of the optoelectronic device 40 on another circuit, in particular on a control circuit is done by means of conventional techniques of matrix hybridization, by means of fusible balls, for example indium, or SnAg, or copper columns or studs.
  • conductive pads 52 are chosen to be compatible with the chosen assembly technology.
  • conductive pads 52 may be Cu or Ti-Ni-Au, Sn-Ag or Ni-Pd-Au.
  • the active layer of the shell 64 of the elementary light-emitting diodes of at least one of the sets of light-emitting diodes D may be manufactured differently from the active layer of the shell of the elementary light-emitting diodes of at least one other set of diodes. emitting.
  • the active layer of the shell 64 of a first set may be adapted to emit light at a first wavelength, for example a blue light
  • the active layer of the shell 64 of a second set may be adapted to emit light at a second wavelength different from the first wavelength, for example a green light. This can be achieved, for example, by adapting in each set the pitch and size of the son, which has the effect of modifying the thickness and the composition of the quantum wells composing these active layers.
  • a third set may be adapted to emit light at a third wavelength different from the first and second wavelengths, for example a red light.
  • a third wavelength different from the first and second wavelengths, for example a red light.
  • the composition of the blue, green, and red lights can be chosen so that an observer perceives a white light by composition of the colors, each diode, or together of diodes, emitting at a first, second and third wavelength that can be addressed independently of others to adjust the color.
  • a phosphor is deposited between and on electroluminescent diodes of a sub-pixel.
  • the phosphor can absorb the deep blue light emitted by the light-emitting diodes and transform it into green or red, or even blue.
  • the advantage of using a blue phosphor and not the natural emission of the light-emitting diodes is an insensitivity of the quality of the blue to the color variations of the spontaneous emission of the wires, from one batch to another or within the same substrate.
  • a selective phosphor deposition method consists of mixing the phosphor grains of a first color with photosensitive silicone resin, then after spreading over the entire substrate and light-emitting diodes, to fix luminophores on the desired sub-pixels. by photolithography. The operation is repeated with a second phosphor and as many times as there are subpixels of different colors.
  • Another method is to use inkjet type printing equipment with an "ink” composed of the silicone-phosphor mixture and specific additives. By printing, from mapping and orientation and referencing the sub-pixels, phosphors are deposited at the required locations.
  • Lenses may be provided on the encapsulation layer 70.
  • a lens may be provided for each subpixel or sets of subpixels.
  • the insulating layer 62 covers the entire periphery of the lower portion 58 of each wire 56.
  • a portion of the lower portion 58, or even the entire lower portion 58, may not to be covered by the insulating layer 62.
  • the shell 64 may cover each wire 56 on a height greater than the height of the upper portion 60, or over the entire height of the wire 56.
  • the insulating layer 62 does not cover the perimeter of the upper portion 60 of each wire 56.
  • the insulating layer 62 may cover part of the upper portion 60 of each wire 56.
  • the insulating layer 62 may, for each wire 56, partially cover the lower portion of the wire. the shell 64.
  • the layer 62 may not be present, especially in the case where the seed pads 54 are replaced by a seed layer covered with a dielectric layer and that the son are formed on the seed layer in openings provided in the dielectric layer.
  • the optoelectronic device 40 may be attached to another integrated circuit, in particular a control circuit, comprising electronic components, in particular transistors, used for controlling the light-emitting diode assemblies of the optoelectronic device 40.
  • a control circuit comprising electronic components, in particular transistors, used for controlling the light-emitting diode assemblies of the optoelectronic device 40.
  • the conductive pads 52 electrically connected to the conductive layer 68 may be connected to a source of a first reference potential.
  • the conductive pad 52 in contact with the portion 50 of the substrate 42 on which the elementary light-emitting diodes of a set D of light-emitting diodes to be activated can be connected to a source of a second reference potential so as to circulate a current through the elementary light-emitting diodes of the set D considered. Since each conductive pad 52 can extend over a large part of the associated portion 50, a homogeneous distribution of the current can be obtained.
  • the conductive layer 68 is shown in contact with portions 50 along one side of the optoelectronic device 40.
  • the conductive layer 68 may be in contact with portions 50 over the entire around the optoelectronic device 40.
  • the optoelectronic device 40 is at least partly made according to the method described in the patent application FR13 / 59413 which is considered to be an integral part of the present description.
  • An embodiment of a method of manufacturing the optoelectronic device 40 may comprise the following steps:
  • the opening may be formed by a reactive ion etching type etching, for example a DRIE engraving.
  • the depth of the opening is strictly greater than the target thickness of the substrate 42 after a thinning step described below.
  • the depth of the opening is between 10 ⁇ m and 200 ⁇ m, for example about 35 ⁇ m or 60 ⁇ m.
  • an insulating layer for example silicon oxide
  • the thickness of the insulating layer may be between 100 nm and 3000 nm, for example about 200 nm.
  • a filling material for example polycrystalline silicon, tungsten or a refractory metal material compatible with the steps of the manufacturing process carried out at high temperatures, deposited for example by chemical vapor deposition at low pressure (LPCVD) for low pressure chemical vapor deposition.
  • LPCVD chemical vapor deposition at low pressure
  • the polycrystalline silicon advantageously has a coefficient of thermal expansion close to silicon and thus makes it possible to reduce the mechanical stresses during the steps of the manufacturing process carried out at high temperatures.
  • CMP Mechano-chemical polishing
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • Atomic Layer Deposition Atomic Layer Deposition
  • PVD Physical Vapor Deposition
  • each elemental light-emitting diode is formed by epitaxial growth steps on a portion of the wire 56.
  • the manufacturing process of the optoelectronic device 40 therefore does not include etching steps liable to deteriorate the active zones of the light-emitting diodes. .
  • the delimitation of the pixels Pix display subpixels is performed only by the electrical insulation elements 48 and does not lead to changes in the manufacturing steps of the elementary light emitting diodes.
  • the diodes The elementary electroluminescent electrodes may be uniformly distributed on the face 46 of the substrate 42. Even though elementary light-emitting diodes may be in line with electrical insulation elements 48 and not be functional, this has the advantage that the steps of FIG. Elemental light emitting diodes are identical irrespective of the shape of the sub-display pixels.
  • the optoelectronic device 40 is electrically connected to an external circuit by solder balls provided on the side of the lower face 44 of the substrate 42.
  • solder balls provided on the side of the lower face 44 of the substrate 42.
  • other modes of electrical connection can be considered.
  • the substrate 42 is a substrate made of a semiconductor or conductive material.
  • the substrate 42 is wholly or partly made of an insulating material, for example silicon dioxide (SiO 2) or sapphire.
  • the electrical connection between the conductive pads 52 and the conductive layer 68 or the seed pads 54 can be achieved by using conductive elements passing through the substrate 42 over its entire thickness, for example vias through or TSV (acronym for Through Silicon Via).
  • FIGS. 4A, 4B and 4C are figures similar respectively to FIGS. 3A, 3B and 3C of another embodiment of an optoelectronic device 80, in particular a display screen or a projection device, in which at least one conductive pad 82 is provided in contact with the conductive layer 68 on the side of the front face 46.
  • the encapsulation layer 70 then comprises an opening 84 which exposes the conductive pad 82.
  • the opening 69 described above is not present.
  • Neither the conductive layer 68 nor the electrode layer 66 are in electrical contact with the semiconductor substrate 42.
  • the conductive pad 82 is electrically connected to an external circuit, not shown, by a not shown wire.
  • a single conductive pad 82 is shown in FIG. 4A.
  • several conductive pads 82 may be distributed over the conductive layer 68, for example at the periphery of the optoelectronic device 80.
  • FIGS. 5A and 5B are figures similar to FIGS. 3A and 3B, respectively, of another embodiment of an optoelectronic device 90, in particular a display screen or a projection device.
  • the optoelectronic device 90 comprises all the elements of the optoelectronic device 40 and furthermore comprises opaque portions 92 resting on the conductive layer 68 between adjacent display sub-pixels, that is to say substantially in the extension of the electrical insulation elements 48.
  • each opaque portion 92 may be greater than or equal to the height of the wires 56.
  • the width of each opaque portion 92 is less than or equal to the smallest gap between two elementary light-emitting diodes of adjacent D-sets.
  • each opaque portion 82 may be in a resin colored in black. This resin is preferably adapted to absorb electromagnetic radiation over the entire visible spectrum. The presence of the opaque portions 92 advantageously makes it possible to increase the contrast of the optoelectronic device 90.
  • the structure of the optoelectronic device 90 shown in FIGS. 5A and 5B can be implemented with the structure of the optoelectronic device 80 shown in FIGS. 4A, 4B and 4C.

Abstract

The invention relates to an optoelectronic device (40) including: - a substrate (42) with first and second opposite surfaces (44, 46); and - electrical insulation side elements (48) extending from the first surface (46) to the second surface (44) and defining, within the substrate, first semi-conductive or conductive portions (50) which are electrically insulated from each other. The optoelectronic device also includes, for each first portion: - a first conductive contact pad (52) on the second surface in contact with the first portion; and - a set (D) of light-emitting diodes resting on the first surface and electrically connected to the first portion. The optoelectronic device also includes: - a conductive, at least partially transparent electrode layer (66) covering all the light-emitting diodes; - an insulating, at least partially transparent encapsulation layer (70) covering the electrode layer; and - at least one second conductive contact pad (52) electrically connected to the electrode layer.

Description

DISPOSITIF OPTOELECTRONIQUE A DIODES ELECTROLUMINESCENTES  OPTOELECTRONIC DEVICE WITH LIGHT EMITTING DIODES
La présente demande de brevet revendique la priorité de la demande de brevet français FR14/63420 qui sera considérée comme faisant partie intégrante de la présente description. The present patent application claims the priority of the French patent application FR14 / 63420 which will be considered as an integral part of the present description.
Domaine Field
La présente demande concerne un dispositif opto¬ électronique à diodes électroluminescentes, notamment à diodes électroluminescentes en matériaux inorganiques, par exemple un écran d'affichage ou un dispositif de projection d'images. The present application relates to an opto ¬ electronic device emitting diodes, in particular LEDs in inorganic materials, for example a display screen or an image projection device.
Exposé de l'art antérieur Presentation of the prior art
Il existe des dispositifs optoélectroniques, notamment des écrans d'affichage ou des dispositifs de projection, comprenant des diodes électroluminescentes à base de matériaux semiconducteurs comprenant un empilement de couches semiconduc- trices comportant majoritairement au moins un élément du groupe III et un élément du groupe V, appelé par la suite composé III-V, notamment le nitrure de gallium (GaN) , le nitrure de gallium et d'indium (GalnN) et le nitrure de gallium et d'aluminium (GaAIN) .  There are optoelectronic devices, in particular display screens or projection devices, comprising light-emitting diodes based on semiconductor materials, comprising a stack of semiconductor layers predominantly comprising at least one group III element and a group V element. , hereinafter called III-V compound, in particular gallium nitride (GaN), gallium indium nitride (GalnN) and gallium aluminum nitride (GaAIN).
Un pixel d'une image correspond à l'élément unitaire de l'image affichée par un écran d'affichage ou projetée par un dispositif de projection. Lorsque le dispositif optoélectronique est un écran d'affichage d'images monochromes ou un dispositif de projection d'images monochromes, il comprend en général une seule source lumineuse pour l'affichage de chaque pixel de l'image. Lorsque le dispositif optoélectronique est un écran d'affichage d'images couleur ou un dispositif de projection d'images couleur, il comprend en général pour l'affichage de chaque pixel d'image au moins trois composants d'émission et/ou de régulation de l'intensité lumineuse, également appelés sous-pixels d'affichage, qui émettent chacun un rayonnement lumineux sensiblement dans une seule couleur (par exemple, le rouge, le vert et le bleu) . La superposition des rayonnements émis par ces trois sous-pixels d'affichage fournit à l'observateur la sensation colorée correspondant au pixel de l'image affichée. On appelle dans ce cas pixel d'affichage de l'écran d'affichage ou du dispositif de projection l'ensemble formé par les trois sous-pixels d'affichage utilisés pour l'affichage d'un pixel d'image. A pixel of an image corresponds to the unitary element of the image displayed by a display screen or projected by a projection device. When the optoelectronic device is a monochrome image display screen or a monochrome image projection device, it generally comprises only one light source for displaying each pixel of the image. When the optoelectronic device is a color image display screen or a color image projection device, it generally comprises for the display of each image pixel at least three emission and / or regulation components luminous intensity, also called sub-display pixels, which each emit light radiation substantially in a single color (for example, red, green and blue). The superposition of the radiation emitted by these three sub-display pixels provides the observer with the color sensation corresponding to the pixel of the displayed image. In this case, it is called the display pixel of the display screen or the projection device the assembly formed by the three display sub-pixels used for the display of an image pixel.
La figure 1 représente un exemple de dispositif optoélectronique 10 à diodes électroluminescentes inorganiques, tel qu'un écran d'affichage ou un dispositif de projection. Le dispositif optoélectronique 10 comprend successivement du bas vers le haut en figure 1 :  FIG. 1 represents an example of an optoelectronic device 10 with inorganic light-emitting diodes, such as a display screen or a projection device. The optoelectronic device 10 successively comprises from bottom to top in FIG. 1:
un support 12 ;  a support 12;
des électrodes inférieures 14, correspondant par exemple à des bandes conductrices parallèles ;  lower electrodes 14, corresponding for example to parallel conductive strips;
des diodes électroluminescentes inorganiques 16 reposant sur les électrodes inférieures 14 et séparées les unes des autres par des portions isolantes 18 ;  inorganic light-emitting diodes 16 resting on the lower electrodes 14 and separated from each other by insulating portions 18;
des électrodes supérieures 20 transparentes au contact des faces supérieures des diodes électroluminescentes inor¬ ganiques 16 ; et upper transparent electrodes 20 in contact with upper surfaces of the LEDs inor ganic ¬ 16; and
une couche de protection transparente 22 recouvrant l'ensemble de la structure.  a transparent protective layer 22 covering the entire structure.
Des couches de luminophores et/ou des filtres colorés peuvent être prévus sur la couche de protection 22.  Phosphor layers and / or color filters may be provided on the protective layer 22.
Chaque diode électroluminescente inorganique 16 comprend un empilement de portions semiconductrices comprenant successivement du bas vers le haut en figure 1 : une portion semiconductrice 24 dopée d'un premier type de conductivité, par exemple de type N, au contact de l'une des électrodes 14 ; Each inorganic light-emitting diode 16 comprises a stack of semiconductor portions comprising successively from bottom to top in FIG. a semiconductor portion 24 doped with a first type of conductivity, for example N type, in contact with one of the electrodes 14;
une zone active 26, c'est-à-dire la zone de la diode électroluminescente émettant la majorité du rayonnement lumineux fourni par la diode électroluminescente en fonctionnement, correspondant à une structure monocouche ou multicouche comprenant, par exemple, une portion semiconductrice non dopée, un puits quantique unique ou des puits quantiques multiples ; et une portion semiconductrice 28 dopée d'un deuxième type de conductivité, opposé au premier type de conductivité, par exemple de type P, au contact de l'une des électrodes 20.  an active zone 26, that is to say the zone of the light-emitting diode emitting the majority of the light radiation provided by the light-emitting diode in operation, corresponding to a monolayer or multilayer structure comprising, for example, an undoped semiconductor portion, a single quantum well or multiple quantum wells; and a doped semiconductor portion 28 of a second conductivity type, opposite the first type of conductivity, for example of the P type, in contact with one of the electrodes 20.
De telles diodes électroluminescentes 16 sont dites bidimensionnelles dans la mesure où elles sont formées d'un empilement de couches minces et planes. Chaque sous-pixel d'affichage P du dispositif optoélectronique 10 comprend une diode électroluminescente 16, une portion isolante 18 entourant la diode électroluminescente 16 et des parties de l'une des électrodes 14 et de l'une des électrodes 20 au contact de la diode électroluminescente 16. A titre d'exemple, la surface occupée par chaque sous-pixel d'affichage P peut correspondre à un carré dont le côté est compris entre 100 p et 1 mm.  Such light-emitting diodes 16 are said to be two-dimensional insofar as they are formed of a stack of thin and flat layers. Each display subpixel P of the optoelectronic device 10 comprises a light-emitting diode 16, an insulating portion 18 surrounding the light-emitting diode 16 and portions of one of the electrodes 14 and one of the electrodes 20 in contact with the diode By way of example, the area occupied by each display subpixel P may correspond to a square whose side is between 100 p and 1 mm.
Les figures 2A à 2C représentent les structures obtenues à des étapes successives d'un exemple de procédé de fabrication du dispositif optoélectronique 10.  FIGS. 2A to 2C show the structures obtained at successive stages of an exemplary method of manufacturing the optoelectronic device 10.
La figure 2A représente la structure obtenue après avoir formé les électrodes inférieures 14 sur le support 12 et après avoir déposé sur l'ensemble de la structure un empilement 30 de couches semiconductrices successives 32, 34, 36.  FIG. 2A shows the structure obtained after having formed the lower electrodes 14 on the support 12 and after having deposited on the whole of the structure a stack 30 of successive semiconductor layers 32, 34, 36.
La figure 2B représente la structure obtenue après avoir gravé des ouvertures 38 dans l'empilement 30 pour délimiter les portions semiconductrices 24, 26, 28 pour chaque diode électroluminescente 16.  FIG. 2B shows the structure obtained after etching apertures 38 in stack 30 to delimit the semiconductor portions 24, 26, 28 for each light-emitting diode 16.
La figure 2C représente la structure obtenue après avoir formé les portions isolantes 18 dans les ouvertures 38 entre les diodes électroluminescentes 16. Ceci peut être réalisé en déposant une couche isolante sur la totalité de la structure représentée en figure 2B, cette couche isolante recouvrant les diodes électroluminescentes 16 et remplissant les ouvertures 38 et en gravant la couche isolante jusqu'à atteindre les portions 28 des diodes électroluminescentes 16. FIG. 2C represents the structure obtained after having formed the insulating portions 18 in the openings 38 between the 16. This can be achieved by depositing an insulating layer on the entire structure shown in FIG. 2B, this insulating layer covering the light-emitting diodes 16 and filling the openings 38 and etching the insulating layer until reaching the portions 28. electroluminescent diodes 16.
L'intensité lumineuse maximale pouvant être émise par chaque sous-pixel d'affichage P dépend de la surface occupée par la diode électroluminescente 16 par rapport à la surface du sous- pixel d'affichage P et ne peut pas être supérieure à la surface totale du sous-pixel d'affichage. La distance minimale entre deux diodes électroluminescentes adjacentes 16 est imposée par le procédé de gravure des couches 32, 34, 36 et le procédé de formation des portions isolantes 18 et est généralement supérieure à 3 um, voire à 5 um. Ceci réduit la surface maximale pouvant être occupée par chaque diode électroluminescente 16.  The maximum light intensity that can be emitted by each display subpixel P depends on the area occupied by the light-emitting diode 16 relative to the surface of the display subpixel P and can not be greater than the total area subpixel display. The minimum distance between two adjacent LEDs 16 is imposed by the method of etching the layers 32, 34, 36 and the method of forming the insulating portions 18 and is generally greater than 3 μm, or even 5 μm. This reduces the maximum area that can be occupied by each light-emitting diode 16.
Les électrodes inférieures 14 peuvent être réalisées par une couche d'électrode continue. Toutefois, la couche d'électrode 14 présente les inconvénients d'être résistives et de conduire la lumière. La résistivité de la couche d'électrode inférieure 14 limite fortement la taille maximale du dispositif optoélectronique car la chute de tension entre le bord et le centre peut rapidement excéder les capacités de correction du système électronique de commande. La conduction de la lumière a pour effet de réinjecter une partie de la lumière émise par un sous-pixel dans les sous- pixels voisins limitant fortement le contraste et la saturation des couleurs du dispositif optoélectronique. Lorsque les électrodes inférieures 14 sont réalisées par des bandes distinctes, la distance nécessaire entre sous-pixels est encore supérieure.  The lower electrodes 14 may be made by a continuous electrode layer. However, the electrode layer 14 has the drawbacks of being resistive and of conducting light. The resistivity of the lower electrode layer 14 strongly limits the maximum size of the optoelectronic device because the voltage drop between the edge and the center can quickly exceed the correction capabilities of the electronic control system. The conduction of the light has the effect of reinjecting a portion of the light emitted by a sub-pixel in the neighboring sub-pixels strongly limiting the contrast and color saturation of the optoelectronic device. When the lower electrodes 14 are made by separate bands, the necessary distance between sub-pixels is even greater.
Un autre inconvénient du procédé de fabrication décrit précédemment est que les étapes de gravure des couches 32, 34, 36 peuvent entraîner une détérioration des flancs latéraux de la zone active 26 de chaque diode électroluminescente 16 et perturber le rayonnement lumineux émis par la zone active 26 de sorte qu'il est difficile de réaliser des sous-pixels de dimensions inférieures à 15 um par 15 um et de bonne qualité. Another disadvantage of the manufacturing method described above is that the etching steps of the layers 32, 34, 36 can cause a deterioration of the lateral flanks of the active zone 26 of each light-emitting diode 16 and disturb the light radiation emitted by the active zone 26 so that he It is difficult to produce sub-pixels smaller than 15 μm by 15 μm and of good quality.
Résumé  summary
Un objet d'un mode de réalisation est de pallier tout ou partie des inconvénients des dispositifs optoélectroniques à diodes électroluminescentes inorganiques décrits précédemment, notamment des écrans d'affichage ou des dispositifs de projection.  An object of an embodiment is to overcome all or part of the disadvantages of inorganic light emitting diode optoelectronic devices described above, including display screens or projection devices.
Un autre objet d'un mode de réalisation est d'augmenter l'intensité lumineuse maximale pouvant être fournie par chaque sous-pixel d'affichage.  Another object of an embodiment is to increase the maximum light intensity that can be provided by each display subpixel.
Un autre objet d'un mode de réalisation est que le procédé de fabrication des diodes électroluminescentes ne comprend pas d'étape de gravure des couches actives des diodes électroluminescentes .  Another object of an embodiment is that the manufacturing method of the light-emitting diodes does not include a step of etching the active layers of the light-emitting diodes.
Ainsi, un mode de réalisation prévoit un dispositif optoélectronique comprenant un substrat comprenant des première et deuxième faces opposées, des éléments d'isolation électrique latérale s 'étendant de la première face à la deuxième face et délimitant dans le support des premières portions semiconductrices ou conductrices isolées électriquement les unes des autres, le dispositif optoélectronique comprenant, en outre, pour chaque première portion, un premier plot conducteur sur la deuxième face au contact de la première portion et une diode électroluminescente ou un ensemble de diodes électroluminescentes reposant sur la première face et reliées électriquement à la première portion, le dispositif optoélectronique comprenant, en outre, une couche d'électrode conductrice et au moins partiellement transparente recouvrant toutes les diodes électroluminescentes, une couche d' encapsulâtion isolante et au moins partiellement transparente recouvrant la couche d'électrode, et au moins un deuxième plot conducteur relié électriquement à la couche d'électrode.  Thus, an embodiment provides an optoelectronic device comprising a substrate comprising opposite first and second faces, lateral electrical insulation elements extending from the first face to the second face and delimiting in the support of the first semiconductor or conductive portions. electrically insulated from each other, the optoelectronic device further comprising, for each first portion, a first conductive pad on the second face in contact with the first portion and a light emitting diode or a set of light-emitting diodes resting on the first face and electrically connected to the first portion, the optoelectronic device further comprising a conductive and at least partially transparent electrode layer covering all the light emitting diodes, an insulative and at least partially transparent encapsulating layer covering the layer. electrode, and at least one second conductive pad electrically connected to the electrode layer.
Selon un mode de réalisation, chaque diode électro¬ luminescente comprend au moins un élément semiconducteur filaire, conique ou tronconique, intégrant ou recouvert au sommet et/ou au moins sur une partie de ses faces latérales par une coque comprenant au moins une couche active adaptée à fournir la majorité du rayonnement de la diode électroluminescente. According to one embodiment, each diode electro ¬ phosphor comprises at least one wire semiconductor element, conical or frustoconical, incorporating or coated at the top and / or at least over a part of its side faces by a cover, comprising at least one active layer adapted to provide the majority of the radiation of the light-emitting diode.
Selon un mode de réalisation, le dispositif opto¬ électronique comprend, en outre, une couche conductrice recouvrant la couche d'électrode autour des diodes électroluminescentes de chaque ensemble. According to one embodiment, the opto electronic ¬ further comprises a conductive layer overlying the electrode layer around the light emitting diodes of each set.
Selon un mode de réalisation, les éléments d' isolation électrique latérale comprennent au moins un mur isolant s' étendant dans le substrat de la première face à la deuxième face.  According to one embodiment, the lateral electrical insulation elements comprise at least one insulating wall extending in the substrate from the first face to the second face.
Selon un mode de réalisation, les éléments d'isolation électrique latérale délimitent, en outre, dans le support, une deuxième portion semiconductrice ou conductrice isolée électriquement des premières portions semiconductrices ou conductrices et reliée électriquement à la couche d'électrode.  According to one embodiment, the lateral electrical insulation elements delimit, in addition, in the support, a second semiconductor or conductive portion electrically insulated from the first semiconductor or conductive portions and electrically connected to the electrode layer.
Selon un mode de réalisation, le deuxième plot conducteur est au contact électrique de la deuxième portion semiconductrice ou conductrice du côté de la deuxième face.  According to one embodiment, the second conductive pad is in electrical contact with the second semiconductive or conductive portion on the side of the second face.
Selon un mode de réalisation, le deuxième plot conducteur est situé du côté de la première face.  According to one embodiment, the second conductive pad is located on the side of the first face.
Selon un mode de réalisation, le substrat est en silicium, en germanium, en carbure de silicium, en un composé III- V, tel que du GaN ou du GaAs, ou en ZnO.  According to one embodiment, the substrate is silicon, germanium, silicon carbide, a compound III-V, such as GaN or GaAs, or ZnO.
Selon un mode de réalisation, le substrat est en silicium monocristallin et comprend une concentration de dopants comprise entre 5*ÎO-^ atomes/cm-^ et 2*10^0 atomes/cm-^.  According to one embodiment, the substrate is made of monocrystalline silicon and comprises a dopant concentration of between 5 10 atoms / cm 2 and 2 10 10 atoms / cm 2.
Selon un mode de réalisation, chaque élément semiconducteur est ma oritairement en un composé III-V, notamment du nitrure de gallium, ou en un composé II-VI.  According to one embodiment, each semiconductor element is orally in a compound III-V, in particular gallium nitride, or in a compound II-VI.
Selon un mode de réalisation, le dispositif optoélectronique comprend des lentilles sur la couche d' encapsulâtion .  According to one embodiment, the optoelectronic device comprises lenses on the encapsulation layer.
Selon un mode de réalisation, le dispositif optoélectronique est un écran d'affichage ou un dispositif de projection. Un mode de réalisation vise également un procédé de fabrication d'un dispositif optoélectronique comprenant les étapes suivantes : According to one embodiment, the optoelectronic device is a display screen or a projection device. One embodiment also relates to a method of manufacturing an optoelectronic device comprising the following steps:
a) former, dans un substrat comprenant des première et deuxième faces opposées, des éléments d'isolation électrique latérale s 'étendant de la première face à la deuxième face et délimitant dans le support des premières portions semiconductrices ou conductrices isolées électriquement les unes des autres et former, pour chaque première portion, un premier plot conducteur sur la deuxième face au contact de la première portion ;  a) forming, in a substrate comprising opposite first and second faces, lateral electrical insulation elements extending from the first face to the second face and delimiting in the support of the first semiconductor or conductive portions electrically insulated from each other and forming, for each first portion, a first conductive pad on the second face in contact with the first portion;
b) former, pour chaque première portion, une diode électroluminescente ou un ensemble de diodes électroluminescentes reposant sur la première face et reliées électriquement à la première portion ; et  b) forming, for each first portion, a light-emitting diode or a set of light-emitting diodes resting on the first face and electrically connected to the first portion; and
c) former, pour chaque première portion, une couche d'électrode conductrice et au moins partiellement transparente recouvrant toutes les diodes électroluminescentes, une couche d' encapsulation en un matériau diélectrique au moins partiellement transparent recouvrant la couche d'électrode, et au moins un deuxième plot conducteur relié électriquement à la couche d' électrode .  c) forming, for each first portion, a conductive and at least partially transparent electrode layer covering all the light-emitting diodes, an encapsulation layer of at least partially transparent dielectric material covering the electrode layer, and at least one second conductive pad electrically connected to the electrode layer.
Selon un mode de réalisation, l'étape a) comprend les étapes suivantes :  According to one embodiment, step a) comprises the following steps:
avant l'étape b) , formation, dans le substrat, des éléments d'isolation électrique latérale s 'étendant depuis la première face sur une partie de la profondeur du substrat ; et après l'étape c) , amincissement du substrat pour former la deuxième face et exposer les éléments d' isolation électrique latérale sur la deuxième face.  before step b), forming, in the substrate, lateral electrical insulation elements extending from the first face over a portion of the depth of the substrate; and after step c), thinning the substrate to form the second face and exposing the lateral electrical insulators on the second face.
Selon un mode de réalisation, le procédé comprend, en outre, le dépôt de luminophores sur au moins certaines des diodes électroluminescentes, notamment par des techniques de photolitho¬ graphie ou par impression. According to one embodiment, the method further comprises the deposition of phosphor on at least some light-emitting diodes, in particular by techniques of photolithography or printing ¬ graphy.
Selon un mode de réalisation, chaque diode électroluminescente comprend au moins un élément semiconducteur filaire, conique ou tronconique, intégrant ou recouvert au sommet et/ou au moins sur une partie de ses faces latérales par une coque comprenant au moins une couche active adaptée à fournir la majorité du rayonnement de la diode électroluminescente. According to one embodiment, each light emitting diode comprises at least one semiconductor element wire, conical or frustoconical, incorporating or covered at the top and / or at least on a portion of its lateral faces by a shell comprising at least one active layer adapted to provide the majority of the radiation of the light emitting diode.
Brève description des dessins Brief description of the drawings
Ces caractéristiques et avantages, ainsi que d'autres, seront exposés en détail dans la description suivante de modes de réalisation particuliers faite à titre non limitatif en relation avec les figures jointes parmi lesquelles :  These and other features and advantages will be set forth in detail in the following description of particular embodiments in a non-limiting manner with reference to the accompanying drawings in which:
la figure 1, décrite précédemment, est une vue avec coupe, partielle et schématique, d'un exemple d'un dispositif optoélectronique à diodes électroluminescentes inorganiques ;  FIG. 1, previously described, is a sectional, partial and diagrammatic view of an example of an optoelectronic device with inorganic light-emitting diodes;
les figures 2A à 2C, décrites précédemment, sont des vues avec coupe, partielles et schématiques, de structures obtenues à des étapes successives d'un exemple de procédé de fabrication du dispositif optoélectronique de la figure 1 ;  FIGS. 2A to 2C, previously described, are sectional, partial and schematic views of structures obtained at successive stages of an exemplary method of manufacturing the optoelectronic device of FIG. 1;
les figures 3A, 3B et 3C sont respectivement une vue de dessus, une vue de face avec coupe et une vue de dessous, partielles et schématiques, d'un mode de réalisation d'un dispositif optoélectronique à diodes électroluminescentes ;  FIGS. 3A, 3B and 3C are respectively a top view, a front view with section and a view from below, partial and schematic, of an embodiment of an optoelectronic device with light-emitting diodes;
les figures 4A à 4C sont respectivement une vue de dessus, une vue de face avec coupe et une vue de dessous, partielles et schématiques, d'un autre mode de réalisation d'un dispositif optoélectronique à diodes électroluminescentes ; et les figures 5A et 5B sont respectivement une vue de dessus et une vue de face avec coupe, partielles et schématiques, d'un autre mode de réalisation d'un dispositif optoélectronique à diodes électroluminescentes.  FIGS. 4A to 4C are respectively a top view, a front view with section and a bottom view, partial and schematic, of another embodiment of an optoelectronic device with light-emitting diodes; and FIGS. 5A and 5B are respectively a top view and a sectional front view, partial and schematic, of another embodiment of an optoelectronic light-emitting diode device.
Description détaillée detailed description
Par souci de clarté, de mêmes éléments ont été désignés par de mêmes références aux différentes figures et, de plus, les diverses figures ne sont pas tracées à l'échelle. En outre, seuls les éléments utiles à la compréhension des modes de réalisation ont été représentés et sont décrits. En particulier, le dispositif de commande d'un dispositif optoélectronique à diodes électroluminescentes est connu de l'homme de l'art et n'est pas décrit par la suite. Dans la suite de la description, sauf indication contraire, les termes "sensiblement", "environ" et "de l'ordre de" signifient "à 10 % près". For the sake of clarity, the same elements have been designated by the same references in the various figures and, in addition, the various figures are not drawn to scale. In addition, only the elements useful for understanding the embodiments have been shown and are described. In particular, the control device of an optoelectronic device with diodes electroluminescent is known to those skilled in the art and is not described later. In the rest of the description, unless otherwise indicated, the terms "substantially", "about" and "of the order of" mean "to within 10%".
Les modes de réalisation décrits par la suite concernent des dispositifs optoélectroniques, notamment des écrans d'affi¬ chage ou des dispositifs de projection, comprenant des diodes électroluminescentes formées à partir d' éléments semiconducteurs tridimensionnels, par exemple des microfils, des nanofils, des éléments coniques ou des éléments tronconiques . Dans la suite de la description, des modes de réalisation sont décrits pour des diodes électroluminescentes formées à partir de microfils ou de nanofils. Toutefois, ces modes de réalisation peuvent être mis en oeuvre pour des éléments tridimensionnels autres que des microfils ou des nanofils, par exemple des éléments tridimensionnels en forme de pyramide . The embodiments described hereinafter relate to optoelectronic devices, in particular of affi ¬ drying screens or projection devices, including light emitting diodes formed from three dimensional semiconductor elements, for example micro-wires, nanowires, elements conical or frustoconical elements. In the remainder of the description, embodiments are described for light-emitting diodes formed from microfilts or nanowires. However, these embodiments can be implemented for three-dimensional elements other than microwires or nanowires, for example three-dimensional pyramid-shaped elements.
En outre, dans la suite de la description, des modes de réalisation sont décrits pour des diodes électroluminescentes comprenant chacune une coque qui entoure au moins partiellement le microfil ou le nanofil. Toutefois, ces modes de réalisation peuvent être mis en oeuvre pour des diodes électroluminescentes pour lesquelles la zone active est située dans la hauteur ou au sommet du microfil ou du nanofil.  In addition, in the following description, embodiments are described for light emitting diodes each comprising a shell which at least partially surrounds the microfil or nanowire. However, these embodiments may be implemented for light-emitting diodes for which the active area is located in the height or at the top of the microfilament or nanowire.
Le terme "microfil" ou "nanofil" désigne une structure tridimensionnelle de forme allongée selon une direction privilégiée dont au moins deux dimensions, appelées dimensions mineures, sont comprises entre 5 nm et 2,5 um, de préférence entre 50 nm et 2,5 um, la troisième dimension, appelée dimension majeure, étant au moins égale à 1 fois, de préférence au moins 5 fois et encore plus préférentiellement au moins 10 fois, la plus grande des dimensions mineures. Dans certains modes de réalisation, les dimensions mineures peuvent être inférieures ou égales à environ 1 um, de préférence comprises entre 100 nm et 1 um, plus préférentiellement entre 100 nm et 300 nm. Dans certains modes de réalisation, la hauteur de chaque microfil ou nanofil peut être supérieure ou égale à 500 nm, de préférence comprise entre 1 um et 50 um. The term "microfil" or "nanowire" denotes a three-dimensional structure of elongated shape in a preferred direction, of which at least two dimensions, called minor dimensions, are between 5 nm and 2.5 μm, preferably between 50 nm and 2.5 μm. um, the third dimension, called major dimension, being at least equal to 1 time, preferably at least 5 times and even more preferably at least 10 times, the largest of the minor dimensions. In some embodiments, the minor dimensions may be less than or equal to about 1 μm, preferably between 100 nm and 1 μm, more preferably between 100 nm and 300 nm. In some embodiments, the height of each microfil or nanowire may be greater than or equal to 500 nm, preferably between 1 μm and 50 μm.
Dans la suite de la description, on utilise le terme "fil" pour signifier "microfil ou nanofil". De préférence, la ligne moyenne du fil qui passe par les barycentres des sections droites, dans des plans perpendiculaires à la direction privilégiée du fil, est sensiblement rectiligne et est appelée par la suite "axe" du fil.  In the remainder of the description, the term "wire" is used to mean "microfil or nanowire". Preferably, the average line of the wire which passes through the barycenters of the straight sections, in planes perpendicular to the preferred direction of the wire, is substantially rectilinear and is hereinafter called "axis" of the wire.
Selon un mode de réalisation, il est prévu un dispositif optoélectronique, notamment un écran d'affichage ou un dispositif de projection, comprenant un circuit intégré comportant un substrat, par exemple un substrat conducteur ou semiconducteur, divisé en portions de substrat isolées électriquement les unes des autres et comportant, pour chaque sous-pixel d'affichage, des ensembles de diodes électroluminescentes formées sur la face avant du substrat. Chaque ensemble de diodes électroluminescentes comprend une diode électroluminescente ou plusieurs diodes électroluminescentes montées en parallèle. Par connexion de diodes électroluminescentes en parallèle, on entend que les anodes des diodes électroluminescentes sont connectées ensemble et que les cathodes des diodes électroluminescentes sont connectées ensemble. Chaque ensemble de diodes électroluminescentes élémentaires est équivalent à une diode électroluminescente globale comprenant une anode et une cathode.  According to one embodiment, an optoelectronic device is provided, in particular a display screen or a projection device, comprising an integrated circuit comprising a substrate, for example a conductive or semiconductor substrate, divided into electrically isolated portions of the substrate. others and comprising, for each display subpixel, sets of light-emitting diodes formed on the front face of the substrate. Each set of light-emitting diodes comprises a light-emitting diode or a plurality of light-emitting diodes connected in parallel. By connecting light-emitting diodes in parallel, it is meant that the anodes of the light-emitting diodes are connected together and that the cathodes of the light-emitting diodes are connected together. Each set of elementary light-emitting diodes is equivalent to a global light-emitting diode comprising an anode and a cathode.
Les figures 3A à 3C représentent un mode de réalisation d'un dispositif optoélectronique 40, notamment un écran d'affichage ou un dispositif de projection, comprenant :  FIGS. 3A to 3C show an embodiment of an optoelectronic device 40, in particular a display screen or a projection device, comprising:
- un substrat conducteur ou semiconducteur 42 comprenant une face inférieure 44 et une face supérieure 46 opposée, la face supérieure 46 étant de préférence plane au moins au niveau des ensembles de diodes électroluminescentes ;  a conductive or semiconductor substrate 42 comprising a lower face 44 and an opposite upper face 46, the upper face 46 preferably being flat at least at the level of the light-emitting diode assemblies;
- des éléments 48 d'isolation électrique qui s'étendent dans le substrat 42 entre les faces 44 et 46 et qui divisent le substrat 42 en portions 50 conductrices ou semiconductrices ; - des plots conducteurs 52 au contact de la face inférieure 44, chaque portion 50 étant au contact de l'un des plots conducteurs 52 ; electrical isolation elements 48 which extend in the substrate 42 between the faces 44 and 46 and which divide the substrate 42 into conductive or semiconducting portions 50; conductive pads 52 in contact with the lower face 44, each portion 50 being in contact with one of the conductive pads 52;
- des plots de germination 54 favorisant la croissance de fils, chaque plot de germination 54 étant au contact de la face germination pads 54 promoting the growth of threads, each germination stud 54 being in contact with the face
46 sur l'une des portions 50 conductrices ou semiconductrices ; 46 on one of the conductive or semiconducting portions 50;
- des fils 56, chaque fil 56 étant en contact avec l'un des plots de germination 54, chaque fil 56 comprenant une portion inférieure 58, en contact avec le plot de germination 54 et une portion supérieure 60, prolongeant la portion inférieure 58 ;  - son 56, each wire 56 being in contact with one of the seed pads 54, each wire 56 comprising a lower portion 58 in contact with the seed pad 54 and an upper portion 60, extending the lower portion 58;
- une couche isolante 62 s 'étendant sur la face 46 du substrat 42 et s 'étendant sur les flancs latéraux de la portion inférieure 58 de chaque fil 56 ;  an insulating layer 62 extending on the face 46 of the substrate 42 and extending on the lateral flanks of the lower portion 58 of each wire 56;
- une coque 64 comprenant un empilement de couches semiconductrices recouvrant la portion supérieure 60 de chaque fil 56 ;  a shell 64 comprising a stack of semiconductor layers covering the upper portion 60 of each wire 56;
- une couche 66 conductrice et au moins partiellement transparente formant une électrode recouvrant chaque coque 64, et s 'étendant sur la couche isolante 62 entre les fils 56 ;  a conductive and at least partially transparent layer 66 forming an electrode covering each shell 64, and extending on the insulating layer 62 between the wires 56;
- une couche conductrice 68 recouvrant la couche d'électrode 66 entre les fils 56 mais ne s 'étendant pas sur les fils 56, la couche conductrice 68 étant, en outre, au contact de l'une des portions semiconductrices 50 au travers d'une ouverture a conductive layer 68 covering the electrode layer 66 between the wires 56 but not extending on the wires 56, the conductive layer 68 being, in addition, in contact with one of the semiconductor portions 50 through an opening
69 prévue dans la couche d'électrode 66 et dans la couche isolante 62 ; et 69 provided in the electrode layer 66 and in the insulating layer 62; and
- une couche d' encapsulâtion 70 transparente recouvrant l'ensemble de la structure.  a transparent encapsulation layer 70 covering the entire structure.
Le dispositif optoélectronique 40 peut, en outre, comprendre une couche de luminophores, non représentée, et/ou des filtres colorés, non représentés, dans la couche d' encapsulation The optoelectronic device 40 may, in addition, comprise a phosphor layer, not shown, and / or colored filters, not shown, in the encapsulation layer.
70 ou sur la couche d' encapsulation 70. Selon un mode de réalisation, des luminophores sont notamment répartis entre les fils 56. Chaque fil 56 et la coque 64 associée constituent une diode électroluminescente élémentaire. Les diodes électro¬ luminescentes élémentaires situées sur une même portion semiconductrice 50 forment un ensemble D de diodes électro- luminescentes. Chaque ensemble D comprend donc plusieurs diodes électroluminescentes élémentaires connectées en parallèle. Le nombre de diodes électroluminescentes élémentaires par ensemble D peut varier de 1 à plusieurs milliers, typiquement de 25 à 100. Le nombre de diodes électroluminescentes élémentaires par ensemble D peut varier d'un ensemble à l'autre. 70 or on the encapsulation layer 70. According to one embodiment, luminophores are distributed among the wires 56. Each wire 56 and the shell 64 associated constitute an elementary light emitting diode. Diodes electro ¬ elementary luminescent located on the same semiconductor portion 50 form a set D of light emitting diodes. Each set D thus comprises several elementary light-emitting diodes connected in parallel. The number of elementary light-emitting diodes per set D can vary from 1 to several thousand, typically from 25 to 100. The number of elementary light-emitting diodes per set D can vary from one set to another.
Chaque sous-pixel d'affichage Pix du dispositif optoélectronique 40 comprend l'une des portions 50 conductrices ou semiconductrices et l'ensemble D de diodes électroluminescentes reposant sur cette portion 50. En figure 3A, on a représenté de façon schématique la séparation entre les sous-pixels d'affichage Pix par des lignes en traits pointillés 72. Selon un mode de réalisation, la surface occupée par chaque sous-pixel Pix en vue de dessus peut varier de 3 um par 3 um à plusieurs rnrn^ et typiquement de 10 à 100 um^ .  Each pixel display pixel Pix of the optoelectronic device 40 comprises one of the conductive or semiconducting portions 50 and the set D of light-emitting diodes resting on this portion 50. In Figure 3A, there is shown schematically the separation between the Pixel subpixels with dashed lines 72. According to one embodiment, the area occupied by each pixel Pix in a view from above can vary from 3 μm by 3 μm to several nm and typically from 10 μm to 10 μm. at 100 μm.
Chaque diode électroluminescente élémentaire est formée d'une coque recouvrant au moins partiellement un fil. La surface développée des couches actives des diodes électroluminescentes élémentaires d'un ensemble D est supérieure à la surface du sous- pixel d'affichage comprenant cet ensemble D. L'intensité maximale lumineuse pouvant être fournie par le sous-pixel d'affichage peut donc être supérieure à celle d'un sous-pixel d'affichage réalisé avec une technologie de diode électroluminescente inorganique bidimensionnelle .  Each elemental light-emitting diode is formed of a shell at least partially covering a wire. The developed surface of the active layers of the elementary light-emitting diodes of a set D is greater than the surface of the sub-display pixel comprising this set D. The maximum light intensity that can be provided by the sub-display pixel can therefore be to be greater than that of a display subpixel made with a two-dimensional inorganic light emitting diode technology.
Selon un mode de réalisation, le substrat 42 correspond à un substrat semiconducteur monolithique. Le substrat 42 semiconducteur est, par exemple, un substrat en silicium, en germanium, ou en un composé III-V tel que du GaAs. De préférence, le substrat 42 est un substrat de silicium monocristallin.  According to one embodiment, the substrate 42 corresponds to a monolithic semiconductor substrate. The semiconductor substrate 42 is, for example, a substrate made of silicon, germanium, or a III-V compound such as GaAs. Preferably, the substrate 42 is a monocrystalline silicon substrate.
De préférence, le substrat semiconducteur 42 est dopé de façon à baisser la résistivité électrique jusqu'à une résistivité proche de celle des métaux, de préférence inférieure à quelques mohm.cm. Le substrat 42 est de préférence un substrat semiconducteur fortement dopé avec une concentration de dopants comprise entre 5*10^^ atomes/cm-^ et 2*10^0 atomes/cm-^, de préférence entre 1*10^^ atomes/cm-^ et 2*10^0 atomes/cm-^, par exemple 5* ÎO-^ atomes/cm-^. Au début du procédé de fabrication du dispositif optoélectronique, le substrat 42 a une épaisseur comprise entre 275 um et 1500 um, de préférence 725 um. Une fois que le dispositif optoélectronique est réalisé, après une étape d'amincissement décrite plus en détail par la suite, le substrat 42 a une épaisseur comprise entre 1 um et 100 um. Dans le cas d'un substrat 42 de silicium, des exemples de dopants de type P sont le bore (B) ou l'indium (In) et des exemples de dopants de type N sont le phosphore (P) , l'arsenic (As), ou l'antimoine (Sb) . De préférence, le substrat 42 est dopé de type N au phosphore. La face 44 du substrat 42 de silicium peut être une face (100) . Preferably, the semiconductor substrate 42 is doped so as to lower the electrical resistivity to a resistivity close to that of metals, preferably less than a few mohm.cm. The substrate 42 is preferably a highly doped semiconductor substrate with a dopant concentration of between 5 * 10 ^^ atoms / cm ^ and 2 * 10 ^ 0 atoms / cm ^, preferably between 1 * 10 ^^ atoms / and 2 * 10 ^ 0 atoms / cm 2, for example 5 * 10 -3 atoms / cm 2. At the beginning of the manufacturing process of the optoelectronic device, the substrate 42 has a thickness of between 275 μm and 1500 μm, preferably 725 μm. Once the optoelectronic device is made, after a thinning step described in more detail below, the substrate 42 has a thickness of between 1 μm and 100 μm. In the case of a silicon substrate 42, examples of P type dopants are boron (B) or indium (In) and examples of N type dopants are phosphorus (P), arsenic ( As), or antimony (Sb). Preferably, the substrate 42 is N-doped with phosphorus. The face 44 of the silicon substrate 42 may be a face (100).
Les plots de germination 54, appelés également îlots de germination, sont en un matériau favorisant la croissance des fils 56. Un traitement peut être prévu pour protéger les flancs latéraux des plots de germination et la surface des parties du substrat non recouvertes par les plots de germination pour empêcher la croissance des fils sur les flancs latéraux des plots de germination et sur la surface des parties du substrat non recouvertes par les plots de germination. Le traitement peut comprendre la formation d'une région diélectrique sur les flancs latéraux des plots de germination et s 'étendant sur et/ou dans le substrat et reliant, pour chaque paire de plots, l'un des plots de la paire à l'autre plot de la paire, les fils ne croissant pas sur la région diélectrique. Ladite région diélectrique peut déborder au-dessus des plots de germination 54. A titre de variante, les plots de germination 54 peuvent être remplacés par une couche de germination recouvrant la face 46 du substrat 42. Une région diélectrique peut alors être formée au-dessus de la couche de germination pour empêcher la croissance de fils dans les emplacements non voulus. A titre d'exemple, le matériau composant les plots de germination 54 peut être un métal de transition de la colonne IV, V ou VI du tableau périodique des éléments ou un nitrure, un carbure ou un borure d'un métal de transition de la colonne IV, V ou VI du tableau périodique des éléments ou une combinaison de ces composés . The germination pads 54, also called germination islands, are made of a material that promotes the growth of the yarns 56. A treatment can be provided to protect the lateral flanks of the seedlings and the surface of the parts of the substrate that are not covered by the bumps. germination to prevent growth of the yarns on the lateral flanks of the seed pads and on the surface of the parts of the substrate not covered by the seed pads. The treatment may comprise forming a dielectric region on the lateral flanks of the seed pads and extending on and / or in the substrate and connecting, for each pair of pads, one of the pads of the pair to the other stud of the pair, the wires not growing on the dielectric region. Said dielectric region can overflow over the seed pads 54. Alternatively, the seed pads 54 can be replaced by a seed layer covering the face 46 of the substrate 42. A dielectric region can then be formed above of the seed layer to prevent growth of threads in unwanted locations. By way of example, the material constituting the seed pads 54 may be a transition metal of column IV, V or VI of the periodic table of the elements or a nitride, a carbide or a boride of a transition metal of the column IV, V or VI of the periodic table of elements or a combination of these compounds.
A titre d'exemple, les plots de germination 54 peuvent être en nitrure d'aluminium (AIN), en bore (B) , en nitrure de bore (BN) , en titane (Ti) , en nitrure de titane (TiN) , en tantale (Ta) , en nitrure de tantale (TaN) , en hafnium (Hf) , en nitrure d'hafnium (HfN) , en niobium (Nb) , en nitrure de niobium (NbN) , en zirconium (Zr) , en borate de zirconium (ZrB2), en nitrure de zirconium (ZrN) , en carbure de silicium (SiC) , en nitrure et carbure de tantale (TaCN) , en nitrure de magnésium sous la forme MgxNy, où x est environ égal à 3 et y est environ égal à 2, par exemple du nitrure de magnésium selon la forme ¾Ν2 ou du nitrure de gallium et de magnésium (MgGaN) , en tungstène (W) , en nitrure de tungstène (WN) ou en une combinaison de ceux-ci . By way of example, the seed pads 54 may be made of aluminum nitride (AIN), boron (B), boron nitride (BN), titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), hafnium (Hf), hafnium nitride (HfN), niobium (Nb), niobium nitride (NbN), zirconium (Zr), zirconium borate (ZrB 2), of zirconium nitride (ZrN), silicon carbide (SiC), nitride and tantalum carbide (TaCN), magnesium nitride in the form Mg x Ny, where x is approximately equal to 3 and y is approximately equal to 2, for example magnesium nitride according to the form ¾Ν2 or gallium and magnesium nitride (MgGaN), tungsten (W), tungsten nitride (WN) or a combination of those -this .
La couche isolante 62 peut être en un matériau diélectrique, par exemple en oxyde de silicium (S1O2) f en nitrure de silicium (SixNy, où x est environ égal à 3 et y est environ égal à 4, par exemple du S13N4), en oxynitrure de silicium (SiOxNy où x peut être environ égal à 1/2 et y peut être environ égal à 1, par exemple du S12ON2) , en oxyde d'aluminium (AI2O3) , en oxyde d'hafnium (HfC>2) ou en diamant. A titre d'exemple, l'épaisseur de la couche isolante 62 est comprise entre 5 nm et 800 nm, par exemple égale à environ 30 nm. The insulating layer 62 may be a dielectric material, such as silicon oxide (S1O2) f silicon nitride (Si x N y, where x is approximately equal to 3 and y is equal to about 4, e.g., S13N4) , in silicon oxynitride (SiO x Ny where x may be about 1/2 and y may be about 1, eg S12ON2), aluminum oxide (Al2O3), hafnium oxide (HfC > 2) or diamond. For example, the thickness of the insulating layer 62 is between 5 nm and 800 nm, for example equal to about 30 nm.
Les fils 56 sont, au moins en partie, formés à partir d'au moins un matériau semiconducteur. Le matériau semiconducteur peut être du silicium, du germanium, du carbure de silicium, un composé III-V, un composé II-VI ou une combinaison de ces composés .  The wires 56 are at least partly formed from at least one semiconductor material. The semiconductor material may be silicon, germanium, silicon carbide, a III-V compound, a II-VI compound or a combination thereof.
Les fils 56 peuvent être, au moins en partie, formés à partir de matériaux semiconducteurs comportant ma oritairement un composé III-V, par exemple des composés III-N. Des exemples d'éléments du groupe III comprennent le gallium (Ga) , l'indium (In) ou l'aluminium (Al) . Des exemples de composés III-N sont GaN, AIN, InN, InGaN, AlGaN ou AlInGaN. D'autres éléments du groupe V peuvent également être utilisés, par exemple, le phosphore ou l'arsenic. De façon générale, les éléments dans le composé III-V peuvent être combinés avec différentes fractions molaires. The wires 56 may be, at least in part, formed from semiconducting materials, typically having a III-V compound, for example III-N compounds. Examples Group III elements include gallium (Ga), indium (In) or aluminum (Al). Examples of III-N compounds are GaN, AlN, InN, InGaN, AlGaN or AlInGaN. Other group V elements may also be used, for example, phosphorus or arsenic. In general, the elements in compound III-V can be combined with different mole fractions.
Les fils 56 peuvent être, au moins en partie, formés à partir de matériaux semiconducteurs comportant ma oritairement un composé II-VI. Des exemples d'éléments du groupe II comprennent des éléments du groupe IIA, notamment le béryllium (Be) et le magnésium (Mg) et des éléments du groupe IIB, notamment le zinc (Zn) et le cadmium (Cd) . Des exemples d'éléments du groupe VI comprennent des éléments du groupe VIA, notamment l'oxygène (0) et le tellure (Te) . Des exemples de composés II-VI sont ZnO, ZnMgO, CdZnO ou CdZnMgO. De façon générale, les éléments dans le composé II-VI peuvent être combinés avec différentes fractions molaires .  The wires 56 may be, at least in part, formed from semiconductor materials having a compound II-VI. Examples of Group II elements include Group IIA elements, including beryllium (Be) and magnesium (Mg) and Group IIB elements, including zinc (Zn) and cadmium (Cd). Examples of Group VI elements include elements of the VIA group, including oxygen (O) and tellurium (Te). Examples of compounds II-VI are ZnO, ZnMgO, CdZnO or CdZnMgO. In general, the elements in II-VI can be combined with different mole fractions.
Les fils 56 peuvent comprendre un dopant. A titre d'exemple, pour des composés III-V, le dopant peut être choisi parmi le groupe comprenant un dopant de type P du groupe II, par exemple, du magnésium (Mg) , du zinc (Zn) , du cadmium (Cd) ou du mercure (Hg) , un dopant du type P du groupe IV, par exemple du carbone (C) ou un dopant de type N du groupe IV, par exemple du silicium (Si) , du germanium (Ge) , du sélénium (Se) , du souffre (S), du terbium (Tb) ou de l'étain (Sn) .  The wires 56 may comprise a dopant. By way of example, for compounds III-V, the dopant may be chosen from the group comprising a group II P dopant, for example magnesium (Mg), zinc (Zn), cadmium (Cd ) or mercury (Hg), a group IV P-type dopant, for example carbon (C) or a group IV N-type dopant, for example silicon (Si), germanium (Ge), selenium (Se), sulfur (S), terbium (Tb) or tin (Sn).
La section droite des fils 56 peut avoir différentes formes, telles que, par exemple, une forme ovale, circulaire ou polygonale, notamment triangulaire, rectangulaire, carrée ou hexagonale. A titre d'exemple, en figure 3A, les fils sont représentés avec une section droite hexagonale. Ainsi, on comprend que, quand on mentionne ici le "diamètre" dans une section droite d'un fil ou d'une couche déposée sur ce fil, il s'agit d'une grandeur associée à la surface de la structure visée dans cette section droite, correspondant, par exemple, au diamètre du disque ayant la même surface que la section droite du fil. Le diamètre moyen de chaque fil 56 peut être compris entre 50 nm et 5 um. La hauteur de chaque fil 56 peut être comprise entre 250 nm et 50 um. Chaque fil 56 peut avoir une structure semiconductrice allongée selon un axe sensiblement perpendiculaire à la face 46. Chaque fil 56 peut avoir une forme générale cylindrique. Les axes de deux fils 56 adjacents peuvent être distants de 0,5 um à 10 um et de préférence de 1,5 um à 5 um. A titre d'exemple, les fils 56 peuvent être régulièrement répartis, notamment selon un réseau hexagonal. The cross section of the yarns 56 may have different shapes, such as, for example, an oval, circular or polygonal shape, in particular triangular, rectangular, square or hexagonal. By way of example, in FIG. 3A, the wires are represented with a hexagonal cross-section. Thus, it is understood that when the "diameter" in a cross-section of a wire or a layer deposited on this wire is mentioned here, it is a quantity associated with the surface of the structure referred to in this section. cross section, corresponding, for example, to the diameter of the disk having the same surface as the cross section of the wire. The diameter average of each wire 56 may be between 50 nm and 5 um. The height of each wire 56 may be between 250 nm and 50 μm. Each wire 56 may have an elongate semiconductor structure along an axis substantially perpendicular to the face 46. Each wire 56 may have a generally cylindrical shape. The axes of two adjacent yarns 56 may be spaced from 0.5 μm to 10 μm and preferably from 1.5 μm to 5 μm. By way of example, the wires 56 may be regularly distributed, in particular along a hexagonal network.
A titre d'exemple, la portion inférieure 58 de chaque fil 56 est ma oritairement constituée du composé III-N, par exemple du nitrure de gallium, dopé du même type que le substrat 42, par exemple de type N, par exemple au silicium. La portion inférieure 58 s'étend sur une hauteur qui peut être comprise entre 100 nm et 25 um.  By way of example, the lower portion 58 of each wire 56 is preferably composed of the compound III-N, for example doped gallium nitride of the same type as the substrate 42, for example N-type, for example silicon . The lower portion 58 extends over a height which may be between 100 nm and 25 μm.
A titre d'exemple, la portion supérieure 60 de chaque fil 56 est au moins partiellement réalisée dans un composé III-N, par exemple du GaN. La portion supérieure 60 peut être dopée de type N, éventuellement moins fortement dopée que la portion inférieure 58 ou ne pas être intentionnellement dopée. La portion supérieure 60 s'étend sur une hauteur qui peut être comprise entre By way of example, the upper portion 60 of each wire 56 is at least partially made of a III-N compound, for example GaN. The upper portion 60 may be N-type doped, possibly less strongly doped than the lower portion 58 or not be intentionally doped. The upper portion 60 extends over a height that can be between
100 nm et 25 um. 100 nm and 25 μm.
La coque 64 peut comprendre un empilement de plusieurs couches comprenant notamment :  The shell 64 may comprise a stack of several layers including:
- une couche active recouvrant la portion supérieure 60 du fil 56 associé ;  an active layer covering the upper portion 60 of the associated wire 56;
- une couche intermédiaire de type de conductivité opposé à la portion inférieure 58 et recouvrant la couche active ; et  an intermediate layer of conductivity type opposite to the lower portion 58 and covering the active layer; and
- une couche de liaison recouvrant la couche inter- médiaire et recouverte par l'électrode 66.  a bonding layer covering the intermediate layer and covered by the electrode 66.
La couche active est la couche depuis laquelle est émise la majorité du rayonnement fourni par la diode électroluminescente élémentaire. Selon un exemple, la couche active peut comporter des moyens de confinement des porteurs de charge électrique, tels que des puits quantiques multiples. Elle est, par exemple, constituée d'une alternance de couches de GaN et de InGaN ayant des épaisseurs respectives de 5 à 20 nm (par exemple 8 nm) et de 1 à 15 nm (par exemple 2,5 nm) . Les couches de GaN peuvent être dopées, par exemple de type N ou P. Selon un autre exemple, la couche active peut comprendre une seule couche d' InGaN, par exemple d'épaisseur supérieure à 10 nm. The active layer is the layer from which the majority of the radiation provided by the elementary light emitting diode is emitted. In one example, the active layer may include means for confining electric charge carriers, such as multiple quantum wells. She is, for example, consisting of an alternation of GaN and InGaN layers having respective thicknesses of 5 to 20 nm (for example 8 nm) and 1 to 15 nm (for example 2.5 nm). The GaN layers may be doped, for example of the N or P type. According to another example, the active layer may comprise a single layer of InGaN, for example with a thickness greater than 10 nm.
La couche intermédiaire, par exemple dopée de type P, peut correspondre à une couche semiconductrice ou à un empilement de couches semiconductrices et permet la formation d'une jonction P-N ou P-I-N, la couche active étant comprise entre la couche intermédiaire de type P et la portion supérieure 60 de type N de la jonction P-N ou P-I-N.  The intermediate layer, for example doped P-type, may correspond to a semiconductor layer or a stack of semiconductor layers and allows the formation of a PN or PIN junction, the active layer being between the intermediate layer of type P and the N-type upper portion 60 of the PN or PIN junction.
La couche de liaison peut correspondre à une couche semiconductrice ou à un empilement de couches semiconductrices et permet la formation d'un contact ohmique entre la couche intermédiaire et l'électrode 66. A titre d'exemple, la couche de liaison peut être dopée très fortement du type opposé à la portion inférieure 58 de chaque fil 56, jusqu'à dégénérer la ou les couches semiconductrices, par exemple dopée de type P à une concentration supérieure ou égale à 10^0 atomes/cm-^.  The bonding layer may correspond to a semiconductor layer or a stack of semiconductor layers and allows the formation of an ohmic contact between the intermediate layer and the electrode 66. By way of example, the bonding layer may be doped very thinly. strongly of the type opposite to the lower portion 58 of each wire 56, until degenerate the semiconductor layer or layers, for example doped P type at a concentration greater than or equal to 10 ^ 0 atoms / cm- ^.
L'empilement de couches semiconductrices peut comprendre une couche de blocage d'électrons formée d'un alliage ternaire, par exemple en nitrure de gallium et d'aluminium (AlGaN) ou en nitrure d' indium et d'aluminium (AlInN) en contact avec la couche active et la couche intermédiaire, pour assurer une bonne répartition des porteurs électriques dans la couche active.  The semiconductor layer stack may comprise an electron blocking layer formed of a ternary alloy, for example gallium aluminum nitride (AlGaN) or indium aluminum nitride (AlInN) in contact with each other. with the active layer and the intermediate layer, to ensure a good distribution of the electric carriers in the active layer.
L'électrode 66 est adaptée à polariser la couche active de chaque fil 56 et à laisser passer le rayonnement électromagnétique émis par les diodes électroluminescentes. Le matériau formant l'électrode 66 peut être un matériau transparent et conducteur tel que de l'oxyde d' indium-étain (ou ITO, acronyme anglais pour Indium Tin Oxide) , de l'oxyde de zinc dopé à l'aluminium, au gallium ou à l' indium, ou du graphène. A titre d'exemple, la couche d'électrode 66 a une épaisseur comprise entre 5 nm et 200 nm, de préférence entre 20 nm et 50 nm. La couche conductrice 68 correspond, de préférence à une couche métallique, par exemple en aluminium, en cuivre, en or, en ruthénium ou en argent, ou à un empilement de couches métalliques, par exemple en titane-aluminium, en silicium-aluminium, en titane- nickel-argent, en cuivre ou en zinc. A titre d'exemple, la couche conductrice 68 a une épaisseur comprise entre 20 nm et 1500 nm, de préférence entre 400 nm et 800 nm. La couche conductrice 68 n'est présente qu'entre les fils et ne recouvre pas la surface émissive de ces derniers. La couche conductrice 68 permet de réduire les pertes résistives lors de la circulation du courant. Elle a également un rôle de réflecteur pour renvoyer vers l'extérieur les rayons émis par les diodes électroluminescentes dans la direction du substrat. The electrode 66 is adapted to polarize the active layer of each wire 56 and to let the electromagnetic radiation emitted by the light-emitting diodes. The material forming the electrode 66 may be a transparent and conductive material such as indium tin oxide (ITO), zinc oxide doped with aluminum, gallium or indium, or graphene. By way of example, the electrode layer 66 has a thickness of between 5 nm and 200 nm, preferably between 20 nm and 50 nm. The conductive layer 68 preferably corresponds to a metal layer, for example aluminum, copper, gold, ruthenium or silver, or to a stack of metal layers, for example titanium-aluminum, silicon-aluminum, titanium-nickel-silver, copper or zinc. By way of example, the conductive layer 68 has a thickness of between 20 nm and 1500 nm, preferably between 400 nm and 800 nm. The conductive layer 68 is present only between the son and does not cover the emissive surface thereof. The conductive layer 68 makes it possible to reduce the resistive losses during the flow of the current. It also has a reflector role to send out the rays emitted by the light-emitting diodes in the direction of the substrate.
La couche d' encapsulation 70 est réalisée en un matériau isolant au moins partiellement transparent. L'épaisseur minimale de la couche d' encapsulation 70 est comprise entre 250 nm et 50 ym de sorte que la couche d' encapsulation 70 recouvre complètement la couche d'électrode 66 au sommet des ensembles D de diodes électroluminescentes. La couche d' encapsulation 70 peut être réalisée en un matériau inorganique au moins partiellement transparent. A titre d'exemple, le matériau inorganique est choisi parmi le groupe comprenant les oxydes de silicium du type SiOx où x est un nombre réel compris entre 1 et 2 ou SiOyNz où y et z sont des nombres réels compris entre 0 et 1 et les oxydes d'aluminium, par exemple AI2O3. La couche d' encapsulation 70 peut être réalisée en un matériau organique au moins partiellement transparent. A titre d'exemple, la couche d' encapsulation 70 est un polymère silicone, un polymère époxyde, un polymère acrylique ou un polycarbonate . The encapsulation layer 70 is made of at least partially transparent insulating material. The minimum thickness of the encapsulation layer 70 is between 250 nm and 50 μm so that the encapsulation layer 70 completely covers the electrode layer 66 at the top of the sets D of light emitting diodes. The encapsulation layer 70 may be made of at least partially transparent inorganic material. By way of example, the inorganic material is chosen from the group comprising silicon oxides of the SiO x type where x is a real number between 1 and 2 or SiOyN z where y and z are real numbers between 0 and 1 and aluminum oxides, for example Al2O3. The encapsulation layer 70 may be made of at least partially transparent organic material. By way of example, the encapsulation layer 70 is a silicone polymer, an epoxy polymer, an acrylic polymer or a polycarbonate.
Les éléments d'isolation électrique 48 peuvent comprendre des tranchées s' étendant sur toute l'épaisseur du substrat 42 et remplies d'un matériau isolant, par exemple un oxyde, notamment de l'oxyde de silicium, ou un polymère isolant. A titre de variante, les parois de chaque tranchée 48 sont recouvertes d'une couche isolante, le reste de la tranchée étant remplie d'un matériau semiconducteur ou conducteur, par exemple du silicium polycristallin. Selon une autre variante, les éléments d'isolation électrique 48 comprennent des régions dopées d'un type de polarité opposé au substrat 42 et s 'étendant sur toute la profondeur du substrat 42. A titre d'exemple, chaque tranchée 48 a une largeur supérieure à 1 um, qui varie notamment de 1 um à 10 um, par exemple d'environ 2 um. La distance entre les deux tranchées 48 d'une paire de tranchées 48 adjacentes est supérieure à 5 um, par exemple d'environ 6 um. Sur les figures 3B et 3C, les éléments d'isolation électrique 48 comprennent des paires de tranchées adjacentes 48 qui délimitent les portions 50 du substrat 42. A titre d'exemple, une seule tranchée 48 peut être prévue pour isoler électriquement chaque portion 50. The electrical insulation elements 48 may comprise trenches extending over the entire thickness of the substrate 42 and filled with an insulating material, for example an oxide, in particular silicon oxide, or an insulating polymer. Alternatively, the walls of each trench 48 are covered with an insulating layer, the remainder of the trench being filled with a semiconductor or conductive material, for example polycrystalline silicon. According to another variant, the electrical insulation elements 48 comprise doped regions of a type of polarity opposite to the substrate 42 and extending over the entire depth of the substrate 42. For example, each trench 48 has a width greater than 1 μm, which varies in particular from 1 μm to 10 μm, for example about 2 μm. The distance between the two trenches 48 of a pair of adjacent trenches 48 is greater than 5 μm, for example about 6 μm. In FIGS. 3B and 3C, the electrical insulation elements 48 comprise pairs of adjacent trenches 48 which delimit the portions 50 of the substrate 42. By way of example, a single trench 48 may be provided to electrically isolate each portion 50.
En général des tranchées si fines ne peuvent être réalisées qu'avec une profondeur limitée, entre une dizaine de micromètres et une centaine de micromètres suivant la technique de gravure et d'isolation choisie. Aussi convient-il d'amincir le substrat 42 jusqu'à l'affleurement des éléments d'isolation électrique 48.  In general, trenches so fine can be made with a limited depth, between ten micrometers and a hundred micrometers according to the chosen etching and insulation technique. It is therefore advisable to thin the substrate 42 until the electrical insulation elements 48 are flush.
Pour ce faire, une poignée en un matériau rigide peut être fixée temporairement ou définitivement à la couche d' encapsulâtion 70. Dans le cas où la poignée est fixée définitivement à la couche d' encapsulation 70, la poignée est en un matériau au moins partiellement transparent. Il peut s'agir de verre, notamment un verre borosilicate, par exemple le verre connu sous l'appellation pyrex, ou de saphir. Après amincissement la face arrière 44 du substrat peut être traitée, puis si le collage est temporaire, la poignée peut être décollée.  To do this, a handle made of a rigid material can be fixed temporarily or permanently to the encapsulation layer 70. In the case where the handle is permanently fixed to the encapsulation layer 70, the handle is made of a material at least partially transparent. It may be glass, especially a borosilicate glass, for example glass known under the name pyrex, or sapphire. After thinning the rear face 44 of the substrate can be treated, and if the gluing is temporary, the handle can be peeled off.
Chaque plot conducteur 52 peut correspondre à une couche ou à un empilement de couches recouvrant la face 44. A titre de variante, une couche isolante peut recouvrir partiellement la face 44, chaque plot conducteur 52 étant au contact de la portion semiconductrice 50 associée au travers d'ouvertures gravées dans cette couche isolante. Dans le présent mode de réalisation, le dispositif optoélectronique 40 est fixé à un autre circuit par des éléments conducteurs fusibles, non représentés, par exemple des billes de soudure ou des billes d'indium fixées aux plots conducteurs 52. L'assemblage du dispositif optoélectronique 40 sur un autre circuit, notamment sur un circuit de commande, se fait au moyen de techniques conventionnelles d'hybridation matricielle, au moyen de billes fusibles, par exemple en indium, ou en SnAg, ou de colonnes de cuivre ou de plots d'or (technologie Stud Bump) ou par collage moléculaire conducteur (cuivre sur cuivre) . L'empilement métallique formant les plots conducteurs 52 est choisi de manière à être compatible avec la technologie d'assemblage choisie. A titre d'exemple, les plots conducteurs 52 peuvent être en Cu ou Ti-Ni-Au, Sn-Ag ou Ni-Pd-Au. Each conductive pad 52 may correspond to a layer or a stack of layers covering the face 44. As a variant, an insulating layer may partially cover the face 44, each conductive pad 52 being in contact with the associated semiconducting portion 50 openings etched in this insulating layer. In the present embodiment, the optoelectronic device 40 is fixed to another circuit by fusible conductive elements, not shown, for example solder balls or indium balls fixed to the conductive pads 52. The assembly of the optoelectronic device 40 on another circuit, in particular on a control circuit, is done by means of conventional techniques of matrix hybridization, by means of fusible balls, for example indium, or SnAg, or copper columns or studs. gold (Stud Bump technology) or conductive molecular bonding (copper on copper). The metal stack forming the conductive pads 52 is chosen to be compatible with the chosen assembly technology. For example, conductive pads 52 may be Cu or Ti-Ni-Au, Sn-Ag or Ni-Pd-Au.
La couche active de la coque 64 des diodes électroluminescentes élémentaires d'au moins l'un des ensembles de diodes électroluminescentes D peut être fabriquée de manière différente de la couche active de la coque des diodes électroluminescentes élémentaires d'au moins un autre ensemble de diodes électroluminescentes. Par exemple, la couche active de la coque 64 d'un premier ensemble peut être adaptée pour émettre une lumière à une première longueur d'onde, par exemple une lumière bleue et la couche active de la coque 64 d'un deuxième ensemble peut être adaptée pour émettre une lumière à une deuxième longueur d'onde différente de la première longueur d'onde, par exemple une lumière verte. Ceci peut être obtenu, par exemple, en adaptant dans chaque ensemble le pas et la taille des fils, ce qui a pour conséquence de modifier l'épaisseur et la composition des puits quantiques composant ces couches actives.  The active layer of the shell 64 of the elementary light-emitting diodes of at least one of the sets of light-emitting diodes D may be manufactured differently from the active layer of the shell of the elementary light-emitting diodes of at least one other set of diodes. emitting. For example, the active layer of the shell 64 of a first set may be adapted to emit light at a first wavelength, for example a blue light, and the active layer of the shell 64 of a second set may be adapted to emit light at a second wavelength different from the first wavelength, for example a green light. This can be achieved, for example, by adapting in each set the pitch and size of the son, which has the effect of modifying the thickness and the composition of the quantum wells composing these active layers.
De plus, un troisième ensemble peut être adapté pour émettre une lumière à une troisième longueur d'onde différente des première et deuxième longueurs d'onde, par exemple une lumière rouge. Ainsi la composition des lumières bleue, verte, et rouge peut être choisie pour qu'un observateur perçoive une lumière blanche par composition des couleurs, chaque diode, ou ensemble de diodes, émettant à une première, deuxième et troisième longueur d'onde pouvant être adressée indépendamment des autres afin d'ajuster la couleur. In addition, a third set may be adapted to emit light at a third wavelength different from the first and second wavelengths, for example a red light. Thus the composition of the blue, green, and red lights can be chosen so that an observer perceives a white light by composition of the colors, each diode, or together of diodes, emitting at a first, second and third wavelength that can be addressed independently of others to adjust the color.
Selon un autre mode de réalisation, un luminophore est déposé entre et sur des diodes électroluminescentes d'un sous pixel. Le luminophore peut absorber la lumière bleue profond émise par les diodes électroluminescentes et la transformer en vert ou en rouge, voire en bleu. L'avantage d'utiliser un luminophore bleu et non l'émission naturelle des diodes électroluminescentes est une insensibilité de la qualité du bleu aux variations de couleur de l'émission spontanée des fils, d'un lot à l'autre ou au sein d'un même substrat.  According to another embodiment, a phosphor is deposited between and on electroluminescent diodes of a sub-pixel. The phosphor can absorb the deep blue light emitted by the light-emitting diodes and transform it into green or red, or even blue. The advantage of using a blue phosphor and not the natural emission of the light-emitting diodes is an insensitivity of the quality of the blue to the color variations of the spontaneous emission of the wires, from one batch to another or within the same substrate.
Une méthode de dépôt sélectif de luminophore consiste à mélanger les grains de luminophore d'une première couleur avec de la résine silicone photosensible, puis après étalement sur l'ensemble du substrat et des diodes électroluminescentes, à fixer des luminophores sur les sous-pixels voulus par photolithographie. On réitère l'opération avec un second luminophore et autant de fois qu'il y a de sous-pixels de couleurs différentes.  A selective phosphor deposition method consists of mixing the phosphor grains of a first color with photosensitive silicone resin, then after spreading over the entire substrate and light-emitting diodes, to fix luminophores on the desired sub-pixels. by photolithography. The operation is repeated with a second phosphor and as many times as there are subpixels of different colors.
Une autre méthode est d'utiliser un équipement d'impression de type jet d'encre avec une « encre » composée du mélange silicone-luminophore et d'adjuvants spécifiques. Par impression, à partir d'une cartographie et de l'orientation et d'un référencement des sous-pixels, les luminophores sont déposés aux emplacements requis.  Another method is to use inkjet type printing equipment with an "ink" composed of the silicone-phosphor mixture and specific additives. By printing, from mapping and orientation and referencing the sub-pixels, phosphors are deposited at the required locations.
Des lentilles peuvent être prévues sur la couche d' encapsulâtion 70. A titre d'exemple, une lentille peut être prévue pour chaque sous-pixel ou pour des ensembles de sous- pixels .  Lenses may be provided on the encapsulation layer 70. For example, a lens may be provided for each subpixel or sets of subpixels.
Dans le mode de réalisation décrit précédemment, la couche isolante 62 recouvre la totalité du pourtour de la portion inférieure 58 de chaque fil 56. A titre de variante, une partie de la portion inférieure 58, voire la totalité de la portion inférieure 58, peut ne pas être recouverte par la couche isolante 62. Dans ce cas, la coque 64 peut recouvrir chaque fil 56 sur une hauteur supérieure à la hauteur de la portion supérieure 60, voire sur la totalité de la hauteur du fil 56. En outre, dans le mode de réalisation décrit précédemment, la couche isolante 62 ne recouvre pas le pourtour de la portion supérieure 60 de chaque fil 56. A titre de variante, la couche isolante 62 peut recouvrir une partie de la portion supérieure 60 de chaque fil 56. De plus, selon une autre variante, la couche isolante 62 peut, pour chaque fil 56, recouvrir partiellement la portion inférieure de la coque 64. Selon un autre mode de réalisation, la couche 62 peut ne pas être présente, notamment dans le cas où les plots de germination 54 sont remplacés par une couche de germination recouverte d'une couche diélectrique et que les fils sont formés sur la couche de germination dans des ouvertures prévues dans la couche diélectrique . In the embodiment described above, the insulating layer 62 covers the entire periphery of the lower portion 58 of each wire 56. As a variant, a portion of the lower portion 58, or even the entire lower portion 58, may not to be covered by the insulating layer 62. In this case, the shell 64 may cover each wire 56 on a height greater than the height of the upper portion 60, or over the entire height of the wire 56. In addition, in the embodiment described above, the insulating layer 62 does not cover the perimeter of the upper portion 60 of each wire 56. Alternatively, the insulating layer 62 may cover part of the upper portion 60 of each wire 56. In addition, according to another variant, the insulating layer 62 may, for each wire 56, partially cover the lower portion of the wire. the shell 64. According to another embodiment, the layer 62 may not be present, especially in the case where the seed pads 54 are replaced by a seed layer covered with a dielectric layer and that the son are formed on the seed layer in openings provided in the dielectric layer.
Le dispositif optoélectronique 40 peut être rapporté sur un autre circuit intégré, notamment un circuit de commande, comprenant des composants électroniques, notamment des transistors, utilisés pour la commande des ensembles de diodes électroluminescentes du dispositif optoélectronique 40.  The optoelectronic device 40 may be attached to another integrated circuit, in particular a control circuit, comprising electronic components, in particular transistors, used for controlling the light-emitting diode assemblies of the optoelectronic device 40.
En fonctionnement, les plots conducteurs 52 reliés électriquement à la couche conductrice 68 peuvent être reliés à une source d'un premier potentiel de référence. Le plot conducteur 52 au contact de la portion 50 du substrat 42 sur laquelle reposent les diodes électroluminescentes élémentaires d'un ensemble D de diodes électroluminescentes à activer peut être relié à une source d'un deuxième potentiel de référence de façon à faire circuler un courant au travers des diodes électroluminescentes élémentaires de l'ensemble D considéré. Chaque plot conducteur 52 pouvant s'étendre sur une partie importante de la portion 50 associée, une répartition homogène du courant peut être obtenue.  In operation, the conductive pads 52 electrically connected to the conductive layer 68 may be connected to a source of a first reference potential. The conductive pad 52 in contact with the portion 50 of the substrate 42 on which the elementary light-emitting diodes of a set D of light-emitting diodes to be activated can be connected to a source of a second reference potential so as to circulate a current through the elementary light-emitting diodes of the set D considered. Since each conductive pad 52 can extend over a large part of the associated portion 50, a homogeneous distribution of the current can be obtained.
Sur les figures 3A à 3C, la couche conductrice 68 est représentée au contact avec des portions 50 le long d'un côté du dispositif optoélectronique 40. A titre de variante, la couche conductrice 68 peut être au contact avec des portions 50 sur tout le pourtour du dispositif optoélectronique 40. Selon un mode de réalisation, le dispositif optoélectronique 40 est au moins en partie réalisé selon le procédé décrit dans la demande de brevet FR13/59413 qui est considérée comme faisant partie intégrante de la présente description. In FIGS. 3A to 3C, the conductive layer 68 is shown in contact with portions 50 along one side of the optoelectronic device 40. Alternatively, the conductive layer 68 may be in contact with portions 50 over the entire around the optoelectronic device 40. According to one embodiment, the optoelectronic device 40 is at least partly made according to the method described in the patent application FR13 / 59413 which is considered to be an integral part of the present description.
Un mode de réalisation d'un procédé de fabrication du dispositif optoélectronique 40 peut comprendre les étapes suivantes :  An embodiment of a method of manufacturing the optoelectronic device 40 may comprise the following steps:
(1) Gravure, pour chaque élément d'isolation élec- trique 48, d'une ouverture dans le substrat 42 du côté de la face avant 46. L'ouverture peut être formée par une gravure de type gravure ionique réactive, par exemple une gravure DRIE. La profondeur de l'ouverture est strictement supérieure à l'épaisseur visée du substrat 42 après une étape d'amincissement décrite par la suite. A titre d'exemple, la profondeur de l'ouverture est comprise entre 10 um et 200 um, par exemple environ 35 um ou 60 um.  (1) Engraving, for each electrical insulating element 48, an opening in the substrate 42 on the front face side 46. The opening may be formed by a reactive ion etching type etching, for example a DRIE engraving. The depth of the opening is strictly greater than the target thickness of the substrate 42 after a thinning step described below. By way of example, the depth of the opening is between 10 μm and 200 μm, for example about 35 μm or 60 μm.
(2) Formation d'une couche isolante, par exemple en oxyde de silicium, sur les parois latérales de l'ouverture, par exemple par un procédé d'oxydation thermique. L'épaisseur de la couche isolante peut être comprise entre 100 nm et 3000 nm, par exemple environ 200 nm.  (2) Formation of an insulating layer, for example silicon oxide, on the side walls of the opening, for example by a thermal oxidation process. The thickness of the insulating layer may be between 100 nm and 3000 nm, for example about 200 nm.
(3) Remplissage de l'ouverture par un matériau de remplissage, par exemple du silicium polycristallin, du tungstène ou un matériau métallique réfractaire compatible avec les étapes du procédé de fabrication réalisées à températures élevées, déposé par exemple par dépôt chimique en phase vapeur à basse pression (LPCVD, sigle anglais pour Low Pressure Chemical Vapor Déposition) . Le silicium polycristallin a, de façon avantageuse, un coefficient de dilatation thermique proche du silicium et permet ainsi de réduire les contraintes mécaniques durant les étapes du procédé de fabrication réalisées à températures élevées.  (3) Filling the opening with a filling material, for example polycrystalline silicon, tungsten or a refractory metal material compatible with the steps of the manufacturing process carried out at high temperatures, deposited for example by chemical vapor deposition at low pressure (LPCVD) for low pressure chemical vapor deposition. The polycrystalline silicon advantageously has a coefficient of thermal expansion close to silicon and thus makes it possible to reduce the mechanical stresses during the steps of the manufacturing process carried out at high temperatures.
(4) Polissage mécano-chimique (CMP) pour retrouver la surface du silicium et éliminer tout relief. (5) Formation des portions de germination 54, des fils 56, de la couche isolante 62 et des coques 64, par croissance par épitaxie, comme cela est décrit dans les demandes de brevet WO2014/044960 et FR13/59413 qui sont considérées comme faisant partie intégrante de la présente description. (4) Mechano-chemical polishing (CMP) to find the silicon surface and eliminate any relief. (5) Formation of the seed portions 54, the yarns 56, the insulating layer 62 and the shells 64, by epitaxial growth, as described in the patent applications WO2014 / 044960 and FR13 / 59413 which are considered as making integral part of this description.
(6) Formation de l'électrode 66 sur la totalité de la structure, par exemple par dépôt conforme de type dépôt chimique en phase vapeur (CVD, sigle anglais pour Chemical Vapor Déposition) , notamment dépôt de couche atomique (ALD, sigle anglais pour Atomic Layer Déposition) , ou dépôt physique en phase vapeur (PVD, sigle anglais pour Physical Vapor Déposition) .  (6) Formation of the electrode 66 over the entire structure, for example by chemical vapor deposition (CVD) type deposition, in particular atomic layer deposition (ALD), Atomic Layer Deposition), or Physical Vapor Deposition (PVD).
(7) Formation de l'ouverture 69 au travers de la couche isolante 62 et de la couche d'électrode 66.  (7) Formation of aperture 69 through insulating layer 62 and electrode layer 66.
(8) Formation de la couche conductrice 68 par exemple par PVD sur l'ensemble de la structure obtenue à l'étape (7) et gravure de cette couche pour exposer la portion de la couche d'électrode 66 recouvrant chaque fil 56.  (8) Formation of the conductive layer 68, for example by PVD, over the entire structure obtained in step (7) and etching of this layer to expose the portion of the electrode layer 66 covering each wire 56.
(9) Traitement thermique de recuit des contacts suivant l'empilement de la couche 68.  (9) Thermal annealing treatment of the contacts following the stacking of the layer 68.
(10) Dépôt de la couche d' encapsulâtion 70 sur la totalité de la structure obtenue à l'étape (8).  (10) Deposition of the encapsulation layer 70 over the entire structure obtained in step (8).
(11) Amincissement du substrat 42 jusqu'à atteindre les éléments 48 d'isolation latérale.  (11) Thinning of the substrate 42 until reaching the elements 48 of lateral insulation.
(12) Formation des plots conducteurs 52.  (12) Formation of conductive pads 52.
La zone active de chaque diode électroluminescente élémentaire est formée par des étapes de croissance par épitaxie sur une partie du fil 56. Le procédé de fabrication du dispositif optoélectronique 40 ne comprend donc pas d'étapes de gravure susceptibles de détériorer les zones actives des diodes électroluminescentes.  The active zone of each elemental light-emitting diode is formed by epitaxial growth steps on a portion of the wire 56. The manufacturing process of the optoelectronic device 40 therefore does not include etching steps liable to deteriorate the active zones of the light-emitting diodes. .
De façon avantageuse, la délimitation des sous-pixels d'affichage Pix est réalisée seulement par les éléments d'isolation électrique 48 et n'entraîne pas de modifications des étapes de fabrication des diodes électroluminescentes élémentaires. Selon un mode de réalisation, les diodes électroluminescentes élémentaires peuvent être réparties uniformément sur la face 46 du substrat 42. Même si des diodes électroluminescentes élémentaires peuvent se trouver à l'aplomb d'éléments d'isolation électrique 48 et ne pas être fonctionnelles, ceci présente l'avantage que les étapes de fabrication des diodes électroluminescentes élémentaires sont identiques quelle que soit la forme des sous-pixels d'affichage. Advantageously, the delimitation of the pixels Pix display subpixels is performed only by the electrical insulation elements 48 and does not lead to changes in the manufacturing steps of the elementary light emitting diodes. According to one embodiment, the diodes The elementary electroluminescent electrodes may be uniformly distributed on the face 46 of the substrate 42. Even though elementary light-emitting diodes may be in line with electrical insulation elements 48 and not be functional, this has the advantage that the steps of FIG. Elemental light emitting diodes are identical irrespective of the shape of the sub-display pixels.
Dans les modes de réalisation représentés sur les figures 3A à 3C, le dispositif optoélectronique 40 est relié électriquement à un circuit externe par des billes de soudure prévues du côté de la face inférieure 44 du substrat 42. Toutefois, d'autres modes de connexion électrique peuvent être envisagés.  In the embodiments shown in FIGS. 3A to 3C, the optoelectronic device 40 is electrically connected to an external circuit by solder balls provided on the side of the lower face 44 of the substrate 42. However, other modes of electrical connection can be considered.
Dans les modes de réalisation décrits précédemment, le substrat 42 est un substrat est en un matériau semiconducteur ou conducteur. Selon un autre mode de réalisation, le substrat 42 est en totalité ou en partie en un matériau isolant, par exemple en dioxyde de silicium (S1O2) ou en saphir. La connexion électrique entre les plots conducteurs 52 et la couche conductrice 68 ou les plots de germination 54 peut être réalisée en utilisant des éléments conducteurs traversant le substrat 42 sur la totalité de son épaisseur, par exemple des vias traversant ou TSV (acronyme anglais pour Through Silicon Via) .  In the embodiments described above, the substrate 42 is a substrate made of a semiconductor or conductive material. According to another embodiment, the substrate 42 is wholly or partly made of an insulating material, for example silicon dioxide (SiO 2) or sapphire. The electrical connection between the conductive pads 52 and the conductive layer 68 or the seed pads 54 can be achieved by using conductive elements passing through the substrate 42 over its entire thickness, for example vias through or TSV (acronym for Through Silicon Via).
Les figures 4A, 4B et 4C sont des figures analogues respectivement aux figures 3A, 3B et 3C d'un autre mode de réalisation d'un dispositif optoélectronique 80, notamment un écran d'affichage ou un dispositif de projection, dans lequel au moins un plot conducteur 82 est prévu au contact de la couche conductrice 68 du côté de la face avant 46. La couche d' encapsulâtion 70 comprend alors une ouverture 84 qui expose le plot conducteur 82. L'ouverture 69 décrite précédemment n'est pas présente. Ni la couche conductrice 68 ni la couche d'électrode 66 ne sont en contact électrique avec le substrat semiconducteur 42. En outre, il peut ne pas y avoir de plots conducteurs 52 au contact des portions 50 du substrat semiconducteur 42 qui ne sont pas connectées électriquement à des diodes électroluminescentes élémentaires. Le plot conducteur 82 est relié électriquement à un circuit externe, non représenté, par un fil non représenté. Un seul plot conducteur 82 est représenté sur la figure 4A. A titre de variante, plusieurs plots conducteurs 82 peuvent être répartis sur la couche conductrice 68, par exemple à la périphérie du dispositif optoélectronique 80. FIGS. 4A, 4B and 4C are figures similar respectively to FIGS. 3A, 3B and 3C of another embodiment of an optoelectronic device 80, in particular a display screen or a projection device, in which at least one conductive pad 82 is provided in contact with the conductive layer 68 on the side of the front face 46. The encapsulation layer 70 then comprises an opening 84 which exposes the conductive pad 82. The opening 69 described above is not present. Neither the conductive layer 68 nor the electrode layer 66 are in electrical contact with the semiconductor substrate 42. In addition, there may be no conductive pads 52 in contact with the portions 50 of the semiconductor substrate 42 that are not connected. electrically to light-emitting diodes elementary. The conductive pad 82 is electrically connected to an external circuit, not shown, by a not shown wire. A single conductive pad 82 is shown in FIG. 4A. As a variant, several conductive pads 82 may be distributed over the conductive layer 68, for example at the periphery of the optoelectronic device 80.
Les figures 5A et 5B sont des figures analogues respectivement aux figures 3A et 3B d'un autre mode de réalisation d'un dispositif optoélectronique 90, notamment un écran d'affichage ou un dispositif de projection. Le dispositif optoélectronique 90 comprend l'ensemble des éléments du dispositif optoélectronique 40 et comprend, en outre, des portions opaques 92 reposant sur la couche conductrice 68 entre des sous-pixels d'affichage adjacents, c'est-à-dire sensiblement dans le prolongement des éléments d'isolation électrique 48.  FIGS. 5A and 5B are figures similar to FIGS. 3A and 3B, respectively, of another embodiment of an optoelectronic device 90, in particular a display screen or a projection device. The optoelectronic device 90 comprises all the elements of the optoelectronic device 40 and furthermore comprises opaque portions 92 resting on the conductive layer 68 between adjacent display sub-pixels, that is to say substantially in the extension of the electrical insulation elements 48.
La hauteur de chaque portion opaque 92 peut être supérieure ou égale à la hauteur des fils 56. De préférence, la largeur de chaque portion opaque 92 est inférieure ou égale au plus petit écart entre deux diodes électroluminescentes élémentaires d'ensembles D adjacents. A titre d'exemple, chaque portion opaque 82 peut être en une résine colorée en noir. Cette résine est de préférence adaptée à absorber un rayonnement électromagnétique sur tout le spectre visible. La présence des portions opaques 92 permet, de façon avantageuse, d'augmenter le contraste du dispositif optoélectronique 90.  The height of each opaque portion 92 may be greater than or equal to the height of the wires 56. Preferably, the width of each opaque portion 92 is less than or equal to the smallest gap between two elementary light-emitting diodes of adjacent D-sets. By way of example, each opaque portion 82 may be in a resin colored in black. This resin is preferably adapted to absorb electromagnetic radiation over the entire visible spectrum. The presence of the opaque portions 92 advantageously makes it possible to increase the contrast of the optoelectronic device 90.
Divers modes de réalisation avec diverses variantes ont été décrits ci-dessus. On note que l'homme de l'art peut combiner divers éléments de ces divers modes de réalisation et variantes sans faire preuve d'activité inventive. A titre d'exemple, la structure du dispositif optoélectronique 90 représenté sur les figures 5A et 5B peut être mis en oeuvre avec la structure du dispositif optoélectronique 80 représenté sur les figures 4A, 4B et 4C.  Various embodiments with various variants have been described above. It is noted that one skilled in the art can combine various elements of these various embodiments and variants without being creative. By way of example, the structure of the optoelectronic device 90 shown in FIGS. 5A and 5B can be implemented with the structure of the optoelectronic device 80 shown in FIGS. 4A, 4B and 4C.

Claims

REVENDICATIONS
1. Dispositif optoélectronique (40 ; 80 ; 90) comprenant un substrat (42) comprenant des première et deuxième faces opposées (44, 46), des éléments (48) d'isolation électrique latérale s 'étendant de la première face (46) à la deuxième face (44) et délimitant dans le support des premières portions semiconductrices ou conductrices (50) isolées électriquement les unes des autres, le dispositif optoélectronique comprenant, en outre, pour chaque première portion, un premier plot conducteur (52) sur la deuxième face au contact de la première portion et une diode électroluminescente ou un ensemble (D) de diodes électroluminescentes reposant sur la première face et reliées électriquement à la première portion, le dispositif optoélec¬ tronique comprenant, en outre, une couche d'électrode (66) conductrice et au moins partiellement transparente recouvrant toutes les diodes électroluminescentes, une couche d'encap- sulation (70) isolante et au moins partiellement transparente recouvrant la couche d'électrode, et au moins un deuxième plot conducteur (52 ; 82) relié électriquement à la couche d'électrode. An optoelectronic device (40; 80; 90) comprising a substrate (42) having first and second opposing faces (44,46), side electrical insulation elements (48) extending from the first face (46). at the second face (44) and delimiting in the support of the first semiconductor or conductive portions (50) electrically insulated from each other, the optoelectronic device further comprising, for each first portion, a first conductive pad (52) on the second face in contact with the first portion and a light emitting diode or a set (D) of light emitting diodes resting on the first face and electrically connected to the first portion, the optoelec ¬ tronic device further comprising an electrode layer ( 66) and at least partially transparent covering all the light-emitting diodes, an insulating encapsulation layer (70) and at least partially ransparent coating the electrode layer, and at least one second conductive pad (52; 82) electrically connected to the electrode layer.
2. Dispositif optoélectronique selon la revendication 1, dans lequel chaque diode électroluminescente comprend au moins un élément semiconducteur (56) filaire, conique ou tronconique, intégrant ou recouvert au sommet et/ou au moins sur une partie de ses faces latérales par une coque (64) comprenant au moins une couche active adaptée à fournir la majorité du rayonnement de la diode électroluminescente.  Optoelectronic device according to claim 1, in which each light-emitting diode comprises at least one wired, conical or frustoconical semiconductor element (56) integrating or covered at the top and / or at least on a part of its lateral faces by a shell ( 64) comprising at least one active layer adapted to provide the majority of the radiation of the light-emitting diode.
3. Dispositif optoélectronique selon la revendication 1 ou 2, comprenant, en outre, une couche conductrice (68) recouvrant la couche d'électrode (66) autour des diodes électroluminescentes de chaque ensemble.  An optoelectronic device according to claim 1 or 2, further comprising a conductive layer (68) covering the electrode layer (66) around the light emitting diodes of each assembly.
4. Dispositif optoélectronique selon l'une quelconque des revendications 1 à 3, dans lequel les éléments (48) d' isolation électrique latérale comprennent au moins un mur isolant s' étendant dans le substrat (42) de la première face (46) à la deuxième face (44) . Optoelectronic device according to any one of claims 1 to 3, wherein the elements (48) of lateral electrical insulation comprise at least one insulating wall extending in the substrate (42) of the first face (46) to the second face (44).
5. Dispositif optoélectronique selon l'une quelconque des revendications 1 à 4, dans lequel les éléments (48) d'isolation électrique latérale délimitent, en outre, dans le support (42) , une deuxième portion semiconductrice ou conductrice (50) isolée électriquement des premières portions semicon¬ ductrices ou conductrices (50) et reliée électriquement à la couche d'électrode (66). Optoelectronic device according to any one of claims 1 to 4, wherein the elements (48) of lateral electrical insulation delimit, in addition, in the support (42), a second semiconductor or conductive portion (50) electrically isolated. first portions semicon ¬ ductrices or drivers (50) and electrically connected to the electrode layer (66).
6. Dispositif optoélectronique selon la revendication 5, dans lequel le deuxième plot conducteur (52) est au contact électrique de la deuxième portion semiconductrice ou conductrice (50) du côté de la deuxième face (44) .  Optoelectronic device according to claim 5, wherein the second conductive pad (52) is in electrical contact with the second semiconductive or conductive portion (50) on the side of the second face (44).
7. Dispositif optoélectronique selon l'une quelconque des revendications 1 à 4, dans lequel le deuxième plot conducteur (82) est situé du côté de la première face (46) .  Optoelectronic device according to any one of claims 1 to 4, wherein the second conductive pad (82) is located on the side of the first face (46).
8. Dispositif optoélectronique selon l'une quelconque des revendications 1 à 7, dans lequel le substrat (42) est en silicium, en germanium, en carbure de silicium, en un composé III- V, tel que du GaN ou du GaAs, ou en ZnO.  An optoelectronic device according to any one of claims 1 to 7, wherein the substrate (42) is silicon, germanium, silicon carbide, a III-V compound, such as GaN or GaAs, or in ZnO.
9. Dispositif optoélectronique selon la revendication 8, dans lequel le substrat (42) est en silicium monocristallin et comprend une concentration de dopants comprise entre 5*1016 atomes/cm3 et 2*1020 atomes/cm3. Optoelectronic device according to claim 8, wherein the substrate (42) is of monocrystalline silicon and comprises a dopant concentration of between 5 * 10 16 atoms / cm 3 and 2 * 10 20 atoms / cm 3 .
10. Dispositif optoélectronique selon l'une quelconque des revendications 1 à 9, dans lequel chaque élément semi- conducteur (56) est ma oritairement en un composé III-V, notamment du nitrure de gallium, ou en un composé II-VI.  An optoelectronic device according to any of claims 1 to 9, wherein each semiconductor element (56) is suitably a III-V compound, especially gallium nitride, or a compound II-VI.
11. Dispositif optoélectronique selon l'une quelconque des revendications 1 à 10, comprenant des lentilles sur la couche d' encapsulâtion (70).  An optoelectronic device according to any one of claims 1 to 10, comprising lenses on the encapsulation layer (70).
12. Dispositif optoélectronique selon l'une quelconque des revendications 1 à 11, dans lequel le dispositif opto¬ électronique est un écran d'affichage ou un dispositif de pro ection. 12. Optoelectronic device according to any one of claims 1 to 11, wherein the opto ¬ e is a display screen or a pro ection device.
13. Procédé de fabrication d'un dispositif opto- électronique (40 ; 80 ; 90) comprenant les étapes suivantes : a) former, dans un substrat (42) comprenant des première et deuxième faces opposées (44, 46) , des éléments (48) d'isolation électrique latérale s 'étendant de la première face (46) à la deuxième face (44) et délimitant dans le support des premières portions semiconductrices ou conductrices (50) isolées électriquement les unes des autres et former, pour chaque première portion, un premier plot conducteur (52) sur la deuxième face au contact de la première portion ; 13. A method of manufacturing an opto-electronic device (40; 80; 90) comprising the steps of: a) forming, in a substrate (42) having first and second opposing faces (44,46), side electrical insulation elements (48) extending from the first face (46) to the second face (44). and delimiting in the support of the first semiconductor or conductive portions (50) electrically insulated from each other and forming, for each first portion, a first conductive pad (52) on the second face in contact with the first portion;
b) former, pour chaque première portion, une diode électroluminescente ou un ensemble (D) de diodes électro¬ luminescentes reposant sur la première face et reliées électriquement à la première portion ; et b) forming, for each first portion, a light emitting diode or a set (D) of diodes electro luminescent ¬ resting on the first face and electrically connected to the first portion; and
c) former, pour chaque première portion, une couche d'électrode (66) conductrice et au moins partiellement trans- parente recouvrant toutes les diodes électroluminescentes, une couche d' encapsulâtion (70) en un matériau diélectrique au moins partiellement transparent recouvrant la couche d'électrode, et au moins un deuxième plot conducteur (52 ; 82) relié électriquement à la couche d'électrode.  c) forming, for each first portion, a conductive and at least partially transparent electrode layer (66) covering all the light-emitting diodes, an encapsulation layer (70) of at least partially transparent dielectric material covering the layer; electrode, and at least one second conductive pad (52; 82) electrically connected to the electrode layer.
14. Procédé selon la revendication 13, dans lequel l'étape a) comprend les étapes suivantes :  The method of claim 13, wherein step a) comprises the following steps:
avant l'étape b) , formation, dans le substrat (42), des éléments (48) d'isolation électrique latérale s 'étendant depuis la première face (46) sur une partie de la profondeur du substrat ; et  prior to step b), forming, in the substrate (42), lateral electrical insulation elements (48) extending from the first face (46) over a portion of the depth of the substrate; and
après l'étape c) , amincissement du substrat (42) pour former la deuxième face (44) et exposer les éléments (48) d'isolation électrique latérale sur la deuxième face.  after step c), thinning the substrate (42) to form the second face (44) and exposing the lateral electrical insulation elements (48) on the second face.
15. Procédé selon la revendication 13 ou 14, comprenant, en outre, le dépôt de luminophores sur au moins certaines des diodes électroluminescentes, notamment par des techniques de photolithographie ou par impression.  15. The method of claim 13 or 14, further comprising the deposition of phosphors on at least some of the light-emitting diodes, in particular by photolithography techniques or by printing.
16. Procédé selon l'une quelconque des revendications 13 à 15, dans lequel chaque diode électroluminescente comprend au moins un élément semiconducteur (56) filaire, conique ou tronconique, intégrant ou recouvert au sommet et/ou au moins sur une partie de ses faces latérales par une coque (64) comprenant au moins une couche active adaptée à fournir la majorité du rayonnement de la diode électroluminescente. The method of any one of claims 13 to 15, wherein each light emitting diode comprises at least one semiconductor element (56) wired, conical or frustoconical, incorporating or covered at the top and / or at least on a portion of its lateral faces by a shell (64) comprising at least one active layer adapted to provide the majority of the radiation of the light emitting diode.
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BR112017012829A2 (en) 2018-01-02

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