EP3224869A1 - Verticall structured power transistor with trench supply electrode - Google Patents
Verticall structured power transistor with trench supply electrodeInfo
- Publication number
- EP3224869A1 EP3224869A1 EP15817449.0A EP15817449A EP3224869A1 EP 3224869 A1 EP3224869 A1 EP 3224869A1 EP 15817449 A EP15817449 A EP 15817449A EP 3224869 A1 EP3224869 A1 EP 3224869A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- layer
- source
- trench
- box
- power transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/6634—Vertical insulated gate bipolar transistors with a recess formed by etching in the source/emitter contact region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
Definitions
- the present invention essentially relates to power transistors of the type VDMOS (acronym for Vertical Double Diffusion Metal Oxide Semiconductor that can be translated by semiconductor / metal / oxide vertical double diffusion) and type IGBT (acronym for the English Insulated Gate Bipolar Transistor that can be translated by bipolar transistor insulated gate).
- VDMOS acronym for Vertical Double Diffusion Metal Oxide Semiconductor that can be translated by semiconductor / metal / oxide vertical double diffusion
- type IGBT an acronym Insulated Gate Bipolar Transistor that can be translated by bipolar transistor insulated gate
- VDMOS are attractive devices for space and aeronautical applications because of the simplicity of their gate control, low volume and weight of circuits obtained compared to those incorporating bipolar transistors. In addition, they are more efficient in high frequency ranges and for switching power supplies.
- VDMOSs are field effect transistors, that is, unipolar components using only one type of charge carrier. They are therefore distinguished by very short switching times (of the order of 100 ns) because unlike bipolar components, there is no delay associated with the recombination of minority carriers in the blocking phase.
- This type of transistor is used in many applications from 10 to 500 kHz for voltage ranges from 10 to 1200 V and for a current rating of a few hundred milliamperes to a few amperes.
- the DMOS transistor Double diffusion Metal Oxide Semiconductor
- VDMOS vertical
- LDMOS lateral
- a VDMOS can be obtained as follows. Starting from an N + -type substrate on which an epitaxial layer N " is grown, PP-type islands, called caissons, are successively diffused and then, in these caissons, source zones of the N + type. drain connection P7P islands are short-circuited by metallization from the source. On the oxide layer is deposited an insulating layer of polysilicate coating a grid connection. The component illustrated in FIG. 1 is thus obtained.
- a VDMOS therefore comprises: a semiconductor material 101 on either side of which there is a source 102 and a drain 103; an insulated gate 104 on the same side as the source 102; three NPN layers in the semiconductor material, ie two opposing PN junctions that prohibit the conduction of the current, these three NPN layers being a first layer N formed by the substrate 105 N + and the epitaxial layer 106 N " , a second layer P formed by a box 107, and a third layer N formed by a source area 108 N + .
- V G s The application of a positive voltage V G s to the gate creates an electric field which drives the majority carriers of the P / P + islands creating an inversion of the type of the zone.
- a current can then flow in a channel, vertically in the substrate and in the epitaxial layer and then horizontally in the inverted doped zone of each P / P + island.
- the structure of an IGBT is based on that of a VDMOS: the thickness of the support 201 is used to separate the collector (drain) 203 from the emitter (source) 202.
- An epitaxial zone 206, doped N " allows the appearance of a channel when electrons are injected by the gate 204, that is to say when V G > 0 (on state)
- An IGBT can be observed in FIG. used to create P / P + 207 doped wells near the source 202, the P + doped region having the function (see below) of reducing the risks of destructive singular events.
- the main difference between a vertical MOSFET and an IGBT is the existence of a heavily doped 205 P + substrate layer on the collector side, whereas the substrate is N + doped in a VDMOS.
- This layer injects holes in the epitaxial layer 206 N " , which has the effect of reducing the voltage drop in the on state and transforming it into a bipolar transistor, the IGBT therefore having four main layers (of the emitter 202 to the manifold 203) NPNP.
- An IGBT is a hybrid transistor, consisting of a solid-state transistor input field and a bipolar transistor output. It is thus controlled by the gate voltage (voltage V G between gate and transmitter) applied to it, but its conduction characteristics (between collector and emitter) are those of a bipolar.
- This hybrid structure gives it the low energy cost of controlling a MOSFET, with the lower conduction losses (with a given chip surface) of a bipolar.
- IGBTs can handle a much higher voltage than that managed by MOSFETs.
- the epitaxial layer N " 106 or 206 which supports the voltage (both in an IGBT and in a VDMOS) .
- This maximum voltage will be all the more important that the epitaxial layer N " will be little doped and / or thick.
- a transistor To be efficient, a transistor must be able to withstand as much voltage as possible to its drain or collector.
- VDMOS and IGBTs are often used in spacecraft and aeronautics.
- the natural radiative environment presents many dangers for these electronic components.
- S space radiative environment including cosmic rays (protons from 100 to 10 6 MeV, high energy particles, heavy ions from 1 to 10 14 MeV), solar flares (protons from 10 MeV to 1 GeV, particles a from 10MeV to a few hundred MeV, heavy ions), solar winds (protons up to 100KeV, electrons up to a few keV, particles a), radiation belts (protons up to a few hundred MeV, electrons a few MeV);
- the atmospheric radiative environment including cosmic showers or air showers, in which highly energetic particles from cosmic radiation can ionize elements of the atmosphere and trigger nuclear chain reactions, forming a chain of secondary particles such as protons, neutrons or pions that may interact with embedded systems and more particularly with semiconductors.
- Cumulative phenomena such as the effects of ionizing doses are at the origin of functional errors and contribute to a deterioration of a device over time.
- the VDMOS have an undesirable characteristic: under certain conditions, a parasitic NPN 1 10 bipolar transistor is formed as illustrated in FIG.
- the source zone N + 108 constitutes the emitter of this parasitic transistor; the casing P 107 is the base, and the epitaxial layer N " 106 serves as a collector.
- This parasitic bipolar transistor normally inactive, can be turned on during a fast switching (high dV / dt) or by the passage of ionizing radiation. Its conduction coupled to the avalanche mechanisms can then cause an irreversible runaway current that leads to burnout.
- the operating principle requires to be in reverse bias in the off state with a sufficiently large space charge area to generate avalanche carriers. The phenomenon is initiated by the capture of holes diffusing laterally under the source in the box until direct polarizing the emitter / base junction of the parasitic bipolar transistor. Once the latter is active the electrons are injected from the transmitter to the epitaxial region by bipolar effect.
- this arrival of electrons has the effect of precipitating the phenomenon of avalanche. Indeed, the electrons crossing the space charge zone acquire sufficient kinetic energy to tear an electron from an atom of the crystal lattice, creating an electron-hole pair in collisions.
- the phenomenon is self-sustaining: the avalanche provides more and more holes to the parasitic bipolar, causing an injection of electrons from the larger bipolar which feeds the avalanche and so on.
- the very strong current flowing through a single cell leads to the destruction of the component by thermal runaway. In the case of an incident ionizing particle, the holes initially come from the ionization trace created by the passage of the latter.
- the parasitic bipolar transistor must therefore be desensitized.
- IGBTs have an undesirable characteristic responsible for the latch-up phenomenon (sometimes called locking phenomenon in French). Indeed, under certain conditions, the four NPNP layers of the IGBT can become vertically passable in the manner of a thyristor 210 (see FIG. 2), due to the presence of a parasitic transistor between the emitter and the base of the bipolar transistor. main. When such a lock occurs, the transistor remains on, with destructive effects, until the power is turned off. Unlike MOSFETs, the impact ionization mechanism is not necessary to trigger this parasitic operation. This means that the main cause that leads to the destruction of the IGBT when it is affected by incident radiation is the conduction and locking of the NPNP parasitic thyristor.
- the probability of achieving latch-up transistor destruction is greatest when the incident ionizing particle enters the intercellular zone and traverses the entire space charge zone.
- destructive events can be seen as soon as the bias voltage exceeds 90V.
- overdoping zone P + designates a zone having undergone at least two doping operations (by implantation , dissemination, etc.).
- a latch-up hardening technique for IGBTs has thus been proposed by varying the width of the overdopage zone P + of the emitter in order to reduce the injection efficiency of the parasitic NPNP thyristor.
- this zone of overdoping P + also has the effect of increasing the switching threshold voltage (voltage applied to the gate / base, either V G or V B E, beyond which the transistor becomes on and below from which it is blocked), which is undesirable;
- the aim of the invention is to overcome these drawbacks by proposing an insensitive power transistor or one that is very insensitive to radiative phenomena, and in particular to irradiations with heavy ions, that is to say a transistor that is unlikely to undergo a destructive event of the type latch-up or burn-out in case of irradiation, in the on state as in the off state, and without degradation of the voltage with respect to the known power transistors.
- Another object of the invention is to achieve this insensitivity result thanks to the very structure of the transistor (structural approach) that is to say independently of the circuit external to the transistor, as opposed to previous solutions proposing circuits of protection whose role is to temporarily cancel the voltage across the transistor to defuse unwanted tripping parasitic structures thereof.
- Another object of the invention is to provide an optimal preferred structure which confers both a high immunity against parasitic tripping while maintaining the static characteristics, including the threshold voltage, and dynamic known standard structures.
- the invention thus aims to provide power transistors that can be used safely in the aerospace field. Another object of the invention is to achieve this end without significantly increasing the manufacturing cost of the power transistor.
- the invention proposes a vertical structure power transistor having a cell having a plane of symmetry and comprising a semiconductor medium, as well as:
- a first supply electrode connecting the two symmetrical source layers and the box layer this first supply electrode being referenced cathode throughout the application, but it can also be called source in the case of a transistor to field effect (VDMOS) or transmitter in the case of a bipolar transistor (IGBT),
- VDMOS transistor to field effect
- IGBT bipolar transistor
- control electrode gate or base isolated and flat (so that one obtains a VDMOS or a "planar” IGBT as opposed to the "Trench” IGBT whose base is in trench);
- a second supply electrode referenced anode throughout the application, but which can also be called drain in a field effect transistor (VDMOS) or collector in a bipolar transistor (IGBT),
- the transistor is observed in a position in which its plane of symmetry is vertical, its front face is the upper face of the semiconductor support, its rear face is the face. bottom of the semiconductor support, the vertical direction (direction of gravity) is orthogonal to the back face.
- the transistor according to the invention is characterized in that: • the cathode has a trench portion formed in an etch formed in the front face of the semiconductor medium between the two source layers, which trench cathode portion comprises a bottom located in the box layer at a distance, in depth (that is to say in the vertical direction), from the NP source / box junction so as to move away from the source layer any side current which, in operation, crosses the box layer below the source layer to the cathode,
- L T on Ls L T / Ls
- L T / Ls standardized trench length, greater than or equal to 15/20
- L T denotes half of a maximum dimension of the etching in an orthogonal transverse direction to the plane of symmetry of the cell
- Ls denotes the distance between the plane of symmetry and the control electrode in the transverse direction.
- Ls represents the internal half-length of the cathode (the latter ending where the insulated control electrode begins) in the transverse direction.
- L T is strictly less than Ls, that is to say that L T / Ls is less than 1.
- the ratio L T / Ls is, according to the invention, between 0.75 (inclusive) and 1 (excluded).
- transverse direction means the (horizontal) direction orthogonal to the plane (vertical) of symmetry of the cell.
- the transistor cell furthermore comprises, in the semiconductor support:
- a box PN junction / epitaxy between the box layer and the epitaxial layer is a box PN junction / epitaxy between the box layer and the epitaxial layer.
- epitaxy in the expression “epitaxial layer” is not intended to limit this layer to its manufacturing process. The invention is also applicable if the layer here called “epitaxial layer” is not obtained by epitaxy.
- the bottom of the trenched cathode portion extends at a distance in depth from the box PN junction / epitaxy.
- the invention extends to a method of manufacturing a transistor according to the invention.
- the invention extends to a method of manufacturing a transistor comprising
- the formation of a cathode on the front face of the semiconductor support bypassing the two source layers and the box layer.
- an etching is provided on the front face of the semiconductor support prior to the formation of the source and caisson layers, at least two doping operations of the second conductivity type (preferably P + ) are performed so as to obtain an overdoping zone around the engraving and at least partially under the two source layers.
- the second conductivity type preferably P +
- the trenched cathode portion forms an edge in the box layer, and more precisely in the overdoping zone, away from the NP junction source / caisson. This edge allows a concentration of the electric field lines that participates in channeling the current and away from it from the source layer.
- a form of trench without stop, with softened outlines, is also possible.
- the trench cathode portion has sidewalls that are vertical.
- the NP source / box junction obtained is substantially horizontal.
- the overdopage zone according to the invention can extend, from each vertical side wall, under the adjacent source layer to a vertical plane delimiting the control electrode, so as to effectively protect the source layer.
- the trench cathode portion has a vertical section of rectangular shape. It has in this case vertical side walls and a horizontal flat bottom, and an edge at the intersection of the bottom and each side wall.
- This embodiment has proved to be the most effective in view of the technical problem that the invention intends to solve. It is also easy to achieve.
- the ratio W T on X N + is greater than or equal to 2, where W T , called trench depth, denotes the maximum dimension of the etching according to the invention.
- the vertical direction ie a distance between the plane containing the front face of the semiconductor support before etching (front face taken at the control electrode or the source layer for example) and the plane containing the front face of the semiconductor support taken at the etching at the etch
- X N + referred to as the depth of the source layer
- the maximum dimension of the source layer in the vertical direction ie a maximum distance between the source NP / box junction and the plane containing the face before etching (front face taken at the source layer for example)
- this maximum dimension in the vertical direction of the source layer can be observed at the side wall of the trench cathode portion adjacent to said layer of source; source.
- a ratio W T on X N + greater than 1 is sufficient to obtain a robust IGBT latch-up under normal conditions of use.
- NGBT becomes more robust to radiation and in particular to heavy ions.
- the ratio W T on X N + is equal to 4. From 4, the VDMOS according to the invention is totally insensitive to irradiations with heavy ions, whereas NGBT is totally insensitive to irradiation by heavy ions, whereas NGBT is the order of 80% of its breakdown voltage.
- the difference between W T and XN + is at least equal to 1 ⁇ .
- X P + is greater than or equal to 9 ⁇ , where X P + , called trench overdoping depth, denotes the maximum distance in the vertical direction between the bottom of the cathode portion. in trench and the bottom of the overdoping zone, which preferably corresponds to the bottom of the box, that is to say with the box PN junction / epitaxy.
- the structure of the power transistor has the following dimensions:
- the invention extends to a transistor characterized in combination by all or some of the characteristics mentioned above and below.
- the invention further extends to a power component, characterized in that it comprises a plurality of power transistors according to the invention.
- Figure 1 is a schematic vertical sectional view of a half cell of a prior standard VDMOS.
- S 2 is a schematic vertical section of a half of a previous standard IGBT cell.
- • s 3 is a schematic view in vertical section of one half of a power transistor cell according to the invention.
- FIG. 4 is a graph showing static characteristics, ie the current at the anode (ordinate) as a function of the bias voltage (abscissa), for a prior standard IGBT and for various embodiments of an IGBT according to the invention having different values of trench depth W T.
- S Figure 5 is a graph showing static characteristics, ie the current at the anode (ordinate) as a function of the bias voltage (abscissa), for a prior standard IGBT and for various embodiments of an IGBT according to the invention having different values of trench length L T.
- FIG. 6 is a graph showing static characteristics, ie the current at the anode (ordinate) as a function of the bias voltage (abscissa), for a prior standard IGBT and for various embodiments of an IGBT according to the invention having different values of overdoping depth trench Xp + .
- Figure 7 illustrates the linear energy transfer LET required to cause burnout for different polarizations and penetration depths ("ranges") for heavy ions from the front of a standard VDMOS (left graph ( a)) and a VDMOS according to the invention (right graph (b)).
- a power transistor according to the invention comprises a semiconductor support 301 as well as, from the bottom to the top of the figure:
- the complete cell therefore comprises a second source layer, symmetrical with the layer 308 illustrated with respect to the plane of symmetry P1;
- control electrode 304 also called grid
- S a cathode 302 formed by a metal conductive layer deposited on a front face 312 of the semiconductor medium 301 and on the insulating layer 316.
- the front face 312 is flat outside an etching described below.
- the source layer 308 here extends transversely under the cathode 302 to the edge of the control electrode 304, that is to say up to the vertical plane P2 which delimits said control electrode 304.
- the cathode 304 has a trench portion 309 which sinks into the box layer 307, and more precisely in the overdoping zone P + 307b of the box layer. It will be noted that the trench portion 309 of the cathode is in contact with this overdoping zone P + 307b over its entire length L T and over part of its height W T. On the remainder of its height W T , the trench portion 309 of the cathode is in contact with the N + source layer 308.
- the cathode portion in trench 309 has a vertical section of rectangular shape, with side walls 1 14 flat and vertical and a bottom 313 plan and horizontal. At the intersection of the bottom 313 and each side wall 314, a straight edge 315 can be seen.
- the horizontal section of the trench portion 309 of the cathode is also rectangular, preferably square.
- the normalized trench length L T / Ls is greater than or equal to 15/20 (0.75) and less than 1 by definition.
- the standardized trench length L T / Ls is 16/20.
- L N + designates the maximum length of each source layer 308, that is to say the maximum dimension of the source layer 308 in the transverse direction.
- the inventors have shown that the value of the half-trench length L T does not affect the value of the threshold voltage of the transistor.
- the trench depth W T is equal to 4 ⁇ .
- the inventors have shown that the latch-up phenomena do not occur regardless of the value of the depth Trench W T , as shown in Figure 4 in the case of an IGBT. Similar results have been obtained for the VDMOS according to the invention which, subjected to irradiation heavy ions, no longer suffer from burn-out regardless of trench depth.
- the depth of overdoping (or box) trench X P + which corresponds to the maximum vertical dimension of the overdoping zone P + 307b at the trench, is equal to 9 ⁇ .
- the inventors have shown that the latch-up and burn-out phenomena do not occur when the P / P + doping diffusion has a depth of 9 ⁇ or more in the configuration corresponding to the preferred version of the invention (that is to say with the other dimensional values given in the preceding paragraphs) as evidenced by the results presented in FIG.
- the proposed trench cathode portion has no influence on the dynamic behavior of the transistors (VDMOS and IGBT) relative to the corresponding standard structures. Only a slight decrease of the peak current at the anode is observed because of the reduction of the conductive area (area between the junction J2 and the junction J1) following the etching of the trench. Indeed, the vertical distance between the junctions J1 and J2 decreases with respect to the corresponding previous transistor (trenchless transistor having identical dimensions), since the junction J2 is shifted down by a distance equal to W T , Xp + equal overdop depth. If it is desired to keep the same peak current, it is sufficient to "lower" the junction J1 so as to maintain the distance J1-J2 of the anterior transistor or, more generally, to compensate for the loss of conductive surface.
- junction J2 in order to obtain the desired junction depth at the P + diffusion (junction J2) at the bottom of the trench, a rather long annealing (greater than 5 hours) may be necessary. Furthermore, usually, a nitride deposition step (Si 3 N 4 ) is performed before that of opening the contacts. To open the contacts, a dry engraving is necessary. However, since the nitride is deposited isotropically, including on the flanks of the trench after the etching, which is anisotropic, it could remain insulating on the vertical walls of the trench, greatly degrading the quality of the contact. cathode. It is therefore preferable to replace this nitride deposit with an oxide which can itself be removed by isotropic wet etching. The oxide can thus be removed from the sides of the trench.
- VDMOS in a VDMOS according to the invention placed in extreme conditions and in particular bombarded with heavy ions, there is no triggering of the parasitic transistor and therefore no burnout whatever the path of these ions in the substrate and the bias voltage in the off state.
- an earlier standard VDMOS is sensitive to all these ions from 15% of its breakdown voltage.
- no destructive phenomenon occurs, in the off state, for a bias voltage of up to more than 80% of the breakdown voltage.
- no destructive phenomenon has been observed up to a bias voltage of 500 V (see FIG. 7, where "SEB” means “Single Event Burn-out”, ie singular burn-out event or singular event destructive, and where the parameter "R” designates the "range” ie the depth of penetration of the heavy ion in the transistor from the front face), while this same voltage is limited to 90 V in an earlier standard IGBT, for the same breakdown voltage of 600 V in both structures.
- the invention can be the subject of numerous variants with respect to the preferred embodiment previously described, since these variants remain within the scope delimited by the appended claims.
- the shape of the trench cathode portion may be different from that illustrated (rectangular section) and its dimensions different from those proposed for the preferred version.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1461381A FR3029014A1 (en) | 2014-11-24 | 2014-11-24 | POWER TRANSISTOR WITH VERTICAL STRUCTURE AND TRENCH CATHODE |
PCT/FR2015/053189 WO2016083725A1 (en) | 2014-11-24 | 2015-11-24 | Verticall structured power transistor with trench supply electrode |
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EP3224869A1 true EP3224869A1 (en) | 2017-10-04 |
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ID=52779749
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EP15817449.0A Withdrawn EP3224869A1 (en) | 2014-11-24 | 2015-11-24 | Verticall structured power transistor with trench supply electrode |
Country Status (4)
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US (1) | US20170309738A1 (en) |
EP (1) | EP3224869A1 (en) |
FR (1) | FR3029014A1 (en) |
WO (1) | WO2016083725A1 (en) |
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CN112951915B (en) * | 2021-01-27 | 2022-06-03 | 杭州电子科技大学 | Power device reinforcing structure capable of resisting single-particle burning and preparation method thereof |
CN113871482B (en) * | 2021-09-29 | 2024-04-12 | 杭州电子科技大学 | LDMOS device for improving single particle burning resistance effect |
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US5159204A (en) | 1987-11-18 | 1992-10-27 | Bernacchi Jerald R | Structure and method for preventing latch-up in integrated circuits |
US5795793A (en) * | 1994-09-01 | 1998-08-18 | International Rectifier Corporation | Process for manufacture of MOS gated device with reduced mask count |
JP2010238738A (en) * | 2009-03-30 | 2010-10-21 | Toshiba Corp | Semiconductor device and method for manufacturing the semiconductor device |
US8253164B2 (en) * | 2010-12-23 | 2012-08-28 | Force Mos Technology Co., Ltd. | Fast switching lateral insulated gate bipolar transistor (LIGBT) with trenched contacts |
-
2014
- 2014-11-24 FR FR1461381A patent/FR3029014A1/en active Pending
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2015
- 2015-11-24 US US15/528,831 patent/US20170309738A1/en not_active Abandoned
- 2015-11-24 EP EP15817449.0A patent/EP3224869A1/en not_active Withdrawn
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WO2016083725A1 (en) | 2016-06-02 |
US20170309738A1 (en) | 2017-10-26 |
FR3029014A1 (en) | 2016-05-27 |
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