EP3193259B1 - Encoding data using combined data mask and data bus inversion - Google Patents
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4265—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus
Definitions
- the present disclosure relates to encoding data for transfer on a chip to chip communication link.
- Integrated circuit devices communicate with one another using input/output (I/O) circuits that are configured to transmit and receive multi-bit data over a plurality of signal lines.
- I/O input/output
- SSO simultaneous switching output
- SSN simultaneous switching noise
- US 2003/0158981 A1 discloses a method and system for transferring read data from a memory device having a data bus and a data masking pin adapted to receive a masking signal during write operations of the memory device.
- the method includes placing a sequence of read data words on the data bus and applying a data bus inversion signal on the data masking pin, the data bus inversion signal indicating whether the data contained in each read data word has been inverted.
- DBI data bus inversion
- DBI dynamic bus inversion
- a data mask (dm) signal is used by one circuit to indicate to another circuit that the data sent by the one circuit should be disregarded by the other circuit.
- the data mask signal may be used by a memory controller to indicate to a memory device that the data transmitted by the memory controller to the memory device should be ignored.
- the data mask signal can be a voltage level on a pin of the memory controller integrated circuit or part of a command transmitted between the memory controller and the memory device.
- Embodiments of the present disclosure include a data encoding scheme for transmission of data from one circuit to another circuit that combines DBI encoding and non-DBI encoding and uses a data mask signal to indicate the type of encoding used.
- non-DBI encoding is used to refer to any encoding scheme that is different from DBI.
- the data mask signal in a first state indicates that the data transmitted from one circuit to said another circuit is to be ignored, and the data mask signal in a second state indicates that the data transmitted from one circuit to said another circuit is not to be ignored. If the data mask signal is in the second state, a first subset of the data is encoded with data bus inversion and a second subset of the data is encoded differently from data bus inversion.
- the encoding scheme according to the embodiments described herein has the advantage that SSO noise can be dramatically reduced when the encoded data is transmitted from one circuit to another circuit.
- FIG. 1 illustrates a system including an encoder and decoder capable of coding and decoding data, according to one embodiment.
- the system of FIG. 1 includes two circuits communicating with each other on a parallel communication link 114.
- circuit 102 may be a memory controller
- circuit 104 may be a memory device such as a DRAM or SRAM.
- circuits 102, 104 may be other types of circuits communicating data between each other.
- the parallel communication link 114 may be a bus on a circuit board on which the circuits 102, 104 reside, and has a data width (n+2 bits) larger than the number of bits (n bits) of data D n to be transmitted from memory controller 102 to memory device 104.
- n is a positive integer greater than one (n > 1).
- the n-bit data D n have varying Hamming Weights (HWs) depending upon the number of logic level "1"s in the n-bit data D n .
- Hamming Weight refers to the number of non-zero (i.e., logic level "1") bits in the n-bit data D n .
- the link 114 is shown herein as a single-ended parallel communication link, note that link 114 can also be a link configured to transmit differential signals or multi-wire signals.
- Memory controller 102 includes an encoder 106 and a transmitter (Tx) 108. Data D n can be provided to encoder 106 as, for example, serial or parallel data. Memory device 104 also includes decoder 112 and a receiver (Rx) 110. In addition, memory device 104 may also include another encoder and a transmitter for transmitting encoded data to memory controller 102, and memory controller 102 may also include a receiver and a decoder for receiving and decoding the encoded data received from memory device 104. However, the encoder and transmitter of memory device 104 and the receiver and decoder of memory controller 102 are not shown in FIG. 1 as they are not necessary for explaining the embodiments of the present disclosure.
- Encoder 106 receives the n-bit data D n and a 1-bit data mask signal (dm) from other circuits (not shown) or other circuit components (e.g., state machines, not shown) within memory controller 102.
- the data mask signal (dm) is used for memory controller 102 to indicate to memory device 104 to ignore the data received from memory controller 102 (i.e., to indicate no-write operation).
- the dm signal can be a voltage level on a pin, which is offset or accompanies data being sent from the memory controller 102 to the memory device.
- Encoder 106 includes combinatorial logic gates or look-up tables (LUTs) that are configured to perform encoding of the n-bit data D n it receives to convert the n-bit data to n-bit encoded data DQ n and a DBI bit (1-bit). Encoder 106 also converts the data mask (dm) signal to a modified data mask (DM) signal. As will be explained in more detail below with reference to FIGS.
- LUTs look-up tables
- encoder 106 uses DBI encoding in some instances of the n-bit data D n and non-DBI encoding in other instances of the n-bit data D n to encode the n-bit data D n , depending upon the Hamming Weights of the n-bit data D n .
- Encoder 106 also generates the modified data mask signal (DM) to indicate to memory device 104 the type of encoding used in the n-bit encoded data DQ n in those different instances.
- DM modified data mask signal
- encoder 106 also receives a mode signal 116.
- mode signal 116 when mode signal 116 is asserted (e.g., logic high), encoder 106 encodes the n-bit data D n using the encoding scheme according to the embodiments of the present disclosure as described herein.
- mode signal 116 When mode signal 116 is not asserted (e.g., logic low), encoder 106 uses DBI encoding (that is independent of the use of masking information) to encode the n-bit data D n .
- transmitter (Tx) 108 transmits the encoded data DQ n , DBI bit, and the DM bit over the parallel link 114 to the receiver (Rx) 110 of memory device 104. In doing so, transmitter (Tx) 108 draws supply current Idd from a power supply (not shown) providing the supply voltage (Vdd), consuming power from the power supply and generating SSO noise. However, the SSO noise generated by transmitter (Tx) 108 can be reduced according to the embodiments of the present disclosure.
- receiver 110 receives the encoded data DQ n , DBI bit, and the DM bit over the parallel link 114 from memory controller 102. In doing so, receiver 110 also draws supply current Idd from a power supply (not shown) providing the supply voltage (Vdd), consuming power from the power supply and generating SSO noise. Again, the SSO noise generated by receiver (Rx) 110 can be reduced according to the embodiments of the present disclosure.
- Receiver 110 provides the received encoded data DQ n , DBI bit, and the DM bit to decoder 112.
- Decoder 112 decodes the encoded data DQ n and DBI bit back to n-bit data D n and converts the modified data mask signal (DM) back to the data mask signal (dm), as will be explained in more detail below with reference to FIGS. 4 and 5 .
- decoder 112 also receives a mode signal 516.
- mode signal 516 when mode signal 516 is asserted (e.g., logic high), decoder 112 decodes the n-bit encoded data DQ n using the decoding scheme according to the embodiments of the present disclosure as described herein.
- mode signal 516 is not asserted (i.e., logic low)
- decoder logic 112 uses DBI decoding (that is independent of the use of masking information) to decode the n-bit encoded data DQ n .
- FIG. 2 is a flow chart illustrating a method of encoding data, according to one embodiment.
- a combination of DBI encoding and non-DBI encoding is used to encode the n-bit data D n depending upon the Hamming Weight of the n-bit data D n , i.e., the number of non-zero (i.e., logic level "1") bits in the n-bit data D n .
- the n-bit data D n is encoded such that the n+1 bit encoded data [DBI, DQ n ] is a predetermined (n+1)-bit data pattern (DQM) indicative of a mask signal to memory device 104. Also, the modified data mask signal (DM) is set to "1" or logic high.
- step 206 it is further determined whether the n-bit data D n , when DBI encoded, has a Hamming Weight lower than a predetermined threshold. In other words, in step 206 it is further determined whether the uncoded n-bit data D n has a Hamming Weight lower than a first predetermined threshold or higher than a second predetermined threshold.
- a threshold of Hamming Weight 3 may be used such that the 8-bit data D n is considered low Hamming Weight data if the 8-bit data D n , when DBI encoded, has Hamming Weight lower than 4 (i.e., HW of DBI-encoded D n is 0, 1, 2, or 3), i.e., when the uncoded 8-bit data D n has Hamming Weight lower than 4 (i.e., HW of uncoded D n is 0, 1, 2, or 3) or higher than 5 (i.e., HW of uncoded D n is 6, 7, or 8).
- the n-bit data D n is encoded such that the n+1 bit encoded data [DBI, DQ n ] is DBI encoded.
- n-bit data D n is 8-bit data and has Hamming Weight of 4, no inversion of the data bits occurs and the DBI bit is not asserted (i.e., logic low).
- the 8-bit data D n has Hamming Weight of 5, inversion of the data bits occurs and the DBI bit is asserted (i.e., logic high).
- the n+1 bit encoded data [DBI, DQ n ] with DBI encoding in step 210 will have Hamming Weight of only 4. Also, the modified data mask signal (DM) is not asserted ("0" or logic low) in step 210.
- the n-bit DBI-encoded data D n is low Hamming Weight data in step 206, then the n-bit data D n is encoded using a non-DBI encoding scheme. In some embodiments, all or most of the n+1 bit encoded data [DBI, DQ n ] is encoded to be non-low Hamming Weight Data.
- n-bit data D n is 8-bit data
- the 8-bit data D n is encoded with a non-DBI encoding scheme that results in most (252) of the 9 bit encoded data [DBI, DQ n ] having Hamming Weights of four and merely some (4) of the 9 bit encoded data [DBI, DQ n ] having Hamming Weights of three.
- the modified data mask signal (DM) is asserted ("1" or logic high) even when the original data mask signal (dm) is not asserted to indicate to memory device 104 that a non-DBI encoding scheme was used to encode the n+1 bit encoded data [DBI, DQ n ].
- the modified data mask signal (DM) is used to indicate to the memory device 104 whether DBI encoding or non-DBI encoding was used to encode the n+1 bit encoded data [DBI, DQ n ].
- the encoding scheme of the embodiment of FIG. 2 significantly reduces SSO noise because the Hamming Weights of the encoded data [DBI, DQ n ] are limited to a small range of variations (for example, Hamming Weights of 3 or 4 in the example of 8 bit data D n ).
- Table 1 illustrates an example of combinatorial logic that may be used to encode 8-bit input data D n to 9-bit encoded data [DBI, DQ n ] according to the embodiment as shown in FIG. 2 .
- the combinatorial logic shown in Table 1 is merely exemplary, and other combinatorial logic may be used to perform the encoding as illustrated in FIG. 2 .
- the encoded data [DBI, DQ n ] is DQM (111000000).
- data D n with Hamming Weights of 4 or 5 are encoded using DBI such that the data bits of data D n with Hamming Weight of 4 are not inverted and the DBI bit is set to 0 while the data bits of data D n with Hamming Weight of 5 are inverted and the DBI bit is set to 1.
- the DBI-encoded data [DBI, DQ n ] has Hamming Weight of 4 only.
- data D n with Hamming Weights of 0, 1, 2, or 3 (lower than 4) or 6, 7, or 8 (higher than 5) are encoded using a non-DBI encoding scheme as shown above in Table 1 that limits the Hamming Weights of the encoded data [DBI, DQ n ] to Hamming Weights of 3 or 4.
- 8-bit data pattern in the form of 00000000 with HW of zero is encoded to the 9-bit encoded data pattern 101010000 with HW of three.
- 8-bit data in the form of x 7 x 6 x 5 x 4 0000 with HW of one are encoded into 9-bit data in the form of 01000 x 7 x 6 x 5 x 4 with HW of four
- 8-bit data patterns in the form of 0000 x 3 x 2 x 1 x 0 with HW of one are encoded to 9-bit encoded data patterns in the form of 00100 x 3 x 2 x 1 x 0 with HW of four, where x n is the n-th bit from a least significant bit of the 8-bit data pattern and x n is the complement of x n .
- 8-bit data patterns in the form of 00 x 5 x 4 x 3 x 2 x 1 x 0 with HW of two are encoded to 9-bit encoded data patterns in the form of 011 x 5 x 4 x 3 x 2 x 1 x 0 with HW of four
- 8-bit data patterns in the form of 01 x 5 x 4 x 3 x 2 x 1 x 0 with HW of two are encoded to 9-bit encoded data patterns in the form of 01010 y 3 y 2 y 1 y 0 with HW of four
- 8-bit data patterns in the form of 10 x 5 x 4 x 3 x 2 x 1 x 0 with HW of two are encoded to 9-bit encoded data patterns in the form of 01001 y 3 y 2 y 1 y 0 with HW of four
- 8-bit data patterns in the form of x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 with HW of three are encoded to 9-bit encoded data patterns in the form of 1 x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 with HW of four, where x n is the n-th bit from a least significant bit of the 8-bit data pattern.
- 8-bit data patterns in the form of x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 with HW of four are DBI-encoded to 9-bit encoded data patterns 0 x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 with HW of four, where x n is the n-th bit from a least significant bit of the 8-bit data pattern.
- 8-bit data patterns in the form of x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 with HW of five are also DBI-encoded to the 9-bit encoded data patterns in the form of 1 x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 with HW of four, where x n is the n-th bit from a least significant bit of the 8-bit data pattern and x n is the complement (inverse) of x .
- 8-bit data patterns in the form of 11 x 5 x 4 x 3 x 2 x 1 x 0 with HW of six are encoded to 9-bit encoded data patterns in the form of 000 x 5 x 4 x 3 x 2 x 1 x 0 with HW of four
- 8-bit data patterns in the form of 10 x 5 x 4 x 3 x 2 x 1 x 0 with HW of six are encoded to 9-bit encoded data patterns 00101 z 3 z 2 z 1 z 0 with HW of four
- 8-bit data patterns in the form of 01 x 5 x 4 x 3 x 2 x 1 x 0 with HW of six are encoded to 9-bit encoded data patterns 00110 z 3 z 2 z 1 z 0 with HW of four
- 8-bit data patterns in the form of 00 x 5 x 4 x 3 x 2 x 1 x 0 with HW of six are encoded to 9-bit
- 8-bit data patterns in the form of x 7 x 6 x 5 x 4 1111 with HW of seven are encoded to 9-bit encoded data patterns in the form of 00111 x 7 x 6 x 5 x 4 with HW of four
- 8-bit data patterns in the form of 1111 x 3 x 2 x 1 x 0 with HW of seven are encoded to 9-bit encoded data patterns in the form of 01011 x 3 x 2 x 1 x 0 with HW of four, where x n is n-th bit from a least significant bit of the 8-bit data pattern and x n is complement of x n .
- 8-bit data pattern 11111111 with HW of eight is encoded to 9-bit encoded data pattern 110100000 with HW of three.
- the DQM data pattern is set to be 111000000.
- n-bit data D n to be transmitted from memory controller 102 to memory device 104 is assumed to be 8-bit data in the examples above, the use of 8-bit data herein is merely exemplary.
- the encoding scheme described herein may be used with any number of bits of data to be transmitted from memory controller 102 to memory device 104. Mappings between 8-bit uncoded data and 9-bit coded data such as those shown in Table 1 above may be predetermined and stored in a LUT (not shown) on a memory controller 102. That way, encoding of data according the embodiments described herein may be performed rapidly.
- FIG. 3 illustrates one example of an encoder circuit, according to one embodiment.
- the encoder circuit of FIG. 3 is one example of a circuit configured to perform the encoding scheme as described above with reference to FIG. 2 , although different circuit configurations may be available with the same functions to perform the encoding scheme of FIG. 2 .
- the encoder 106 includes a DBI encoder 302, a non-DBI encoder 304, an AND gate 312, an OR gate 314, and multiplexers 308, 310.
- DBI encoder 302 is configured to conduct DBI encoding on the input data D n as explained above with step 210 of FIG. 2
- non-DBI encoder 304 is configured to conduct non-DBI encoding on the input data D n as explained above with step 208 of FIG.
- Mode signal 116 is used to indicate to encoder 116 whether the encoding scheme according to the embodiments herein ( FIG. 2 ) should be used (when mode 116 is asserted) or DBI encoding (that is independent of the use of masking information) should be used (when mode 116 is not asserted). For purposes of illustration herein of the encoding scheme of FIG. 2 , mode signal 116 will be assumed asserted (logic high).
- data mask signal (dm) 312 when data mask signal (dm) 312 is asserted ("1" or logic high), the modified data mask signal DM 326 output from OR gate 314 is also "1" or logic high.
- data mask signal (dm) 312 also causes multiplexer 310 to select the predetermined bit pattern DQM 323 as its output 316.
- the multiplexer 310 selects the output 322 of multiplexer 308 as its encoded data [DBI, DQ n ].
- the output 322 of multiplexer 308 is either the output 318 of DBI encoder 302 or the output 320 of non-DBI encoder 304, selected according to the output 324 of AND gate 312.
- DBI encoder 302 includes logic (not shown) configured to determine whether the input data D n , when DBI-encoded by DBI encoder 302, has a Hamming Weight lower than a predetermined threshold.
- DBI encoder 302 is also configured to determine whether the uncoded n-bit data D n has a Hamming Weight lower than a first predetermined threshold or higher than a second predetermined threshold.
- DBI encoder 302 when DBI-encoded by DBI encoder 302, has a Hamming Weight lower than a predetermined threshold, DBI encoder 302 generates the low HW signal 306 to be logic high ("1"), but otherwise generates the low HW signal 306 to be logic low (“0").
- mode signal 116 is set to be logic high
- the output 324 of AND gate 312 becomes logic high if the input data D n , when DBI-encoded by DBI encoder 302, has a Hamming Weight lower than a predetermined threshold and thus the low HW signal 306 is asserted.
- multiplexer 308 selects the output 320 of non-DBI encoder 304 as its output 322.
- the modified data mask signal DM 326 at logic high can indicate to the memory device 104 that a non-DBI encoding has been used to encode the input data D n .
- the output 324 of AND gate 312 becomes logic low if the input data D n , when DBI-encoded by DBI encoder 302, has a Hamming Weight not lower than a predetermined threshold and thus the low HW signal 306 is not asserted.
- multiplexer 308 selects the output 318 of DBI encoder 302 as its output 322.
- the modified data mask signal DM 326 at logic low can indicate to the memory device 104 that DBI encoding has been used to encode the input data D n .
- the modified data mask signal (DM) 326 output from OR gate 314 follows the original data mask signal (dm) 312, and multiplexer 308 always selects the output 318 of DBI encoder 302.
- multiplexer 310 selects the output 322 of multiplexer 308, which is always the output 318 of DBI encoder, resulting in DBI encoding regardless of the Hamming Weight of the input data D n .
- multiplexer 310 selects the DQM signal to indicate a mask signal to the memory device 104.
- mode signal 116 is at logic low, the encoder 106 performs DBI encoding (that is independent of the use of masking information), and thus the encoder 106 is completely backward compatible with conventional DBI encoding schemes.
- mode signal 116 may stored as a value in a programmable configuration register or hard wired by means of a fuse or metal mask, etc.
- FIG. 4 is a flow chart illustrating a method of decoding data, according to one embodiment.
- the decoding scheme of the embodiment of FIG. 4 is used to decode the data [DBI, DQ n ] encoded using a combination of DBI encoding and non-DBI encoding according to the encoding scheme as explained above with reference to FIG. 2 .
- the modified data mask signal (DM) is asserted ("1" or logic high). If the modified data mask signal (DM) is not asserted, that means the data [DBI, DQ n ] was DBI-encoded (step 210 of FIG. 2 ). Thus, data [DBI, DQ n ] is decoded using DBI and the data mask signal (dm) is set to "0" to indicate that the decoded data D n should not be ignored. On the other hand, if the modified data mask (DM) signal is not asserted, then it is further determined 406 whether the encoded data [DBI, DQ n ] matches the predetermined data pattern DQM.
- the encoded data [DBI, DQ n ] matches the predetermined data pattern DQM, that means the original data mask signal (dm) was asserted (step 204 of FIG. 2 ).
- the data mask signal (dm) is set to "1" to indicate that the encoded data DQ n should be ignored and DQ n is disregarded by memory device 104.
- the encoded data [DBI, DQ n ] does not match the predetermined data pattern DQM, then that means the data [DBI, DQ n ] was encoded using non-DBI encoding (step 208 of FIG. 2 ).
- the data [DBI, DQ n ] is decoded using non-DBI decoding and the data mask signal (dm) is set to "0.”
- decoding of the data [DBI, DQ n ] can be performed simply by reversing the combinatorial logic used to encode the data DQ n .
- the 9-bit data [DBI, DQ n ] can be decoded to recover the 8-bit data DQ n simply by reversing the combinatorial logic shown in Table 1.
- 9-bit data in the form of 01000 x 7 x 6 x 5 x 4 with HW of four can be decoded into 8 bit data x 7 x 6 x 5 x 4 0000 with HW of one.
- Numerous other examples of reversing the combinatorial logic for decoding are apparent from Table 1.
- such reverse mappings of logic may also be predetermined and stored in a LUT.
- FIG. 5 illustrates one example of a decoder circuit, according to one embodiment.
- the decoder circuit of FIG. 5 is one example of a circuit configured to perform the decoding scheme as described above with reference to FIG. 4 , although different circuit configurations may be available with the same functions to perform the decoding scheme of FIG. 4 .
- the decoder 112 includes a DBI decoder 502, a non-DBI decoder 504, AND gates 506, 530, an OR gate 526, a comparator 514, and a multiplexer 510.
- DBI decoder 502 is configured to conduct DBI decoding on the encoded data [DBI, DQ n ] as explained above with step 404 of FIG.
- Mode signal 516 is used to indicate to decoder 112 whether the decoding scheme according to the embodiments herein ( FIG. 4 ) should be used (when mode signal 516 is asserted) or DBI decoding (that is independent of the use of masking information) should be used (when mode signal 516 is not asserted). For purposes of illustration herein of the decoding scheme of FIG. 4 , mode signal 516 will be assumed asserted (logic high).
- the decoder circuit 112 when the modified data mask signal (DM) 512 is not asserted ("0" or logic low), that means that the data [DBI, DQ n ] was DBI-encoded (step 210 of FIG. 2 ).
- the data mask signal (dm) 532 output from AND gate 530 is set at logic low ("0").
- the output 508 of AND gate 506 is also at logic low, thereby causing multiplexer 510 to select the output 518 of DBI decoder 502 as its output DQ n 522.
- the data [DBI, DQ n ] is decoded using DBI (step 404 of FIG. 4 ).
- the output data mask signal (dm) 532 of AND gate 530 is at logic high if the output 524 of comparator 512 is at logic high, i.e., when the encoded data [DBI, DQ n ] matches the predetermined data pattern DQM as in step 406 of FIG. 4 .
- data mask signal (dm) 532 is at logic high, the encoded data is disregarded (step 408 of FIG. 4 ).
- the output 524 of comparator 512 is at logic low (i.e., when the encoded data [DBI, DQ n ] does not match the predetermined data pattern DQM), the output 528 of OR gate 528 is also at logic low ("0") and thus the data mask signal (dm) 532 output from AND gate 530 is also set at logic low.
- the output 508 of AND gate 506 is also at logic high, thereby causing multiplexer 510 to select the output 520 of non-DBI decoder 504 as its output DQ n 522.
- the data [DBI, DQ n ] is decoded using non-DBI decoding (step 410 of FIG. 4 ).
- mode signal 516 is at logic low (“0")
- the output 508 of AND gate 506 is also always at logic low regardless of the state of the modified data mask signal (DM) 512, thereby causing multiplexer 510 to always select the output 518 of DBI decoder 502 as its output DQ n 522.
- the output 528 of OR gate 526 is always at logic high if mode signal 516 is at logic low, and thus the data mask signal (dm) 532 output from AND gate 530 follows the state of the modified data mask signal (DM) 512.
- the data [DBI, DQ n ] is always decoded using DBI decoding when mode signal 516 is not asserted.
- mode signal 516 when mode signal 516 is at logic low, the decoder 112 performs DBI decoding (that is independent of the use of masking information), and thus the decoder 112 is completely backward compatible with conventional DBI decoding schemes.
- mode signal 516 may stored as a value in a programmable configuration register or hard wired by means of a fuse or metal mask, etc.
- FIG. 6A illustrates Hamming Weights (HWs) present in 9 bit data including 8 bit uncoded data and a DBI bit
- FIG. 6B illustrates Hamming Weights present in 9 bit coded data including a DBI bit and 8 bit coded data encoded according to one embodiment.
- HWs Hamming Weights
- the HW histogram illustrates the distribution of HWs in the 9-bit data including DBI (1 bit) and 8 bit uncoded data, and the HW histograms 602 when such uncoded 9 bit data is encoded using conventional DBI ([DBI + 8 bit DBI-encoded data]).
- the HW histograms 602 illustrates that only Hamming Weights 0 to 4 would be present when such 8 bit data is encoded using DBI ([DBI + 8 bit DBI-encoded data]), since data with Hamming Weights 5 through 8 would be inverted.
- the HW histogram 652 illustrates the distribution of HWs in the 9-bit data ([DBI + 8 bit encoded data]) including encoded according to the combined data mask and DBI encoding scheme as described above with reference to FIG. 2 .
- Table 2 shows the current (Idd) that would be drawn by transmitter (Tx) 108 ( FIG. 1 ) when the data D n is transmitted uncoded, conventional DBI-coded, and coded with combined DM/DBI according to the embodiments herein, referencing the supply current Idd to be drawn when data D n is transmitted uncoded as the reference (100%).
- Table 2 Idd Uncoded Conventional DBI Combined DM/DBI Coded Idd, DC-peak (%) 100% 50% 50% Idd, DC-average (%) 100% 40% 45% Idd, AC peak-peak (%) 100% 50% 25% Idd, AC rms (%) 100% 61% 13%
- the AC supply current drawn from the power supply is reduced dramatically, from 50% to 25% for AC peak-to-peak supply current Idd and from 61% to 13% for AC rms (root-mean-square) values, when the combined DM/DBI encoding scheme according to the embodiments described herein is used, compared to conventional DBI encoding.
- SSO noise can be dramatically reduced when using the combined DM/DBI encoding scheme according to the embodiments described herein.
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Description
- The present disclosure relates to encoding data for transfer on a chip to chip communication link.
- Integrated circuit devices communicate with one another using input/output (I/O) circuits that are configured to transmit and receive multi-bit data over a plurality of signal lines. When multiple output drivers on the circuits change state at the same time at a high speed to transmit the multi-bit data, the changing current drawn from a power supply by the output drivers induces a voltage that results in power supply disturbance, commonly referred to as simultaneous switching output ("SSO") noise (or simultaneous switching noise ("SSN)). SSN can cause undesired transient behavior among the output drivers, input receivers or internal logic on the circuits
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US 2003/0158981 A1 discloses a method and system for transferring read data from a memory device having a data bus and a data masking pin adapted to receive a masking signal during write operations of the memory device. The method includes placing a sequence of read data words on the data bus and applying a data bus inversion signal on the data masking pin, the data bus inversion signal indicating whether the data contained in each read data word has been inverted. - The invention is as defined by the
independent claims -
-
FIG. 1 illustrates a system including an encoder and decoder capable of coding and decoding data, according to one embodiment. -
FIG. 2 is a flow chart illustrating a method of encoding data, according to one embodiment. -
FIG. 3 illustrates one example of an encoder circuit, according to one embodiment. -
FIG. 4 is a flow chart illustrating a method of decoding data, according to one embodiment. -
FIG. 5 illustrates one example of a decoder circuit, according to one embodiment. -
FIG. 6A illustrates Hamming Weights (HWs) present in 9 bit data including 8 bit uncoded data and a DBI bit. -
FIG. 6B illustrates Hamming Weights present in 9 bit coded data including a DBI bit and 8 bit coded data encoded according to one embodiment. - Techniques used for reducing SSN on parallel links include data bus inversion (DBI), also referred to as dynamic bus inversion. DBI inverts some of the multi-bit data to be transferred based on the previous bits transmitted over the parallel communication link, for example, to reduce SSN by decreasing the number of transmitter switching transitions that occur across the link.
- A data mask (dm) signal is used by one circuit to indicate to another circuit that the data sent by the one circuit should be disregarded by the other circuit. For example, the data mask signal may be used by a memory controller to indicate to a memory device that the data transmitted by the memory controller to the memory device should be ignored. The data mask signal can be a voltage level on a pin of the memory controller integrated circuit or part of a command transmitted between the memory controller and the memory device.
- Embodiments of the present disclosure include a data encoding scheme for transmission of data from one circuit to another circuit that combines DBI encoding and non-DBI encoding and uses a data mask signal to indicate the type of encoding used. Here, the term "non-DBI encoding" is used to refer to any encoding scheme that is different from DBI. The data mask signal in a first state indicates that the data transmitted from one circuit to said another circuit is to be ignored, and the data mask signal in a second state indicates that the data transmitted from one circuit to said another circuit is not to be ignored. If the data mask signal is in the second state, a first subset of the data is encoded with data bus inversion and a second subset of the data is encoded differently from data bus inversion. The encoding scheme according to the embodiments described herein has the advantage that SSO noise can be dramatically reduced when the encoded data is transmitted from one circuit to another circuit.
- Reference will now be made to several embodiments of the present disclosure, examples of which are illustrated in the accompanying figures. It is noted that wherever practicable similar or like reference numbers may be used in the figures and may indicate similar or like functionality. The figures depict embodiments of the present disclosure for purposes of illustration only. One skilled in the art will readily recognize from the following description that alternative embodiments of the structures and methods illustrated herein may be employed without departing from the principles of the disclosure described herein.
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FIG. 1 illustrates a system including an encoder and decoder capable of coding and decoding data, according to one embodiment. The system ofFIG. 1 includes two circuits communicating with each other on aparallel communication link 114. For example,circuit 102 may be a memory controller, andcircuit 104 may be a memory device such as a DRAM or SRAM. However,circuits - The
parallel communication link 114 may be a bus on a circuit board on which thecircuits memory controller 102 tomemory device 104. Here, n is a positive integer greater than one (n > 1). The n-bit data Dn have varying Hamming Weights (HWs) depending upon the number of logic level "1"s in the n-bit data Dn. Here, Hamming Weight refers to the number of non-zero (i.e., logic level "1") bits in the n-bit data Dn. Although thelink 114 is shown herein as a single-ended parallel communication link, note thatlink 114 can also be a link configured to transmit differential signals or multi-wire signals. -
Memory controller 102 includes anencoder 106 and a transmitter (Tx) 108. Data Dn can be provided toencoder 106 as, for example, serial or parallel data.Memory device 104 also includesdecoder 112 and a receiver (Rx) 110. In addition,memory device 104 may also include another encoder and a transmitter for transmitting encoded data tomemory controller 102, andmemory controller 102 may also include a receiver and a decoder for receiving and decoding the encoded data received frommemory device 104. However, the encoder and transmitter ofmemory device 104 and the receiver and decoder ofmemory controller 102 are not shown inFIG. 1 as they are not necessary for explaining the embodiments of the present disclosure. -
Encoder 106 receives the n-bit data Dn and a 1-bit data mask signal (dm) from other circuits (not shown) or other circuit components (e.g., state machines, not shown) withinmemory controller 102. As explained above, the data mask signal (dm) is used formemory controller 102 to indicate tomemory device 104 to ignore the data received from memory controller 102 (i.e., to indicate no-write operation). The dm signal can be a voltage level on a pin, which is offset or accompanies data being sent from thememory controller 102 to the memory device. Alternatively, masking information conveyed by the dm signal may be included as part of a command transmitted between thememory controller 102 and thememory device 104, and thus no physical data mask signal dm need be present on theparallel link 114.Encoder 106 includes combinatorial logic gates or look-up tables (LUTs) that are configured to perform encoding of the n-bit data Dn it receives to convert the n-bit data to n-bit encoded data DQn and a DBI bit (1-bit).Encoder 106 also converts the data mask (dm) signal to a modified data mask (DM) signal. As will be explained in more detail below with reference toFIGS. 2 and3 ,encoder 106 uses DBI encoding in some instances of the n-bit data Dn and non-DBI encoding in other instances of the n-bit data Dn to encode the n-bit data Dn, depending upon the Hamming Weights of the n-bit data Dn. Encoder 106 also generates the modified data mask signal (DM) to indicate tomemory device 104 the type of encoding used in the n-bit encoded data DQn in those different instances. - In addition,
encoder 106 also receives amode signal 116. In one embodiment, whenmode signal 116 is asserted (e.g., logic high),encoder 106 encodes the n-bit data Dn using the encoding scheme according to the embodiments of the present disclosure as described herein. Whenmode signal 116 is not asserted (e.g., logic low),encoder 106 uses DBI encoding (that is independent of the use of masking information) to encode the n-bit data Dn. - In an embodiment, transmitter (Tx) 108 transmits the encoded data DQn, DBI bit, and the DM bit over the
parallel link 114 to the receiver (Rx) 110 ofmemory device 104. In doing so, transmitter (Tx) 108 draws supply current Idd from a power supply (not shown) providing the supply voltage (Vdd), consuming power from the power supply and generating SSO noise. However, the SSO noise generated by transmitter (Tx) 108 can be reduced according to the embodiments of the present disclosure. - In an embodiment,
receiver 110 receives the encoded data DQn, DBI bit, and the DM bit over theparallel link 114 frommemory controller 102. In doing so,receiver 110 also draws supply current Idd from a power supply (not shown) providing the supply voltage (Vdd), consuming power from the power supply and generating SSO noise. Again, the SSO noise generated by receiver (Rx) 110 can be reduced according to the embodiments of the present disclosure. -
Receiver 110 provides the received encoded data DQn, DBI bit, and the DM bit todecoder 112.Decoder 112 decodes the encoded data DQn and DBI bit back to n-bit data Dn and converts the modified data mask signal (DM) back to the data mask signal (dm), as will be explained in more detail below with reference toFIGS. 4 and5 . - In addition,
decoder 112 also receives amode signal 516. In one embodiment, whenmode signal 516 is asserted (e.g., logic high),decoder 112 decodes the n-bit encoded data DQn using the decoding scheme according to the embodiments of the present disclosure as described herein. Whenmode signal 516 is not asserted (i.e., logic low),decoder logic 112 uses DBI decoding (that is independent of the use of masking information) to decode the n-bit encoded data DQn. -
FIG. 2 is a flow chart illustrating a method of encoding data, according to one embodiment. According to the encoding scheme of the embodiment ofFIG. 2 , a combination of DBI encoding and non-DBI encoding is used to encode the n-bit data Dn depending upon the Hamming Weight of the n-bit data Dn, i.e., the number of non-zero (i.e., logic level "1") bits in the n-bit data Dn. - First, it is determined 202 whether the data mask signal (dm) is asserted (in this example "1" or logic high). If the data mask signal (dm) is asserted, the n-bit data Dn is encoded such that the n+1 bit encoded data [DBI, DQn] is a predetermined (n+1)-bit data pattern (DQM) indicative of a mask signal to
memory device 104. Also, the modified data mask signal (DM) is set to "1" or logic high. On the other hand, if the data mask signal (dm) is not asserted ("0" or logic low), then it is further determined 206 whether the n-bit data Dn, when DBI encoded, has a Hamming Weight lower than a predetermined threshold. In other words, instep 206 it is further determined whether the uncoded n-bit data Dn has a Hamming Weight lower than a first predetermined threshold or higher than a second predetermined threshold. For example, when Dn is 8-bit data, a threshold ofHamming Weight 3 may be used such that the 8-bit data Dn is considered low Hamming Weight data if the 8-bit data Dn, when DBI encoded, has Hamming Weight lower than 4 (i.e., HW of DBI-encoded Dn is 0, 1, 2, or 3), i.e., when the uncoded 8-bit data Dn has Hamming Weight lower than 4 (i.e., HW of uncoded Dn is 0, 1, 2, or 3) or higher than 5 (i.e., HW of uncoded Dn is 6, 7, or 8). - If the DBI-encoded n-bit data Dn is not low Hamming Weight data in
step 206, then the n-bit data Dn is encoded such that the n+1 bit encoded data [DBI, DQn] is DBI encoded. For example, when n-bit data Dn is 8-bit data and has Hamming Weight of 4, no inversion of the data bits occurs and the DBI bit is not asserted (i.e., logic low). On the other hand, if the 8-bit data Dn has Hamming Weight of 5, inversion of the data bits occurs and the DBI bit is asserted (i.e., logic high). Thus, for 8-bit input data Dn, the n+1 bit encoded data [DBI, DQn] with DBI encoding instep 210 will have Hamming Weight of only 4. Also, the modified data mask signal (DM) is not asserted ("0" or logic low) instep 210. - On the other hand, if the n-bit DBI-encoded data Dn is low Hamming Weight data in
step 206, then the n-bit data Dn is encoded using a non-DBI encoding scheme. In some embodiments, all or most of the n+1 bit encoded data [DBI, DQn] is encoded to be non-low Hamming Weight Data. For example, when n-bit data Dn is 8-bit data, the 8-bit data Dn is encoded with a non-DBI encoding scheme that results in most (252) of the 9 bit encoded data [DBI, DQn] having Hamming Weights of four and merely some (4) of the 9 bit encoded data [DBI, DQn] having Hamming Weights of three. Also, the modified data mask signal (DM) is asserted ("1" or logic high) even when the original data mask signal (dm) is not asserted to indicate tomemory device 104 that a non-DBI encoding scheme was used to encode the n+1 bit encoded data [DBI, DQn]. Thus, the modified data mask signal (DM) is used to indicate to thememory device 104 whether DBI encoding or non-DBI encoding was used to encode the n+1 bit encoded data [DBI, DQn]. The encoding scheme of the embodiment ofFIG. 2 significantly reduces SSO noise because the Hamming Weights of the encoded data [DBI, DQn] are limited to a small range of variations (for example, Hamming Weights of 3 or 4 in the example of 8 bit data Dn). - Table 1 below illustrates an example of combinatorial logic that may be used to encode 8-bit input data Dn to 9-bit encoded data [DBI, DQn] according to the embodiment as shown in
FIG. 2 . The combinatorial logic shown in Table 1 is merely exemplary, and other combinatorial logic may be used to perform the encoding as illustrated inFIG. 2 .Table 1 HW of 8-bit data Dn 8 Bit Uncoded Data Dn (x= x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0) 9-Bit Encoded Data [DBI, DQn] ( x is complement of x)Notes and Logic ("+" is OR operation) HW of Coded Data [DBI, DQn] 0 0000 0000 1 0101 0000 3 1 x 7 x 6 x 5 x 4 0000 0 1000 x 7 x 6 x 5 x 4 4 0000 x 3 x 2 x 1 x 0 0 0100 x 3 x 2 x 1 x 0 4 2 00 x 5 x 4 x 3 x 2 x 1 x 0 0 11 x 5 x 4 x 3 x 2 x 1 x 0 y 3 = x 5 + x2 + x 0 4 01 x 5 x 4 x 3 x 2 x 1 x 0 0 1010 y 3 y 2 y 1 y 0 Y 2 = x 5 + x 4 + x 1 4 10 x 5 x 4 x 3 x 2 x 1 x 0 0 1001 y3 y 2 y 1 y 0 y 1 = x 4 + x 3 + x 0 4 11 x 5 x 4 x 3 x 2 x 1 x 0 0 1001 0001 y 0 x 3 x 2 x 1 3 3 x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 1 x7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 4 4 x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 0 x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 DBI (no inversion) 4 5 x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 1 x7 x 6 x 5 x 4 x3 x 2 x 1 x 0 DBI (inversion) 4 6 11 x 5 x 4 x 3 x 2 x 1 x 0 0 00 x 5 x 4 x 3 x 2 x 1 x 0 z 3 = x 5 +x 2 +x 0 4 10 x 5 x 4 x 3 x 2 x 1 x 0 0 0101 z 3 z 2 z 1 z 0 z 2 = x 5 +x 4 +x 1 4 01 x 5 x 4 x 3 x 2 x 1 x 0 0 0110 z 3 z 2 z 1 z 0 z 1 = x 4 +x 3 +x 0 4 00 x 5 x 4 x 3 x 2 x 1 x 0 0 0110 0001 z 0 = x 3 +x 2 +x 1 3 7 x 7 x 6 x 5 x 4 1111 0 0111 x 7 x 6 x 5 x 4 4 1111 x 3 x 2 x 1 x 0 0 1011 x 3 x 2 x 1 x 0 4 8 1111 1111 1 1010 0000 3 Data Mask (dm)=1 DQM=1 1100 0000 3 - As can be seen from Table 1 above, when the data mask signal (dm) is asserted, the encoded data [DBI, DQn] is DQM (111000000). On the other hand, when the data mask signal (dm) is not asserted, then data Dn with Hamming Weights of 4 or 5 are encoded using DBI such that the data bits of data Dn with Hamming Weight of 4 are not inverted and the DBI bit is set to 0 while the data bits of data Dn with Hamming Weight of 5 are inverted and the DBI bit is set to 1. The DBI-encoded data [DBI, DQn] has Hamming Weight of 4 only. Also, when the data mask signal (dm) is not asserted, then data Dn with Hamming Weights of 0, 1, 2, or 3 (lower than 4) or 6, 7, or 8 (higher than 5) are encoded using a non-DBI encoding scheme as shown above in Table 1 that limits the Hamming Weights of the encoded data [DBI, DQn] to Hamming Weights of 3 or 4.
- More specifically, as shown in Table 1, 8-bit data pattern in the form of 00000000 with HW of zero is encoded to the 9-bit encoded data pattern 101010000 with HW of three. 8-bit data in the form of x 7 x 6 x 5 x 4 0000 with HW of one are encoded into 9-bit data in the form of 01000
x 7 x 6 x 5 x 4 with HW of four, and 8-bit data patterns in the form of 0000 x 3 x 2 x 1 x 0 with HW of one are encoded to 9-bit encoded data patterns in the form of 00100x 3 x 2 x 1 x 0 with HW of four, where xn is the n-th bit from a least significant bit of the 8-bit data pattern andxn is the complement of xn . 8-bit data patterns in the form of 00 x 5 x 4 x 3 x 2 x 1 x 0 with HW of two are encoded to 9-bit encoded data patterns in the form of 011 x 5 x 4 x 3 x 2 x 1 x 0 with HW of four, 8-bit data patterns in the form of 01 x 5 x 4 x 3 x 2 x 1 x 0 with HW of two are encoded to 9-bit encoded data patterns in the form of 01010 y 3 y 2 y 1 y 0 with HW of four, 8-bit data patterns in the form of 10 x 5 x 4 x 3 x 2 x 1 x 0 with HW of two are encoded to 9-bit encoded data patterns in the form of 01001 y 3 y 2 y 1 y 0 with HW of four, and 8-bit data patterns in the form of 11 x 5 x 4 x 3 x 2 x 1 x 0 with HW of two are encoded to 9-bit encoded data pattern 010010001 with HW of three, where xn is the n-th bit from a least significant bit of the 8-bit data pattern, y 3 = x 5 + x 2 + x 0, y 2 = x 5 + x 4 + x 1, y 1 = x 4 + x 3 + x 0, and y 0 = x 3 + x 2 + x 1 and where + is OR operation. - For another example, 8-bit data patterns in the form of x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 with HW of three are encoded to 9-bit encoded data patterns in the form of 1 x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 with HW of four, where xn is the n-th bit from a least significant bit of the 8-bit data pattern. 8-bit data patterns in the form of x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 with HW of four are DBI-encoded to 9-bit encoded data patterns 0 x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 with HW of four, where xn is the n-th bit from a least significant bit of the 8-bit data pattern. 8-bit data patterns in the form of x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 with HW of five are also DBI-encoded to the 9-bit encoded data patterns in the form of 1
x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 with HW of four, where xn is the n-th bit from a least significant bit of the 8-bit data pattern andxn is the complement (inverse) of x. - For still another example, 8-bit data patterns in the form of 11 x 5 x 4 x 3 x 2 x 1 x 0 with HW of six are encoded to 9-bit encoded data patterns in the form of 000 x 5 x 4 x 3 x 2 x 1 x 0 with HW of four, 8-bit data patterns in the form of 10 x 5 x 4 x 3 x 2 x 1 x 0 with HW of six are encoded to 9-bit encoded data patterns 00101 z 3 z 2 z 1 z 0 with HW of four, 8-bit data patterns in the form of 01 x 5 x 4 x 3 x 2 x 1 x 0 with HW of six are encoded to 9-bit encoded data patterns 00110 z 3 z 2 z 1 z 0 with HW of four, and 8-bit data patterns in the form of 00 x 5 x 4 x 3 x2 x 1 x 0 with HW of six are encoded to 9-bit encoded data patterns 001100001 with HW of three, where xn is the n-th bit from a least significant bit of the 8-bit data pattern, z 3 =
x 5 +x 2 +x 0 , z 2 =x 5 +x 4 +x 1 , z 1 =x 4 +x 3 +x 0 , and z 0 =x 3 +x 2 +x 1 ,xn is complement of xn , and "+" is OR operation. 8-bit data patterns in the form of x 7 x 6 x 5 x 4 1111 with HW of seven are encoded to 9-bit encoded data patterns in the form of 00111x 7 x 6 x 5 x 4 with HW of four, and 8-bit data patterns in the form of 1111 x 3 x 2 x 1 x 0 with HW of seven are encoded to 9-bit encoded data patterns in the form of 01011x 3 x 2 x 1 x 0 with HW of four, where xn is n-th bit from a least significant bit of the 8-bit data pattern andxn is complement of xn. For still another example, 8-bit data pattern 11111111 with HW of eight is encoded to 9-bit encoded data pattern 110100000 with HW of three. Also, the DQM data pattern is set to be 111000000. - Although the n-bit data Dn to be transmitted from
memory controller 102 tomemory device 104 is assumed to be 8-bit data in the examples above, the use of 8-bit data herein is merely exemplary. Thus, the encoding scheme described herein may be used with any number of bits of data to be transmitted frommemory controller 102 tomemory device 104. Mappings between 8-bit uncoded data and 9-bit coded data such as those shown in Table 1 above may be predetermined and stored in a LUT (not shown) on amemory controller 102. That way, encoding of data according the embodiments described herein may be performed rapidly. -
FIG. 3 illustrates one example of an encoder circuit, according to one embodiment. The encoder circuit ofFIG. 3 is one example of a circuit configured to perform the encoding scheme as described above with reference toFIG. 2 , although different circuit configurations may be available with the same functions to perform the encoding scheme ofFIG. 2 . Theencoder 106 includes aDBI encoder 302, anon-DBI encoder 304, an ANDgate 312, an ORgate 314, andmultiplexers DBI encoder 302 is configured to conduct DBI encoding on the input data Dn as explained above withstep 210 ofFIG. 2 andnon-DBI encoder 304 is configured to conduct non-DBI encoding on the input data Dn as explained above withstep 208 ofFIG. 2 , for example as shown above in Table 1.Mode signal 116 is used to indicate toencoder 116 whether the encoding scheme according to the embodiments herein (FIG. 2 ) should be used (whenmode 116 is asserted) or DBI encoding (that is independent of the use of masking information) should be used (whenmode 116 is not asserted). For purposes of illustration herein of the encoding scheme ofFIG. 2 ,mode signal 116 will be assumed asserted (logic high). - Turning to the operation of the
encoder circuit 106, when data mask signal (dm) 312 is asserted ("1" or logic high), the modified datamask signal DM 326 output from ORgate 314 is also "1" or logic high. In addition, data mask signal (dm) 312 also causesmultiplexer 310 to select the predeterminedbit pattern DQM 323 as itsoutput 316. - On the other hand, if the data mask signal (dm) 312 is not asserted ("0" or logic low), the
multiplexer 310 selects theoutput 322 ofmultiplexer 308 as its encoded data [DBI, DQn]. Theoutput 322 ofmultiplexer 308 is either theoutput 318 ofDBI encoder 302 or theoutput 320 ofnon-DBI encoder 304, selected according to theoutput 324 of ANDgate 312. In this regard,DBI encoder 302 includes logic (not shown) configured to determine whether the input data Dn, when DBI-encoded byDBI encoder 302, has a Hamming Weight lower than a predetermined threshold. In other words,DBI encoder 302 is also configured to determine whether the uncoded n-bit data Dn has a Hamming Weight lower than a first predetermined threshold or higher than a second predetermined threshold. When the input data Dn, when DBI-encoded byDBI encoder 302, has a Hamming Weight lower than a predetermined threshold,DBI encoder 302 generates the low HW signal 306 to be logic high ("1"), but otherwise generates the low HW signal 306 to be logic low ("0"). - Since
mode signal 116 is set to be logic high, theoutput 324 of ANDgate 312 becomes logic high if the input data Dn, when DBI-encoded byDBI encoder 302, has a Hamming Weight lower than a predetermined threshold and thus thelow HW signal 306 is asserted. As a result,multiplexer 308 selects theoutput 320 ofnon-DBI encoder 304 as itsoutput 322. In addition, theoutput 326 ofOR gate 314 also becomes logic high (modified data mask signal DM=1) even through the original datamask signal dm 312 is not asserted. Thus, the modified datamask signal DM 326 at logic high can indicate to thememory device 104 that a non-DBI encoding has been used to encode the input data Dn. - On the other hand, the
output 324 of ANDgate 312 becomes logic low if the input data Dn, when DBI-encoded byDBI encoder 302, has a Hamming Weight not lower than a predetermined threshold and thus thelow HW signal 306 is not asserted. As a result,multiplexer 308 selects theoutput 318 ofDBI encoder 302 as itsoutput 322. In addition, theoutput 326 ofOR gate 314 also becomes logic low (modified data mask signal DM=0) when the original data mask signal (dm) 312 is not asserted. Thus, the modified datamask signal DM 326 at logic low can indicate to thememory device 104 that DBI encoding has been used to encode the input data Dn. - Finally, when
mode signal 116 is at logic low ("0"), then theoutput 324 of ANDgate 312 is always at logic low regardless of thelow HW signal 306. Thus, the modified data mask signal (DM) 326 output from ORgate 314 follows the original data mask signal (dm) 312, andmultiplexer 308 always selects theoutput 318 ofDBI encoder 302. Thus, when the original data mask signal (dm) 312 is not asserted,multiplexer 310 selects theoutput 322 ofmultiplexer 308, which is always theoutput 318 of DBI encoder, resulting in DBI encoding regardless of the Hamming Weight of the input data Dn. When the original data mask signal (dm) 312 is asserted,multiplexer 310 selects the DQM signal to indicate a mask signal to thememory device 104. Thus, whenmode signal 116 is at logic low, theencoder 106 performs DBI encoding (that is independent of the use of masking information), and thus theencoder 106 is completely backward compatible with conventional DBI encoding schemes. For example,mode signal 116 may stored as a value in a programmable configuration register or hard wired by means of a fuse or metal mask, etc. -
FIG. 4 is a flow chart illustrating a method of decoding data, according to one embodiment. The decoding scheme of the embodiment ofFIG. 4 is used to decode the data [DBI, DQn] encoded using a combination of DBI encoding and non-DBI encoding according to the encoding scheme as explained above with reference toFIG. 2 . - First, it is determined 402 whether the modified data mask signal (DM) is asserted ("1" or logic high). If the modified data mask signal (DM) is not asserted, that means the data [DBI, DQn] was DBI-encoded (step 210 of
FIG. 2 ). Thus, data [DBI, DQn] is decoded using DBI and the data mask signal (dm) is set to "0" to indicate that the decoded data Dn should not be ignored. On the other hand, if the modified data mask (DM) signal is not asserted, then it is further determined 406 whether the encoded data [DBI, DQn] matches the predetermined data pattern DQM. - If the encoded data [DBI, DQn] matches the predetermined data pattern DQM, that means the original data mask signal (dm) was asserted (step 204 of
FIG. 2 ). Thus, the data mask signal (dm) is set to "1" to indicate that the encoded data DQn should be ignored and DQn is disregarded bymemory device 104. On the other hand, if the encoded data [DBI, DQn] does not match the predetermined data pattern DQM, then that means the data [DBI, DQn] was encoded using non-DBI encoding (step 208 ofFIG. 2 ). Thus, the data [DBI, DQn] is decoded using non-DBI decoding and the data mask signal (dm) is set to "0." - Note that decoding of the data [DBI, DQn] can be performed simply by reversing the combinatorial logic used to encode the data DQn. For example, when 8-bit data DQn is encoded to 9-bit data [DBI, DQn] using combinatorial logic shown in Table 1, the 9-bit data [DBI, DQn] can be decoded to recover the 8-bit data DQn simply by reversing the combinatorial logic shown in Table 1. For example, 9-bit data in the form of 01000
x 7 x 6 x 5 x 4 with HW of four can be decoded into 8 bit data x 7 x 6 x 5 x 4 0000 with HW of one. Numerous other examples of reversing the combinatorial logic for decoding are apparent from Table 1. In some embodiments, such reverse mappings of logic may also be predetermined and stored in a LUT. -
FIG. 5 illustrates one example of a decoder circuit, according to one embodiment. The decoder circuit ofFIG. 5 is one example of a circuit configured to perform the decoding scheme as described above with reference toFIG. 4 , although different circuit configurations may be available with the same functions to perform the decoding scheme ofFIG. 4 . Thedecoder 112 includes aDBI decoder 502, anon-DBI decoder 504, ANDgates gate 526, acomparator 514, and amultiplexer 510.DBI decoder 502 is configured to conduct DBI decoding on the encoded data [DBI, DQn] as explained above withstep 404 ofFIG. 5 andnon-DBI encoder 504 is configured to conduct non-DBI decoding on the encoded data [DBI, DQn] as explained above withstep 410 ofFIG. 4 .Mode signal 516 is used to indicate todecoder 112 whether the decoding scheme according to the embodiments herein (FIG. 4 ) should be used (whenmode signal 516 is asserted) or DBI decoding (that is independent of the use of masking information) should be used (whenmode signal 516 is not asserted). For purposes of illustration herein of the decoding scheme ofFIG. 4 ,mode signal 516 will be assumed asserted (logic high). - Turning to the operation of the
decoder circuit 112, when the modified data mask signal (DM) 512 is not asserted ("0" or logic low), that means that the data [DBI, DQn] was DBI-encoded (step 210 ofFIG. 2 ). Thus, the data mask signal (dm) 532 output from ANDgate 530 is set at logic low ("0"). In addition, theoutput 508 of ANDgate 506 is also at logic low, thereby causingmultiplexer 510 to select theoutput 518 ofDBI decoder 502 as itsoutput DQ n 522. Thus, the data [DBI, DQn] is decoded using DBI (step 404 ofFIG. 4 ). - When the modified data mask signal (DM) 512 is asserted ("1" or logic high), the output data mask signal (dm) 532 of AND
gate 530 is at logic high if theoutput 524 ofcomparator 512 is at logic high, i.e., when the encoded data [DBI, DQn] matches the predetermined data pattern DQM as instep 406 ofFIG. 4 . When data mask signal (dm) 532 is at logic high, the encoded data is disregarded (step 408 ofFIG. 4 ). - On the other hand, if the
output 524 ofcomparator 512 is at logic low (i.e., when the encoded data [DBI, DQn] does not match the predetermined data pattern DQM), theoutput 528 ofOR gate 528 is also at logic low ("0") and thus the data mask signal (dm) 532 output from ANDgate 530 is also set at logic low. In addition, theoutput 508 of ANDgate 506 is also at logic high, thereby causingmultiplexer 510 to select theoutput 520 ofnon-DBI decoder 504 as itsoutput DQ n 522. Thus, the data [DBI, DQn] is decoded using non-DBI decoding (step 410 ofFIG. 4 ). - Finally, when
mode signal 516 is at logic low ("0"), then theoutput 508 of ANDgate 506 is also always at logic low regardless of the state of the modified data mask signal (DM) 512, thereby causingmultiplexer 510 to always select theoutput 518 ofDBI decoder 502 as itsoutput DQ n 522. In addition, theoutput 528 ofOR gate 526 is always at logic high ifmode signal 516 is at logic low, and thus the data mask signal (dm) 532 output from ANDgate 530 follows the state of the modified data mask signal (DM) 512. Thus, the data [DBI, DQn] is always decoded using DBI decoding whenmode signal 516 is not asserted. In other words, whenmode signal 516 is at logic low, thedecoder 112 performs DBI decoding (that is independent of the use of masking information), and thus thedecoder 112 is completely backward compatible with conventional DBI decoding schemes. For example,mode signal 516 may stored as a value in a programmable configuration register or hard wired by means of a fuse or metal mask, etc. - With the encoding technique in accordance with the embodiments described herein, SSN can be reduced significantly and AC current drawn from the power supply may also be reduced significantly compared to conventional encoding methods such as DBI. This is explained in more detail with reference to
FIGS. 6A and6B .FIG. 6A illustrates Hamming Weights (HWs) present in 9 bit data including 8 bit uncoded data and a DBI bit, andFIG. 6B illustrates Hamming Weights present in 9 bit coded data including a DBI bit and 8 bit coded data encoded according to one embodiment. - Referring to
FIG. 6A , the HW histogram illustrates the distribution of HWs in the 9-bit data including DBI (1 bit) and 8 bit uncoded data, and the HW histograms 602 whensuch uncoded 9 bit data is encoded using conventional DBI ([DBI + 8 bit DBI-encoded data]). Among the possible data patterns (29) of the 9-bit parallel uncoded data, there is 1 data pattern with HW=0, 9 data patterns with HW=1, 36 data patterns with HW=2, 84 data patterns with HW=3, 126 data patterns with HW=4, 126 data patterns with HW=5, 84 data patterns with HW=6, 36 data patterns with HW=7, 9 data pattern with HW=8, and 1 data pattern with HW=9. The maximum possible variation in the HWs in the 9-bit uncoded data pattern is thus 9 (between HW=0 and HW=9), which results in significant SSN if transmitted uncoded. - Still referring to
FIG. 6A , the HW histograms 602 illustrates that onlyHamming Weights 0 to 4 would be present when such 8 bit data is encoded using DBI ([DBI + 8 bit DBI-encoded data]), since data withHamming Weights 5 through 8 would be inverted. Among the possible data patterns (28) of the 9-bit parallel coded data, there is 1 data pattern with HW=0, 9 data patterns with HW=1, 36 data patterns with HW=2, 84 data patterns with HW=3 and 128 data patterns with HW=4. The maximum possible variation in the HWs in the 9-bit DBI-encoded data pattern is thus 4 (between HW=0 and HW=4), which results in reduced SSN compared to when the data is transmitted uncoded. - Referring to
FIG. 6B , the HW histogram 652 illustrates the distribution of HWs in the 9-bit data ([DBI + 8 bit encoded data]) including encoded according to the combined data mask and DBI encoding scheme as described above with reference toFIG. 2 . Among the possible data patterns (28) of the 9-bit parallel coded data, there are 5 data patterns with HW=3 (including the DQM pattern) and 252 data patterns with HW=4. The maximum possible variation in the HWs in the 9-bit data pattern is thus only 1 (between HW=3 and HW=4), which results in significant reduction of SSN compared to the SSN when the data is transmitted uncoded or conventional DBI-coded. - These advantages are shown more specifically in Table 2 below, which shows the current (Idd) that would be drawn by transmitter (Tx) 108 (
FIG. 1 ) when the data Dn is transmitted uncoded, conventional DBI-coded, and coded with combined DM/DBI according to the embodiments herein, referencing the supply current Idd to be drawn when data Dn is transmitted uncoded as the reference (100%).Table 2 Idd Uncoded Conventional DBI Combined DM/DBI Coded Idd, DC-peak (%) 100% 50% 50% Idd, DC-average (%) 100% 40% 45% Idd, AC peak-peak (%) 100% 50% 25% Idd, AC rms (%) 100% 61% 13% - As shown in Table 2 above, the average DC supply current Idd increases slightly (from 40% to 45%) when the combined DM/DBI encoding scheme described herein is used, compared to conventional DBI encoding. This is because a large number of encoded data patterns are concentrated at high Hamming Weight (HW=4), thereby increasing the average DC current Idd drawn from the power supply (not shown). On the other hand, the AC supply current drawn from the power supply is reduced dramatically, from 50% to 25% for AC peak-to-peak supply current Idd and from 61% to 13% for AC rms (root-mean-square) values, when the combined DM/DBI encoding scheme according to the embodiments described herein is used, compared to conventional DBI encoding. Thus, SSO noise can be dramatically reduced when using the combined DM/DBI encoding scheme according to the embodiments described herein.
- Upon reading this disclosure, those of ordinary skill in the art will appreciate still additional alternative structural and functional designs for encoding data to reduce SSO noise, through the disclosed principles of the present disclosure. Thus, while particular embodiments and applications of the present disclosure have been illustrated and described, it is to be understood that the disclosure is not limited to the precise construction and components disclosed herein. Various modifications, changes and variations which will be apparent to those skilled in the art may be made in the arrangement, operation and details of the method and apparatus of the present disclosure disclosed herein without departing from the scope of the disclosure as defined in the appended claims.
Claims (8)
- A memory controller (102) to control the operation of a DRAM memory device (104), the memory controller (102) comprising:an encoder (106) to generate encoded data (DQ) and a data mask signal (DM) that accompanies the encoded data (DQ), wherein the encoder (106) is configured to:(i) if the encoded data (DQ) is to be masked by the DRAM memory device (104), generate the encoded data (DQ) as a predetermined bit pattern and generate the data mask signal (DM) to have a first state;(ii) if the encoded data (DQ) is to be inverted and written to an array in the DRAM memory device (104), generate the encoded data (DQ) as inverted data and generate the data mask signal (DM) to have a second state;(iii) if the encoded data (DQ) is to be non-inverted and written to the array in the DRAM memory device (104), generate the encoded data as non-inverted data and generate the data mask signal (DM) to have the first state; anda transmitter (108) configured to transmit the encoded data (DQ) and the data mask signal (DM) to the DRAM memory device (104).
- The memory controller (102) according to claim 1, wherein the encoder is adapted to receive a mode signal (116), wherein(a) if the mode signal defines a first state, the encoder is configured to perform steps (i) to (iii); and(b) if the mode signal defines a second state, the encoder is configured to generate the encoded data using data bus inversion.
- A DRAM memory device (104), comprising:an array to store data;a receiver (110) configured to receive encoded data (DQ) and a data mask signal (DM) that accompanies the encoded data (DQ) from a memory controller (102); anda decoder (112) configured to decode the encoded data (DQ) and the data mask signal (DM) to generate data (Dn),
wherein the decoder (112) is further configured to:(i) if the data mask signal (DM) is in a first state and the encoded data matches a predetermined bit pattern, mask the encoded data (DQ) received from said memory controller (102) from being written to the array;(ii) if the data mask signal (DM) is in a second state, invert the encoded data before writing the data to the array in the DRAM memory device 20 (104);(iii) if the data mask signal (DM) is in the first state and the encoded data does not match the predetermined bit pattern, write the data (Dn) to the array in the DRAM memory device (104) without inversion. - The DRAM memory device (104) according to claim 2, further comprising a register that specifies a mode for the DRAM indicating how to use the encoded data (DQ) and the data mask signal (DM), wherein(a) if the mode defines a first state, the decoder is configured to perform steps (i) to (iii); and(b) if the mode defines a second state, the decoder is configured to invert the encoded data before writing the data to the array in the DRAM memory device (104) regardless of the data mask signal (DM).
- A method performed by a memory controller (102) for controlling the operation of a DRAM memory device (104), the method comprising the steps of:(i) generating encoded data (DQ) as a predetermined bit pattern and generating a data mask signal (DM) that accompanies the encoded data (DQ) having a first state, if the encoded data (DQ) is to be masked by the DRAM memory device (104);(ii) generating encoded data (DQ) as inverted data and generating a data mask signal (DM) that accompanies the encoded data (DQ) to have a second state, if the encoded data (DQ) is to be inverted and written to an array in the DRAM memory device (104);(iii) generating encoded data (DQ) as non-inverted data and generating a data mask signal (DM) that accompanies the encoded data (DQ) to have the first state, if the encoded data (DQ) is to be non-inverted and written to the array in the DRAM memory device (104); and(iv) transmitting the encoded data (DQ) and the data mask signal (DM) to the DRAM memory device (104).
- The method according to claim 5, wherein the method further comprises
receiving by the memory controller a mode signal prior to step (i);(a) if the mode signal defines a first state, performing steps (i) to (iv); and(b) if the mode signal defines a second state, generating encoded data as inverted data instead of steps (i) to (iii) before performing step (iv). - A method performed by a DRAM memory device (104) of receiving data from a memory controller (102), the method comprising the steps of:receiving encoded data (DQ) and a data mask signal (DM) that accompanies the encoded data (DQ) from a memory controller (102); anddecoding the encoded data (DQ) and the data mask signal (DM) to generate data (Dn),wherein the decoding comprises:(i) if the data mask signal (DM) is in a first state and the encoded data matches a predetermined bit pattern, masking the encoded data (DQ) received from said memory controller (102);(ii) if the data mask signal (DM) is in a second state, inverting the data before writing the data to the array in the DRAM memory device (104);(iii) if the data mask signal (DM) is in the first state and the data does not match the predetermined bit pattern, writing the data (DQ) to the array in the DRAM memory device (104).
- The method according to claim 7, wherein the method further comprises
obtaining from a register a mode for the DRAM indicating how to use the encoded data (DQ) and the data mask signal (DM),(a) if the mode defines a first state, performing steps (i) to (iii); and(b) if the mode defines a second state, inverting the data before writing the data to the array in the DRAM memory device (104) regardless of the data mask signal (DM).
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