EP3174099A1 - Organic light emitting diode display - Google Patents
Organic light emitting diode display Download PDFInfo
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- EP3174099A1 EP3174099A1 EP16187747.7A EP16187747A EP3174099A1 EP 3174099 A1 EP3174099 A1 EP 3174099A1 EP 16187747 A EP16187747 A EP 16187747A EP 3174099 A1 EP3174099 A1 EP 3174099A1
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- thin film
- film transistor
- light emitting
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- 239000010409 thin film Substances 0.000 claims abstract description 91
- 239000003990 capacitor Substances 0.000 claims description 118
- 230000003071 parasitic effect Effects 0.000 claims description 32
- 230000001419 dependent effect Effects 0.000 claims 1
- 230000003068 static effect Effects 0.000 description 20
- 230000005684 electric field Effects 0.000 description 11
- 230000004044 response Effects 0.000 description 8
- 230000008859 change Effects 0.000 description 7
- 230000000694 effects Effects 0.000 description 7
- 208000033361 autosomal recessive with axonal neuropathy 2 spinocerebellar ataxia Diseases 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- 150000002894 organic compounds Chemical class 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/126—Shielding, e.g. light-blocking means over the TFTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
Definitions
- the present invention relates to an organic light emitting diode display.
- the flat panel displays include liquid crystal displays (LCDs), field emission displays (FEDs), plasma display panels (PDPs), organic light emitting diode displays (OLEDs), etc.
- LCDs liquid crystal displays
- FEDs field emission displays
- PDPs plasma display panels
- OLEDs organic light emitting diode displays
- the organic light emitting diode displays are self-luminous displays that emit light through excitation of organic compounds.
- the organic light emitting diode displays work without a backlight; thus, organic light emitting diode displays can be lighter and thinner and made in a simplified process.
- the organic light emitting diode displays are widely used because they can be manufactured at low temperatures, have a fast response time of 1 ms or less, and feature low power consumption, wide viewing angle, and high contrast.
- An organic light emitting diode display comprises an organic light emitting diode that converts electrical energy into light energy.
- the organic light emitting diode comprises an anode, a cathode, and an organic emission layer situated between the anode and cathode.
- a hole is ejected from the anode, and an electron is ejected from the cathode.
- EML organic emission layer
- each pixel comprises a switching thin film transistor and a driving thin film transistor, in order to apply a driving signal to the anode in a display area.
- the switching thin film transistor functions to select a pixel.
- the driving thin film transistor serves to drive the organic light emitting diode of the pixel selected by the switching thin film transistor.
- One pixel is defined by the intersection of a gate line, a data line, and a common power supply line.
- a switching thin film transistor, a driving thin film transistor, a storage capacitor, and an organic light emitting diode are formed, or located.
- the thin film transistors and the above-mentioned lines can be integrated thanks to the smaller pixel size, so they are arranged very close to each other.
- a parasitic capacitor is formed between the driving thin film transistor's gate electrode and a line adjacent to it, for example, a data line to which a data voltage is applied.
- the gate voltage applied to the gate electrode of the driving thin film transistor changes due to a change in the data voltage applied to the data line.
- a change in the gate voltage due to interference from the data voltage leads to a change in the gate-source voltage Vgs of the driving thin film transistor.
- the user will perceive this as a vertical crosstalk.
- the vertical crosstalk degrades the display quality and product reliability of the display device. Therefore, there is a need for an effort to solve this problem.
- the present invention is directed to an organic light emitting diode display that has a shielding electrode in order that a gate voltage applied to a driving thin film transistor's gate electrode is not affected by changes in the voltage of an adjacent line.
- An organic light emitting display including pixels in which each pixel has a driving thin film transistor for adjusting the current flowing through an organic light emitting diode based on a voltage applied to a gate electrode of the driving thin film transistor, the organic light emitting display further includes a signal line adjacent to the gate electrode of the driving thin film transistor; and a first shielding electrode located above the gate electrode of the driving thin film transistor, and a first insulating layer between the first shielding electrode and the gate electrode of the driving thin film transistor, wherein the first shielding electrode protrudes further towards the signal line than the gate electrode of the driving thin film transistor.
- the distance between the signal line and the first shielding electrode is shorter than the distance between the signal line and the gate electrode of the driving thin film transistor.
- the first shielding electrode may be configured to be connected to a first static voltage source.
- the first shielding electrode may be configured to be a first capacitor to suppress pixel voltage discharge. This suppression of pixel voltage discharge may improve the data maintainability of each pixel.
- the first capacitor may be formed by the overlapping of the first shielding electrode and the gate electrode of the driving thin film transistor.
- the first capacitor may have a higher capacitance than a parasitic capacitor that may be formed between the signal line and the gate electrode of the driving thin film transistor.
- the organic light emitting diode display may be as described above but further comprising: a second shielding electrode located below the gate electrode of the driving thin film transistor; and a second insulating layer between the second shielding electrode located below the gate electrode of the driving thin film transistor, wherein the second shielding electrode protrudes towards the signal line further than the gate electrode of the driving thin film transistor.
- the distance between the signal line and the second shielding electrode is shorter than the distance between the signal line and the gate electrode of the driving thin film transistor.
- the second shielding electrode may be configured to be connected to a second static voltage source.
- the second shielding electrode may be configured to be a second capacitor to suppress pixel voltage discharge. This suppression of pixel voltage discharge may improve the data maintainability of each pixel.
- the second capacitor may be formed by the overlapping of the second shielding electrode and the gate electrode of the driving thin film transistor.
- the second capacitor may have a higher capacitance than the parasitic capacitor that may be formed between the signal line and the gate electrode of the driving thin film transistor.
- the first static voltage source and the second static voltage source are the same.
- Each pixel may be configured in a six transistor and one capacitor structure.
- the six transistor and one capacitor structure may comprise:
- FIG. 1 is a view schematically illustrating an organic light emitting diode display according to the present invention.
- FIG. 2 is a configuration diagram schematically illustrating a pixel shown in FIG. 1 .
- FIG. 3 is a view showing an example of the circuit configuration of the pixel of FIG. 2 .
- an organic light emitting diode display 10 comprises a display driver circuit and a display panel DIS.
- the display driver circuit comprises a data drive circuit 12, a gate drive circuit 14, and a timing controller 16, and writes, or applies, a video data voltage of an input image in the pixels of the display panel DIS.
- the data drive circuit 12 converts digital video data RGB input from the timing controller 16 to an analog gamma compensation voltage to generate a data voltage.
- the data voltage output from the data drive circuit 12 is supplied to data lines D1 to Dm.
- the gate drive circuit 14 sequentially supplies a gate pulse synchronized with the data voltage to gate lines G1 to Gn and selects pixels from the display panel DIS to write, or apply, the data voltage.
- the timing controller 16 receives timing signals, such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, a main clock MCLK, etc., input from a host system 19, and synchronizes the timings of operation of the data drive circuit 12 and gate drive circuit 14.
- Data timing control signals for controlling the data drive circuit 12 include a source sampling clock SSC, a source output enable signal SOE, etc.
- Gate timing control signals for controlling the gate drive circuit 14 include a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, etc.
- the host system 19 may be implemented as one among a television system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system.
- the host system 19 comprises a system-on-chip (SoC) with a scaler embedded in it, and converts the digital video data RGB of the input image into a data format suitable for display on the display panel DIS.
- SoC system-on-chip
- the host system 19 transmits the digital video data RGB and the timing signals Vsync, Hsync, DE, and MCLK to the timing controller 16.
- a pixel array on the display panel DIS comprises pixels formed, or located, in pixel areas defined by the data lines D1 to Dm (m is a positive integer) and the gate lines G1 to Gn (n is a positive integer).
- Each pixel comprises an organic light emitting diode (hereinafter, OLED), which is a self-luminous element.
- a plurality of data lines D and a plurality of gate lines G cross each other on the display panel DIS, and pixels are arranged in a matrix at the crossings of the data lines D and the gate lines G.
- Each pixel comprise a driving thin film transistor (hereinafter, TFT) DT for controlling the amount of current flowing through the OLED, and a programming part SC for setting the gate-source voltage of the driving TFT DT.
- TFT driving thin film transistor
- the programming part SC may comprise at least one switching TFT and at least one storage capacitor.
- the switching TFT turns on in response to a scan signal from a gate line G to thereby apply a data voltage from a data line D to one electrode of the storage capacitor.
- the driving TFT DT adjusts the amount of light emitted by the OLED by controlling the amount of current supplied to the OLED based on the amount of voltage stored in the storage capacitor. The amount of light emitted by the OLED is proportional to the current supplied from the driving TFT DT.
- Such a pixel is connected to a high voltage source EVDD and a low voltage source EVSS and takes high voltage and low voltage from a power generator (not shown).
- the TFTs of the pixel may be implemented as p-type or n-type.
- a semiconductor layer for the TFTs of the pixel may comprise amorphous silicon, or polysilicon, or oxide.
- the OLED comprises an anode ANO, a cathode CAT, and an organic compound layer interposed between the anode ANO and the cathode CAT.
- the anode ANO is connected to the driving TFT DT.
- a pixel may consist of 6 transistors and 1 capacitor (6T1C).
- the pixel configuration of the present invention is not limited to the 6T1C structure. That is, the present invention may use all types of OLED pixel structures that adjust the current flowing through the OLED using the driving TFT.
- the TFTs included in the pixels to be described below are P-type TFTs, for example, but not limited thereto and may be N-type TFTs.
- the positions of source and drain electrodes may vary depending on the type of the TFTs, so the source and drain electrodes may be called a first electrode and a second electrode in the following description.
- a first TFT T1 comprises a gate electrode connected to a 1a gate line GL1a, a first electrode connected to a first data line DL1, and a second electrode connected to one end of a storage capacitor Cstg.
- the first TFT T1 serves to transmit a data signal supplied through the first data line DL1 to the storage capacitor Cstg, in response to a 1a gate signal SCAN1.
- a second TFT T2 comprises a gate electrode connected to a 1b gate line GL1b, a first electrode connected to a gate electrode of a driving TFT DT, and a second electrode connected to a second electrode of the driving TFT DT.
- the second TFT T2 connects the gate electrode and source electrode node of the driving TFT DT in a diode connection, in response to a 1b gate signal SCAN2.
- a third TFT T3 comprises a gate electrode connected to a 1c gate line GL1c, a first electrode connected to a reference voltage line VREF, and a second electrode connected to one end of the storage capacitor Cst.
- the third TFT T3 serves to supply a reference voltage Vref (or compensating voltage) to one end of the storage capacitor Cstg, in response to a 1c gate signal EM.
- a fourth TFT T4 comprises a gate electrode connected to a 1c gate line GL1c, a first electrode connected to the second electrode of the driving TFT DT, and a second electrode connected to the anode of the organic light emitting diode OLED.
- the fourth TFT T4 serves to transmit driving current to the organic light emitting diode OLED to make it emit light, in response to the 1b gate signal SCAN2.
- a fifth TFT T5 comprises a gate electrode connected to the 1b gate line GL1b, a first electrode connected to the reference voltage line VREF, and a second electrode connected to the anode of the organic light emitting diode OLED.
- the fifth TFT T5 serves to supply the reference voltage Vref to the anode of the organic light emitting diode OLED, in response to the 1b gate signal SCAN2.
- the driving TFT DT comprises the gate electrode connected to the other end of the storage capacitor Cstg, a first electrode connected to a first power supply (or high voltage source) EVDD, and a second electrode connected to the first electrode of the fourth TFT T4.
- the driving TFT DT turns on in response to a data voltage supplied from the storage capacitor Cstg and generates driving current to be supplied to the organic light emitting diode OLED.
- the organic light emitting diode OLED comprises the anode connected to the second electrode of the fourth TFT T4 and a cathode connected to a second power supply (or low voltage source) EVSS.
- the organic light emitting diode OLED emits light by the driving current transmitted through the fourth TFT T4.
- a parasitic capacitor Cgd is formed between the gate electrode of the driving TFT DT and an adjacent line.
- the adjacent line refers to a line to which a signal different from the gate voltage applied to the gate electrode of the driving TFT DT is applied.
- the parasitic capacitor Cgd may be formed between the gate electrode of the driving TFT DT and a first data line DL1.
- the parasitic capacitor may cause degradation of the display quality of the display device, including nonuniform luminance. This problem can be especially critical because many elements and lines are disposed adjacent to one another in a display device with high resolution.
- FIG. 4 is a top plan view schematically illustrating a driving TFT of a pixel and an area adjacent to it, in an organic light emitting diode display. It should be noted that FIG. 4 only schematically illustrates the distinctive elements of the present invention, i.e., the gate electrode of the driving TFT and adjacent signal lines, for convenience of explanation.
- the gate electrode DG of the driving TFT and signal lines adjacent to the gate electrode DG are formed, or located, in a pixel in the organic light emitting diode display.
- the signal lines may comprise a first data line DL1, a first power supply line VDL, a 1a gate line GL1a, a 1b gate line GL1b, and a 1c gate line GL1c.
- a data voltage is applied to the first data line DL1.
- a high voltage is applied to the first power supply line VDL.
- Gate signals from the gate drive circuit are applied to the 1a gate line GL1a, 1b gate line GL1b, and 1c gate line GL1c.
- the driving TFT DT adjusts the amount of current flowing through the organic light emitting diode OLED based on the gate-source voltage Vgs. Since the gate electrode DG of the driving TFT DT and the first data line DL1 are coupled due to the parasitic capacitor Cgd between the gate electrode DG and the first data line DL1, an electrical field may form between the first data line DL1 and the gate electrode DG of the driving TFT DT.
- the gate-source voltage Vs of the driving TFT DT changes with a change in the data voltage applied to the first data line DL1, thus causing a change in the luminance of the pixel. Hence, the user will perceive a vertical crosstalk.
- parasitic capacitors Cgg1, Cgg2, and Cge may be formed between the gate electrode DG of the driving TFT DT and the 1a gate line GL1a, between the gate electrode DG of the driving TFT DT and the 1b gate line GL1b, and between the gate electrode DG of the driving TFT DT and the 1c gate line GL1c, and the above-described problem may occur due to the parasitic capacitors Cgg1, Cgg2, and Cge.
- the present invention is characterized by having a shielding electrode, in order that a gate voltage applied to the driving TFT's gate electrode is not affected by changes in the voltage of an adjacent line.
- the present invention involves an organic light emitting diode display that is devised to shield an electric field generated between the gate electrode of the driving TFT and an adjacent line.
- each pixel has a driving thin film transistor that adjusts the current flowing through the organic light emitting diode based on a voltage applied to the gate electrode.
- the organic light emitting diode display according to the present invention comprise the driving thin film transistor's gate electrode, a signal line adjacent to the gate electrode of the driving thin film transistor, and a first shielding electrode located above the gate electrode of the driving thin film transistor, with a first insulating layer between them.
- the insulating layer is between the first shielding electrode and the gate electrode of the driving thin film transistor.
- the first shielding electrode protrudes towards the signal line further than the gate electrode. The distance between the signal line and the first shielding electrode may be shorter than the distance between the signal line and the gate electrode.
- the signal line refers to a line to which a signal (or voltage) different from the gate voltage applied to the gate electrode of the driving thin film transistor is applied.
- the first shielding electrode is connected to a static voltage source.
- a static voltage source may also be referred to as a constant voltage source.
- the organic light emitting diode display according to the present invention may further comprise a second shielding electrode.
- the second shielding electrode is located below the gate electrode of the driving thin film transistor, with a second insulating layer between them.
- the second shielding electrode protrudes towards the signal line further than the gate electrode of the driving thin film transistor.
- the distance between the signal line and the second shielding electrode may be shorter than the distance between the signal line and the gate electrode.
- the signal line refers to a line to which a signal different from the gate voltage applied to the gate electrode of the driving thin film transistor is applied.
- the second shielding electrode is connected to a static voltage source. As above, a static voltage source may also be referred to as a constant voltage source.
- the organic light emitting diode display according to the present invention comprises a first capacitor.
- the first capacitor is formed by the overlapping of the first shielding electrode and the gate electrode of the driving thin film transistor, with an insulating layer between them.
- the first capacitor has a higher capacitance than a parasitic capacitor formed between the gate electrode of the driving thin film transistor and an adjacent signal line.
- the organic light emitting diode display according to the present invention may further comprise a second capacitor.
- the second capacitor is formed by the overlapping of the second shielding electrode and the gate electrode of the driving thin film transistor, with an insulating layer between them.
- the second capacitor has a higher capacitance than a parasitic capacitor formed between the gate electrode of the driving thin film transistor and an adjacent signal line.
- FIG. 5 is a top plan view schematically illustrating a driving TFT of a pixel and an area adjacent to it, in the organic light emitting diode display according to the first exemplary embodiment of the present invention.
- FIG. 6 is a cross-sectional view taken along I-I' of FIG. 5 .
- FIG. 5 only schematically illustrates the distinctive elements of the present invention, i.e., the gate electrode of the driving TFT and adjacent signal lines, for convenience of explanation.
- the gate electrode DG of the driving TFT and a plurality of signal lines adjacent to the gate electrode DG are formed, or located, in a pixel in the organic light emitting diode display.
- the signal lines may comprise a first data line DL1, a first power supply line VDL, a 1a gate line GL1a, a 1b gate line GL1b, and a 1c gate line GL1c.
- a data voltage is applied to the first data line DL1.
- Gate signals from the gate drive circuit are applied to the 1a gate line GL1a, 1b gate line GL1b, and 1c gate line GL1c.
- the gate electrode of the driving TFT DT is located on a substrate SUB.
- a first insulating layer IN1 may be further formed, or located, under the gate electrode DG.
- the first data line DL1 is located above the gate electrode DG of the driving TFT DT, spaced horizontally apart from the gate electrode DG with a second insulating layer IN2 and a third insulating layer IN3 interposed between them.
- a parasitic capacitor Cgd is formed between the gate electrode DG of the driving TFT DT and the first data line DL1.
- the organic light emitting diode display according to the first exemplary embodiment of the present invention further comprises a first shielding electrode TM formed, or located, between the gate electrode DG of the driving TFT DT and the first data line DL1.
- the first shielding electrode TM is located on a different layer than the gate electrode DG of the driving TFT DT, with the second insulating layer IN2 between them.
- the first shielding electrode TM is located on a different layer than the first data line DL1, with the third insulating layer IN3 between them.
- the first shielding electrode TM overlaps the gate electrode DG of the driving DFT DT in such a way that fully covers the end of the gate electrode DG adjacent to the first data line DL1.
- the end of the first shielding electrode TM extends further towards the first data line DL1 than the end of the gate electrode DG. Accordingly, the end of the first shielding electrode TM is located horizontally more adjacent to the first data line DL1 than the end of the gate electrode DG.
- the first shielding electrode TM is connected to a static voltage source.
- the static voltage source may be a high voltage source EVDD.
- the first shielding electrode TM may be electrically connected to the first power supply line VDL through a first contact hole TH.
- the first shielding electrode TM When the first shielding electrode TM is connected to the static voltage source, the first shielding electrode TM maintains a static voltage.
- a first capacitor C1 is formed between the first shielding electrode TM and the gate electrode DG of the driving TFT DT. That is, the first shielding electrode TM and the gate electrode DG of the driving TFT DT overlap each other, with the second insulating layer IN2 between them, thereby forming the first capacitor C1 between them.
- the gate voltage at the gate electrode DG is affected by a capacitor with a relatively high capacitance.
- the first capacitor C1 has a higher capacitance value than the parasitic capacitor Cgd between the driving TFT DT of the first data line DL1 and the gate electrode DG, and this reduces the effect of the parasitic capacitor Cgd on the gate electrode DG of the driving TFT DT. Due to this, the gate voltage at the driving TFT DT is not affected by the parasitic capacitor Cgd; thus, it is not sensitive to changes in data voltage.
- the voltage at the first shielding electrode TM connected to the first capacitor C1 is constant, it is not affected by the voltage at the first shielding electrode TM even though the gate electrode DG of the driving TFT DT is coupled to the first shielding electrode TM through the first capacitor C1.
- the first shielding electrode TM protrudes further towards the first data line DL1 than the gate electrode DG of the driving TFT DT so as to overlap the gate electrode DG over a wide area.
- the first shielding electrode TM extending further towards the first data line DL1 provides electric field (E) shielding effect.
- the first shielding electrode TM may exist between the gate electrode DG of the driving TFT DT and the first data line DL1 to shield an electric field E formed between them, thereby keeping the gate voltage at the driving TFT DT from being affected by the data voltage.
- the end IS_T of the first shielding electrode TM protrudes further towards the first data line DL1 than the end IS_G of the gate electrode DG, in order to give the first capacitor C1 a higher capacitance value than that of the parasitic capacitor Cgd and to shield an electric field E formed between the gate electrode DG of the driving TFT DT and the first data line DL1.
- the present invention can minimize the effect of the data voltage on the gate electrode DG of the driving TFT DT and, as a result, prevent a vertical crosstalk that occurs when the gate voltage at the driving TFT DT changes with a change in data voltage.
- the first capacitor C1 formed between the first shielding electrode TM and the gate electrode DG of the driving TFT DT functions as a storage capacitor. It is preferable that the first shielding electrode TM overlaps the gate electrode DG of the driving TFT DT over a wide area, in order for the storage capacitor to have a sufficient capacitance. Therefore, with the storage capacitor having a sufficient capacitance, the present invention can improve the data maintainability of the pixels and suppress pixel voltage discharge when the pixels run at a low refresh rate for reduced power consumption, thereby enhancing the picture quality even with the low refresh rate.
- the present invention is characterized by having a first shielding electrode TM, in order that a gate voltage applied to the driving TFT DT's gate electrode DG is not affected by changes in the voltage of an adjacent line.
- the adjacent line is not limited to the above-described data line to which a data voltage is applied.
- the adjacent line may include any line, as long as a signal different from the gate voltage applied to the gate electrode DG of the driving TFT DT is applied to the adjacent line and the adjacent line is located adjacent to the gate electrode DG of the driving TFT DT.
- the adjacent line may include the 1a gate line GL1a, the 1b gate line GL1b, and the 1c gate line GL1c.
- FIG. 7 is a top plan view schematically illustrating a driving TFT of a pixel and an area adjacent to it, in an organic light emitting diode display according to a second exemplary embodiment of the present invention.
- FIG. 8 is a cross-sectional view taken along II-II' of FIG. 7 .
- FIG. 7 only schematically illustrates the distinctive elements of the present invention, i.e., the gate electrode of the driving TFT and adjacent signal lines, for convenience of explanation.
- the gate electrode DG of the driving TFT and a plurality of signal lines adjacent to the gate electrode DG are formed, or located, in a pixel in the organic light emitting diode display.
- the signal lines may comprise a first data line DL1, a first power supply line VDL, a 1a gate line GL1a, a 1b gate line GL1b, and a 1c gate line GL1c.
- a data voltage is applied to the first data line DL1.
- Gate signals from the gate drive circuit are applied to the 1a gate line GL1a, 1b gate line GL1b, and 1c gate line GL1c.
- the gate electrode of the driving TFT DT is located on a substrate SUB.
- a first insulating layer IN1 may be further formed, or located, under the gate electrode DG.
- the first data line DL1 is located above the gate electrode DG of the driving TFT DT, spaced horizontally apart from the gate electrode DG with a second insulating layer IN2 and a third insulating layer IN3 interposed between them.
- a parasitic capacitor Cgd is formed between the gate electrode DG of the driving TFT DT and the first data line DL1.
- the organic light emitting diode display according to the second exemplary embodiment of the present invention further comprises a first shielding electrode TM and a second shielding electrode BM.
- the first shielding electrode TM is provided above the gate electrode DG of the driving TFT DT.
- the first shielding electrode TM is provided between the gate electrode DG of the driving TFT DT and the first data line DL1.
- the first shielding electrode TM is located on a different layer than the gate electrode DG of the driving TFT DT, with the second insulating layer IN2 between them.
- the first shielding electrode TM is located on a different layer than the first data line DL1, with the third insulating layer IN3 between them
- the first shielding electrode TM overlaps the gate electrode DG of the driving DFT DT in such a way that fully covers the end IS_G of the gate electrode DG adjacent to the first data line DL1.
- the end IS_T of the first shielding electrode TM extends further towards the first data line DL1 than the end IS_G of the gate electrode DG. Accordingly, the end IS_T of the first shielding electrode TM is located horizontally more adjacent to the first data line DL1 than the end IS_G of the gate electrode DG does.
- the first shielding electrode TM is connected to a static voltage source.
- the first shielding electrode TM may be connected to a constant voltage source.
- the static voltage source may be a high voltage source EVDD.
- the first shielding electrode TM may be electrically connected to the first power supply line VDL through a first contact hole TH.
- the second shielding electrode BM is provided below the gate electrode DG of the driving TFT DT.
- the second shielding electrode BM is located on a different layer than the gate electrode DG of the driving TFT DT, with the first insulating layer IN1 between them.
- the second shielding electrode BM overlaps the gate electrode DG of the driving DFT DT.
- the end IS_B of the second shielding electrode BM extends further towards the first data line DL1 than the end IS_G of the gate electrode DG. Accordingly, the end IS_B of the second shielding electrode BM is located horizontally more adjacent to the first data line DL1 than the end IS_G of the gate electrode DG.
- the second shielding electrode BM is connected to a static voltage source.
- the second shielding electrode BM may be connected to a constant voltage source.
- the static voltage source may be a high voltage source EVDD.
- the second shielding electrode BM may be electrically connected to the first power supply line VDL through a second contact hole BH.
- a first capacitor C1 is formed between the first shielding electrode TM and the gate electrode DG of the driving TFT DT. That is, the first shielding electrode TM and the gate electrode DG of the driving TFT DT overlap each other, with the second insulating layer IN2 between them, thereby forming the first capacitor C1 between them.
- a second capacitor C2 is formed between the second shielding electrode BM and the gate electrode DG of the driving TFT DT. That is, the second shielding electrode BM and the gate electrode DG of the driving TFT DT overlap each other, with the first insulating layer IN1 between them, thereby forming the second capacitor C2 between them.
- the gate voltage at the gate electrode DG is affected by a capacitor with a relatively high capacitance.
- the first capacitor C1 and the second capacitor C2 have a higher capacitance value than the parasitic capacitor Cgd between the first data line DL1 and the gate electrode DG of the driving TFT DT, and this reduces the effect of the parasitic capacitor Cgd on the gate electrode DG of the driving TFT DT. Due to this, the gate voltage at the driving TFT DT is not affected by the parasitic capacitor Cgd; thus, it is not sensitive to changes in data voltage.
- the voltage at the first shielding electrode TM connected to the first capacitor C1 is constant, it is not affected by the voltage at the first shielding electrode TM even though the gate electrode DG of the driving TFT DT is coupled to the first shielding electrode TM through the first capacitor C1.
- the first shielding electrode TM protrudes further towards the first data line DL1 than the gate electrode DG of the driving TFT DT so as to overlap the gate electrode DG over a wide area.
- the second shielding electrode BM connected to the second capacitor C2 Since the voltage at the second shielding electrode BM connected to the second capacitor C2 is constant, it is not affected by the voltage at the second shielding electrode BM even though the gate electrode DG of the driving TFT DT is coupled to the second shielding electrode BM through the second capacitor C2.
- the second capacitor C2 in order for the second capacitor C2 to have a higher capacitance than the parasitic capacitor Cgd, it is preferable that the second shielding electrode BM protrudes further towards the first data line DL1 than the gate electrode DG of the driving TFT DT so as to overlap the gate electrode DG over a wide area.
- the first shielding electrode TM extending further towards the first data line DL1 provides electric field (E) shielding effect in the upward direction from the gate electrode DG of the driving TFT DT.
- the first shielding electrode TM may exist between the gate electrode DG of the driving TFT DT and the first data line DL1 to shield an upward electric field E formed between them, thereby keeping the gate voltage at the driving TFT DT from being affected by the data voltage.
- the second shielding electrode BM extending further towards the first data line DL1 provides electric field (E) shielding effect in the downward direction from the gate electrode DG of the driving TFT DT.
- the second shielding electrode BM may exist below the gate electrode DG of the driving TFT DT to shield a downward electric field E formed between them, thereby keeping the gate voltage at the driving TFT DT from being affected by the data voltage.
- the end IS_T of the first shielding electrode TM protrudes further towards the first data line DL1 than the end IS_G of the gate electrode DG, in order to give the first capacitor C1 a higher capacitance value than that of the parasitic capacitor Cgd and to shield the upward electric field E formed between the gate electrode DG of the driving TFT DT and the first data line DL1.
- the end IS_B of the second shielding electrode BM protrudes further towards the first data line DL1 than the end IS_G of the gate electrode DG, in order to give the second capacitor C2 a higher capacitance value than that of the parasitic capacitor Cgd and to shield the downward electric field E formed between the gate electrode DG of the driving TFT DT and the first data line DL1.
- the present invention can minimize the effect of the data voltage on the gate electrode DG of the driving TFT DT and, as a result, prevent a vertical crosstalk that occurs when the gate voltage at the driving TFT DT changes with a change in data voltage.
- the first capacitor C1 and the second capacitor C2 both function as a storage capacitor. It is preferable that both the first shielding electrode TM and the second shielding electrode BM overlap the gate electrode DG of the driving TFT DT across a wide area, in order for the storage capacitor to have a sufficient capacitance. Therefore, with the storage capacitor having a sufficient capacitance, the present invention can improve the data maintainability of the pixels and suppress pixel voltage discharge when the pixels run at a low refresh rate for reduced power consumption, thereby enhancing the picture quality even with the low refresh rate.
- the present invention allows the storage capacitor to have a sufficient capacitance in a limited area since a dual storage capacitor can be formed, or located, vertically. Accordingly, the second exemplary embodiment of the present invention may be applicable to organic light emitting diode displays with high resolution that require a storage capacitor in a limited area.
- the second exemplary embodiment of the present invention is characterized by having a first shielding electrode TM and a second shielding electrode BM, in order that a gate voltage applied to the driving TFT DT's gate electrode DG is not affected by changes in the voltage of an adjacent line.
- the adjacent line is not limited to the above-described data line to which a data voltage is applied.
- the adjacent line may include any line, as long as a signal different from the gate voltage applied to the gate electrode DG of the driving TFT DT is applied to the adjacent line and the adjacent line is located adjacent to the gate electrode DG of the driving TFT DT.
- the adjacent line may include the 1a gate line GL1a, the 1b gate line GL1b, and the 1c gate line GL1c.
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Abstract
Description
- The present invention relates to an organic light emitting diode display.
- Recently, various flat panel displays that are less bulky and lighter than cathode ray tubes (CRTs) are being developed. Examples of the flat panel displays include liquid crystal displays (LCDs), field emission displays (FEDs), plasma display panels (PDPs), organic light emitting diode displays (OLEDs), etc. Among these types of flat panel displays, the organic light emitting diode displays are self-luminous displays that emit light through excitation of organic compounds. In contrast to LCDs the organic light emitting diode displays work without a backlight; thus, organic light emitting diode displays can be lighter and thinner and made in a simplified process. Also, the organic light emitting diode displays are widely used because they can be manufactured at low temperatures, have a fast response time of 1 ms or less, and feature low power consumption, wide viewing angle, and high contrast.
- An organic light emitting diode display comprises an organic light emitting diode that converts electrical energy into light energy. The organic light emitting diode comprises an anode, a cathode, and an organic emission layer situated between the anode and cathode. A hole is ejected from the anode, and an electron is ejected from the cathode. Once the hole from the anode and the electron from the cathode are injected into an organic emission layer EML, they form an exciton and this exciton releases its energy as light to emit light.
- In such an organic light emitting diode display, each pixel comprises a switching thin film transistor and a driving thin film transistor, in order to apply a driving signal to the anode in a display area. The switching thin film transistor functions to select a pixel. The driving thin film transistor serves to drive the organic light emitting diode of the pixel selected by the switching thin film transistor.
- In line with the rising demand for high resolution needed for larger display sizes, the pixel size is becoming smaller and smaller. One pixel is defined by the intersection of a gate line, a data line, and a common power supply line. In this pixel, a switching thin film transistor, a driving thin film transistor, a storage capacitor, and an organic light emitting diode are formed, or located. With this configuration, the thin film transistors and the above-mentioned lines can be integrated thanks to the smaller pixel size, so they are arranged very close to each other.
- A parasitic capacitor is formed between the driving thin film transistor's gate electrode and a line adjacent to it, for example, a data line to which a data voltage is applied. In this instance, the gate voltage applied to the gate electrode of the driving thin film transistor changes due to a change in the data voltage applied to the data line. A change in the gate voltage due to interference from the data voltage leads to a change in the gate-source voltage Vgs of the driving thin film transistor. The user will perceive this as a vertical crosstalk. The vertical crosstalk degrades the display quality and product reliability of the display device. Therefore, there is a need for an effort to solve this problem.
- Accordingly, the present invention is directed to an organic light emitting diode display that has a shielding electrode in order that a gate voltage applied to a driving thin film transistor's gate electrode is not affected by changes in the voltage of an adjacent line.
- An organic light emitting display including pixels in which each pixel has a driving thin film transistor for adjusting the current flowing through an organic light emitting diode based on a voltage applied to a gate electrode of the driving thin film transistor, the organic light emitting display further includes a signal line adjacent to the gate electrode of the driving thin film transistor; and a first shielding electrode located above the gate electrode of the driving thin film transistor, and a first insulating layer between the first shielding electrode and the gate electrode of the driving thin film transistor, wherein the first shielding electrode protrudes further towards the signal line than the gate electrode of the driving thin film transistor.
- Preferably, the distance between the signal line and the first shielding electrode is shorter than the distance between the signal line and the gate electrode of the driving thin film transistor.
- The first shielding electrode may be configured to be connected to a first static voltage source.
- The first shielding electrode may be configured to be a first capacitor to suppress pixel voltage discharge. This suppression of pixel voltage discharge may improve the data maintainability of each pixel.
- The first capacitor may be formed by the overlapping of the first shielding electrode and the gate electrode of the driving thin film transistor. The first capacitor may have a higher capacitance than a parasitic capacitor that may be formed between the signal line and the gate electrode of the driving thin film transistor.
- The organic light emitting diode display may be as described above but further comprising: a second shielding electrode located below the gate electrode of the driving thin film transistor; and a second insulating layer between the second shielding electrode located below the gate electrode of the driving thin film transistor, wherein the second shielding electrode protrudes towards the signal line further than the gate electrode of the driving thin film transistor.
- Preferably, the distance between the signal line and the second shielding electrode is shorter than the distance between the signal line and the gate electrode of the driving thin film transistor.
- The second shielding electrode may be configured to be connected to a second static voltage source.
- The second shielding electrode may be configured to be a second capacitor to suppress pixel voltage discharge. This suppression of pixel voltage discharge may improve the data maintainability of each pixel.
- The second capacitor may be formed by the overlapping of the second shielding electrode and the gate electrode of the driving thin film transistor. The second capacitor may have a higher capacitance than the parasitic capacitor that may be formed between the signal line and the gate electrode of the driving thin film transistor.
- In some cases, the first static voltage source and the second static voltage source are the same.
- Each pixel may be configured in a six transistor and one capacitor structure.
- The six transistor and one capacitor structure may comprise:
- a first thin film transistor comprising a gate electrode connected to a first gate line, a first electrode connected to a first data line, and a second electrode connected to one end of a storage capacitor;
- a second thin film transistor comprising a gate electrode connected to a second gate line, a first electrode connected to a gate electrode of the driving thin film transistor, and a second electrode connected to a second electrode of the driving thin film transistor ;
- a third thin film transistor comprising a gate electrode connected to a third gate line, a first electrode connected to a reference voltage line, and a second electrode connected to one end of the storage capacitor;
- a fourth thin film transistor comprising a gate electrode connected to a third gate line, a first electrode connected to the second electrode of the driving thin film transistor, and a second electrode connected to the anode of the organic light emitting diode;
- a fifth thin film transistor comprising a gate electrode connected to the second gate line, a first electrode connected to the reference voltage line, and a second electrode connected to the anode of the organic light emitting diode; and
- the driving thin film transistor comprising the gate electrode connected to the other end of the storage capacitor, a first electrode connected to a first power supply, and a second electrode connected to the first electrode of the fourth thin film transistor.
- The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawings:
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FIG. 1 is a view schematically illustrating an organic light emitting diode display according to the present invention; -
FIG. 2 is a configuration diagram schematically illustrating a pixel shown inFIG. 1 ; -
FIG. 3 is a view showing an example of the circuit configuration of the pixel ofFIG. 2 ; -
FIG. 4 is a top plan view schematically illustrating a driving TFT of a pixel and an area adjacent to it, in an organic light emitting diode display; -
FIG. 5 is a top plan view schematically illustrating a driving TFT of a pixel and an area adjacent to it, in an organic light emitting diode display according to a first exemplary embodiment of the present invention; -
FIG. 6 is a cross-sectional view taken along I-I' ofFIG. 5 ; -
FIG. 7 is a top plan view schematically illustrating a driving TFT of a pixel and an area adjacent to it, in an organic light emitting diode display according to a second exemplary embodiment of the present invention; and -
FIG. 8 is a cross-sectional view taken along II-II' ofFIG. 7 . - Reference will now be made in detail to embodiments illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. Detailed description of known arts will be omitted if it is determined that the arts can mislead the reader regarding the embodiments of the invention. In describing various embodiments, descriptions of the same or like parts may be given with respect to a particular exemplary embodiment and, in light of this description and for conciseness, may be omitted in other exemplary embodiments.
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FIG. 1 is a view schematically illustrating an organic light emitting diode display according to the present invention.FIG. 2 is a configuration diagram schematically illustrating a pixel shown inFIG. 1 .FIG. 3 is a view showing an example of the circuit configuration of the pixel ofFIG. 2 . - Referring to
FIG. 1 , an organic light emittingdiode display 10 according to the present invention comprises a display driver circuit and a display panel DIS. - The display driver circuit comprises a
data drive circuit 12, agate drive circuit 14, and atiming controller 16, and writes, or applies, a video data voltage of an input image in the pixels of the display panel DIS. The data drivecircuit 12 converts digital video data RGB input from thetiming controller 16 to an analog gamma compensation voltage to generate a data voltage. The data voltage output from the data drivecircuit 12 is supplied to data lines D1 to Dm. Thegate drive circuit 14 sequentially supplies a gate pulse synchronized with the data voltage to gate lines G1 to Gn and selects pixels from the display panel DIS to write, or apply, the data voltage. - The
timing controller 16 receives timing signals, such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, a main clock MCLK, etc., input from ahost system 19, and synchronizes the timings of operation of the data drivecircuit 12 andgate drive circuit 14. Data timing control signals for controlling the data drivecircuit 12 include a source sampling clock SSC, a source output enable signal SOE, etc. Gate timing control signals for controlling thegate drive circuit 14 include a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, etc. - The
host system 19 may be implemented as one among a television system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system. Thehost system 19 comprises a system-on-chip (SoC) with a scaler embedded in it, and converts the digital video data RGB of the input image into a data format suitable for display on the display panel DIS. Thehost system 19 transmits the digital video data RGB and the timing signals Vsync, Hsync, DE, and MCLK to thetiming controller 16. - A pixel array on the display panel DIS comprises pixels formed, or located, in pixel areas defined by the data lines D1 to Dm (m is a positive integer) and the gate lines G1 to Gn (n is a positive integer). Each pixel comprises an organic light emitting diode (hereinafter, OLED), which is a self-luminous element.
- Referring further to
FIG. 2 , a plurality of data lines D and a plurality of gate lines G cross each other on the display panel DIS, and pixels are arranged in a matrix at the crossings of the data lines D and the gate lines G. Each pixel comprise a driving thin film transistor (hereinafter, TFT) DT for controlling the amount of current flowing through the OLED, and a programming part SC for setting the gate-source voltage of the driving TFT DT. - The programming part SC may comprise at least one switching TFT and at least one storage capacitor. The switching TFT turns on in response to a scan signal from a gate line G to thereby apply a data voltage from a data line D to one electrode of the storage capacitor. The driving TFT DT adjusts the amount of light emitted by the OLED by controlling the amount of current supplied to the OLED based on the amount of voltage stored in the storage capacitor. The amount of light emitted by the OLED is proportional to the current supplied from the driving TFT DT. Such a pixel is connected to a high voltage source EVDD and a low voltage source EVSS and takes high voltage and low voltage from a power generator (not shown). The TFTs of the pixel may be implemented as p-type or n-type. Also, a semiconductor layer for the TFTs of the pixel may comprise amorphous silicon, or polysilicon, or oxide. The OLED comprises an anode ANO, a cathode CAT, and an organic compound layer interposed between the anode ANO and the cathode CAT. The anode ANO is connected to the driving TFT DT.
- Referring to
FIG. 3 , a pixel may consist of 6 transistors and 1 capacitor (6T1C). However, the pixel configuration of the present invention is not limited to the 6T1C structure. That is, the present invention may use all types of OLED pixel structures that adjust the current flowing through the OLED using the driving TFT. - The TFTs included in the pixels to be described below are P-type TFTs, for example, but not limited thereto and may be N-type TFTs. The positions of source and drain electrodes may vary depending on the type of the TFTs, so the source and drain electrodes may be called a first electrode and a second electrode in the following description.
- A first TFT T1 comprises a gate electrode connected to a 1a gate line GL1a, a first electrode connected to a first data line DL1, and a second electrode connected to one end of a storage capacitor Cstg. The first TFT T1 serves to transmit a data signal supplied through the first data line DL1 to the storage capacitor Cstg, in response to a 1a gate signal SCAN1.
- A second TFT T2 comprises a gate electrode connected to a 1b gate line GL1b, a first electrode connected to a gate electrode of a driving TFT DT, and a second electrode connected to a second electrode of the driving TFT DT. The second TFT T2 connects the gate electrode and source electrode node of the driving TFT DT in a diode connection, in response to a 1b gate signal SCAN2.
- A third TFT T3 comprises a gate electrode connected to a 1c gate line GL1c, a first electrode connected to a reference voltage line VREF, and a second electrode connected to one end of the storage capacitor Cst. The third TFT T3 serves to supply a reference voltage Vref (or compensating voltage) to one end of the storage capacitor Cstg, in response to a 1c gate signal EM.
- A fourth TFT T4 comprises a gate electrode connected to a 1c gate line GL1c, a first electrode connected to the second electrode of the driving TFT DT, and a second electrode connected to the anode of the organic light emitting diode OLED. The fourth TFT T4 serves to transmit driving current to the organic light emitting diode OLED to make it emit light, in response to the 1b gate signal SCAN2.
- A fifth TFT T5 comprises a gate electrode connected to the 1b gate line GL1b, a first electrode connected to the reference voltage line VREF, and a second electrode connected to the anode of the organic light emitting diode OLED. The fifth TFT T5 serves to supply the reference voltage Vref to the anode of the organic light emitting diode OLED, in response to the 1b gate signal
SCAN2. - The driving TFT DT comprises the gate electrode connected to the other end of the storage capacitor Cstg, a first electrode connected to a first power supply (or high voltage source) EVDD, and a second electrode connected to the first electrode of the fourth TFT T4. The driving TFT DT turns on in response to a data voltage supplied from the storage capacitor Cstg and generates driving current to be supplied to the organic light emitting diode OLED.
- The organic light emitting diode OLED comprises the anode connected to the second electrode of the fourth TFT T4 and a cathode connected to a second power supply (or low voltage source) EVSS. The organic light emitting diode OLED emits light by the driving current transmitted through the fourth TFT T4.
- In this instance, a parasitic capacitor Cgd is formed between the gate electrode of the driving TFT DT and an adjacent line. The adjacent line refers to a line to which a signal different from the gate voltage applied to the gate electrode of the driving TFT DT is applied. For example, the parasitic capacitor Cgd may be formed between the gate electrode of the driving TFT DT and a first data line DL1. The parasitic capacitor may cause degradation of the display quality of the display device, including nonuniform luminance. This problem can be especially critical because many elements and lines are disposed adjacent to one another in a display device with high resolution.
- The above-mentioned problem will now be described concretely with further reference to
FIG. 4. FIG. 4 is a top plan view schematically illustrating a driving TFT of a pixel and an area adjacent to it, in an organic light emitting diode display. It should be noted thatFIG. 4 only schematically illustrates the distinctive elements of the present invention, i.e., the gate electrode of the driving TFT and adjacent signal lines, for convenience of explanation. - Referring to
FIG. 4 , the gate electrode DG of the driving TFT and signal lines adjacent to the gate electrode DG are formed, or located, in a pixel in the organic light emitting diode display. The signal lines may comprise a first data line DL1, a first power supply line VDL, a 1a gate line GL1a, a 1b gate line GL1b, and a 1c gate line GL1c. A data voltage is applied to the first data line DL1. A high voltage is applied to the first power supply line VDL. Gate signals from the gate drive circuit are applied to the 1a gate line GL1a, 1b gate line GL1b, and 1c gate line GL1c. - The driving TFT DT adjusts the amount of current flowing through the organic light emitting diode OLED based on the gate-source voltage Vgs. Since the gate electrode DG of the driving TFT DT and the first data line DL1 are coupled due to the parasitic capacitor Cgd between the gate electrode DG and the first data line DL1, an electrical field may form between the first data line DL1 and the gate electrode DG of the driving TFT DT. The gate-source voltage Vs of the driving TFT DT changes with a change in the data voltage applied to the first data line DL1, thus causing a change in the luminance of the pixel. Hence, the user will perceive a vertical crosstalk.
- This problem may be more severe between the gate electrode DG of the driving TFT DT and an adjacent line, as well as between the gate electrode DG of the driving TFT DT and the first data line DL1. For example, parasitic capacitors Cgg1, Cgg2, and Cge may be formed between the gate electrode DG of the driving TFT DT and the 1a gate line GL1a, between the gate electrode DG of the driving TFT DT and the 1b gate line GL1b, and between the gate electrode DG of the driving TFT DT and the 1c gate line GL1c, and the above-described problem may occur due to the parasitic capacitors Cgg1, Cgg2, and Cge.
- The present invention is characterized by having a shielding electrode, in order that a gate voltage applied to the driving TFT's gate electrode is not affected by changes in the voltage of an adjacent line. The present invention involves an organic light emitting diode display that is devised to shield an electric field generated between the gate electrode of the driving TFT and an adjacent line.
- In an organic light emitting diode display, each pixel has a driving thin film transistor that adjusts the current flowing through the organic light emitting diode based on a voltage applied to the gate electrode. The organic light emitting diode display according to the present invention comprise the driving thin film transistor's gate electrode, a signal line adjacent to the gate electrode of the driving thin film transistor, and a first shielding electrode located above the gate electrode of the driving thin film transistor, with a first insulating layer between them. Thus, the insulating layer is between the first shielding electrode and the gate electrode of the driving thin film transistor. The first shielding electrode protrudes towards the signal line further than the gate electrode. The distance between the signal line and the first shielding electrode may be shorter than the distance between the signal line and the gate electrode. The signal line refers to a line to which a signal (or voltage) different from the gate voltage applied to the gate electrode of the driving thin film transistor is applied. The first shielding electrode is connected to a static voltage source. A static voltage source may also be referred to as a constant voltage source.
- The organic light emitting diode display according to the present invention may further comprise a second shielding electrode. The second shielding electrode is located below the gate electrode of the driving thin film transistor, with a second insulating layer between them. The second shielding electrode protrudes towards the signal line further than the gate electrode of the driving thin film transistor. The distance between the signal line and the second shielding electrode may be shorter than the distance between the signal line and the gate electrode. The signal line refers to a line to which a signal different from the gate voltage applied to the gate electrode of the driving thin film transistor is applied. The second shielding electrode is connected to a static voltage source. As above, a static voltage source may also be referred to as a constant voltage source.
- The organic light emitting diode display according to the present invention comprises a first capacitor. The first capacitor is formed by the overlapping of the first shielding electrode and the gate electrode of the driving thin film transistor, with an insulating layer between them. The first capacitor has a higher capacitance than a parasitic capacitor formed between the gate electrode of the driving thin film transistor and an adjacent signal line.
- The organic light emitting diode display according to the present invention may further comprise a second capacitor. The second capacitor is formed by the overlapping of the second shielding electrode and the gate electrode of the driving thin film transistor, with an insulating layer between them. The second capacitor has a higher capacitance than a parasitic capacitor formed between the gate electrode of the driving thin film transistor and an adjacent signal line.
- The characteristics of the present invention will now be described concretely with exemplary embodiments of the present invention.
- An organic light emitting diode display according to a first exemplary embodiment of the present invention will be described below in detail with reference to
FIGS. 5 and6 .FIG. 5 is a top plan view schematically illustrating a driving TFT of a pixel and an area adjacent to it, in the organic light emitting diode display according to the first exemplary embodiment of the present invention.FIG. 6 is a cross-sectional view taken along I-I' ofFIG. 5 . - It should be noted that
FIG. 5 only schematically illustrates the distinctive elements of the present invention, i.e., the gate electrode of the driving TFT and adjacent signal lines, for convenience of explanation. - Referring to
FIGS. 5 and6 , the gate electrode DG of the driving TFT and a plurality of signal lines adjacent to the gate electrode DG are formed, or located, in a pixel in the organic light emitting diode display. For example, the signal lines may comprise a first data line DL1, a first power supply line VDL, a 1a gate line GL1a, a 1b gate line GL1b, and a 1c gate line GL1c. A data voltage is applied to the first data line DL1. A high voltage applied to the first power supply line VDL. Gate signals from the gate drive circuit are applied to the 1a gate line GL1a, 1b gate line GL1b, and 1c gate line GL1c. - The gate electrode of the driving TFT DT is located on a substrate SUB. A first insulating layer IN1 may be further formed, or located, under the gate electrode DG. The first data line DL1 is located above the gate electrode DG of the driving TFT DT, spaced horizontally apart from the gate electrode DG with a second insulating layer IN2 and a third insulating layer IN3 interposed between them. A parasitic capacitor Cgd is formed between the gate electrode DG of the driving TFT DT and the first data line DL1.
- The organic light emitting diode display according to the first exemplary embodiment of the present invention further comprises a first shielding electrode TM formed, or located, between the gate electrode DG of the driving TFT DT and the first data line DL1. The first shielding electrode TM is located on a different layer than the gate electrode DG of the driving TFT DT, with the second insulating layer IN2 between them. The first shielding electrode TM is located on a different layer than the first data line DL1, with the third insulating layer IN3 between them.
- The first shielding electrode TM overlaps the gate electrode DG of the driving DFT DT in such a way that fully covers the end of the gate electrode DG adjacent to the first data line DL1. In an area adjacent to the first data line DL1, the end of the first shielding electrode TM extends further towards the first data line DL1 than the end of the gate electrode DG. Accordingly, the end of the first shielding electrode TM is located horizontally more adjacent to the first data line DL1 than the end of the gate electrode DG.
- The first shielding electrode TM is connected to a static voltage source. For example, the static voltage source may be a high voltage source EVDD. To this end, the first shielding electrode TM may be electrically connected to the first power supply line VDL through a first contact hole TH.
- When the first shielding electrode TM is connected to the static voltage source, the first shielding electrode TM maintains a static voltage. A first capacitor C1 is formed between the first shielding electrode TM and the gate electrode DG of the driving TFT DT. That is, the first shielding electrode TM and the gate electrode DG of the driving TFT DT overlap each other, with the second insulating layer IN2 between them, thereby forming the first capacitor C1 between them.
- The greater the capacitance of a capacitor, the larger the amount of charge in the capacitor. When a plurality of capacitors are connected to the gate electrode DG of the driving TFT DT, the gate voltage at the gate electrode DG is affected by a capacitor with a relatively high capacitance. The first capacitor C1 has a higher capacitance value than the parasitic capacitor Cgd between the driving TFT DT of the first data line DL1 and the gate electrode DG, and this reduces the effect of the parasitic capacitor Cgd on the gate electrode DG of the driving TFT DT. Due to this, the gate voltage at the driving TFT DT is not affected by the parasitic capacitor Cgd; thus, it is not sensitive to changes in data voltage. Since the voltage at the first shielding electrode TM connected to the first capacitor C1 is constant, it is not affected by the voltage at the first shielding electrode TM even though the gate electrode DG of the driving TFT DT is coupled to the first shielding electrode TM through the first capacitor C1. In the present invention, in order for the first capacitor C1 to have a higher capacitance than the parasitic capacitor Cgd, it is preferable that the first shielding electrode TM protrudes further towards the first data line DL1 than the gate electrode DG of the driving TFT DT so as to overlap the gate electrode DG over a wide area.
- The first shielding electrode TM extending further towards the first data line DL1 provides electric field (E) shielding effect. In other words, the first shielding electrode TM may exist between the gate electrode DG of the driving TFT DT and the first data line DL1 to shield an electric field E formed between them, thereby keeping the gate voltage at the driving TFT DT from being affected by the data voltage.
- As discussed above, it is preferable that the end IS_T of the first shielding electrode TM protrudes further towards the first data line DL1 than the end IS_G of the gate electrode DG, in order to give the first capacitor C1 a higher capacitance value than that of the parasitic capacitor Cgd and to shield an electric field E formed between the gate electrode DG of the driving TFT DT and the first data line DL1. With the first shielding electrode TM extending further towards the first data line DL1, the present invention can minimize the effect of the data voltage on the gate electrode DG of the driving TFT DT and, as a result, prevent a vertical crosstalk that occurs when the gate voltage at the driving TFT DT changes with a change in data voltage.
- Moreover, the first capacitor C1 formed between the first shielding electrode TM and the gate electrode DG of the driving TFT DT functions as a storage capacitor. It is preferable that the first shielding electrode TM overlaps the gate electrode DG of the driving TFT DT over a wide area, in order for the storage capacitor to have a sufficient capacitance. Therefore, with the storage capacitor having a sufficient capacitance, the present invention can improve the data maintainability of the pixels and suppress pixel voltage discharge when the pixels run at a low refresh rate for reduced power consumption, thereby enhancing the picture quality even with the low refresh rate.
- The present invention is characterized by having a first shielding electrode TM, in order that a gate voltage applied to the driving TFT DT's gate electrode DG is not affected by changes in the voltage of an adjacent line. The adjacent line is not limited to the above-described data line to which a data voltage is applied. The adjacent line may include any line, as long as a signal different from the gate voltage applied to the gate electrode DG of the driving TFT DT is applied to the adjacent line and the adjacent line is located adjacent to the gate electrode DG of the driving TFT DT. For example, the adjacent line may include the 1a gate line GL1a, the 1b gate line GL1b, and the 1c gate line GL1c.
- An organic light emitting diode display according to a second exemplary embodiment of the present invention will be described below in detail with reference to
FIGS. 7 and8 .FIG. 7 is a top plan view schematically illustrating a driving TFT of a pixel and an area adjacent to it, in an organic light emitting diode display according to a second exemplary embodiment of the present invention.FIG. 8 is a cross-sectional view taken along II-II' ofFIG. 7 . - It should be noted that
FIG. 7 only schematically illustrates the distinctive elements of the present invention, i.e., the gate electrode of the driving TFT and adjacent signal lines, for convenience of explanation. - Referring to
FIGS. 7 and8 , the gate electrode DG of the driving TFT and a plurality of signal lines adjacent to the gate electrode DG are formed, or located, in a pixel in the organic light emitting diode display. For example, the signal lines may comprise a first data line DL1, a first power supply line VDL, a 1a gate line GL1a, a 1b gate line GL1b, and a 1c gate line GL1c. A data voltage is applied to the first data line DL1. A high voltage applied to the first power supply line VDL. Gate signals from the gate drive circuit are applied to the 1a gate line GL1a, 1b gate line GL1b, and 1c gate line GL1c. - The gate electrode of the driving TFT DT is located on a substrate SUB. A first insulating layer IN1 may be further formed, or located, under the gate electrode DG. The first data line DL1 is located above the gate electrode DG of the driving TFT DT, spaced horizontally apart from the gate electrode DG with a second insulating layer IN2 and a third insulating layer IN3 interposed between them. A parasitic capacitor Cgd is formed between the gate electrode DG of the driving TFT DT and the first data line DL1.
- The organic light emitting diode display according to the second exemplary embodiment of the present invention further comprises a first shielding electrode TM and a second shielding electrode BM.
- The first shielding electrode TM is provided above the gate electrode DG of the driving TFT DT. The first shielding electrode TM is provided between the gate electrode DG of the driving TFT DT and the first data line DL1. The first shielding electrode TM is located on a different layer than the gate electrode DG of the driving TFT DT, with the second insulating layer IN2 between them. The first shielding electrode TM is located on a different layer than the first data line DL1, with the third insulating layer IN3 between them
- The first shielding electrode TM overlaps the gate electrode DG of the driving DFT DT in such a way that fully covers the end IS_G of the gate electrode DG adjacent to the first data line DL1. In an area adjacent to the first data line DL1, the end IS_T of the first shielding electrode TM extends further towards the first data line DL1 than the end IS_G of the gate electrode DG. Accordingly, the end IS_T of the first shielding electrode TM is located horizontally more adjacent to the first data line DL1 than the end IS_G of the gate electrode DG does.
- The first shielding electrode TM is connected to a static voltage source. In other words, the first shielding electrode TM may be connected to a constant voltage source. For example, the static voltage source may be a high voltage source EVDD. To this end, the first shielding electrode TM may be electrically connected to the first power supply line VDL through a first contact hole TH.
- The second shielding electrode BM is provided below the gate electrode DG of the driving TFT DT. The second shielding electrode BM is located on a different layer than the gate electrode DG of the driving TFT DT, with the first insulating layer IN1 between them.
- The second shielding electrode BM overlaps the gate electrode DG of the driving DFT DT. In an area adjacent to the first data line DL1, the end IS_B of the second shielding electrode BM extends further towards the first data line DL1 than the end IS_G of the gate electrode DG. Accordingly, the end IS_B of the second shielding electrode BM is located horizontally more adjacent to the first data line DL1 than the end IS_G of the gate electrode DG.
- The second shielding electrode BM is connected to a static voltage source. In other words, the second shielding electrode BM may be connected to a constant voltage source. For example, the static voltage source may be a high voltage source EVDD. To this end, the second shielding electrode BM may be electrically connected to the first power supply line VDL through a second contact hole BH.
- When the first shielding electrode TM and the second shielding electrode BM are connected to the static voltage source, the first shielding electrode TM and the second shielding electrode BM maintain a static voltage. A first capacitor C1 is formed between the first shielding electrode TM and the gate electrode DG of the driving TFT DT. That is, the first shielding electrode TM and the gate electrode DG of the driving TFT DT overlap each other, with the second insulating layer IN2 between them, thereby forming the first capacitor C1 between them. A second capacitor C2 is formed between the second shielding electrode BM and the gate electrode DG of the driving TFT DT. That is, the second shielding electrode BM and the gate electrode DG of the driving TFT DT overlap each other, with the first insulating layer IN1 between them, thereby forming the second capacitor C2 between them.
- The greater the capacitance of a capacitor, the larger the amount of charge in the capacitor. When a plurality of capacitors are connected to the gate electrode DG of the driving TFT DT, the gate voltage at the gate electrode DG is affected by a capacitor with a relatively high capacitance. The first capacitor C1 and the second capacitor C2 have a higher capacitance value than the parasitic capacitor Cgd between the first data line DL1 and the gate electrode DG of the driving TFT DT, and this reduces the effect of the parasitic capacitor Cgd on the gate electrode DG of the driving TFT DT. Due to this, the gate voltage at the driving TFT DT is not affected by the parasitic capacitor Cgd; thus, it is not sensitive to changes in data voltage.
- Since the voltage at the first shielding electrode TM connected to the first capacitor C1 is constant, it is not affected by the voltage at the first shielding electrode TM even though the gate electrode DG of the driving TFT DT is coupled to the first shielding electrode TM through the first capacitor C1. In the present invention, in order for the first capacitor C1 to have a higher capacitance than the parasitic capacitor Cgd, it is preferable that the first shielding electrode TM protrudes further towards the first data line DL1 than the gate electrode DG of the driving TFT DT so as to overlap the gate electrode DG over a wide area.
- Since the voltage at the second shielding electrode BM connected to the second capacitor C2 is constant, it is not affected by the voltage at the second shielding electrode BM even though the gate electrode DG of the driving TFT DT is coupled to the second shielding electrode BM through the second capacitor C2. In the present invention, in order for the second capacitor C2 to have a higher capacitance than the parasitic capacitor Cgd, it is preferable that the second shielding electrode BM protrudes further towards the first data line DL1 than the gate electrode DG of the driving TFT DT so as to overlap the gate electrode DG over a wide area.
- The first shielding electrode TM extending further towards the first data line DL1 provides electric field (E) shielding effect in the upward direction from the gate electrode DG of the driving TFT DT. In other words, the first shielding electrode TM may exist between the gate electrode DG of the driving TFT DT and the first data line DL1 to shield an upward electric field E formed between them, thereby keeping the gate voltage at the driving TFT DT from being affected by the data voltage. The second shielding electrode BM extending further towards the first data line DL1 provides electric field (E) shielding effect in the downward direction from the gate electrode DG of the driving TFT DT. In other words, the second shielding electrode BM may exist below the gate electrode DG of the driving TFT DT to shield a downward electric field E formed between them, thereby keeping the gate voltage at the driving TFT DT from being affected by the data voltage.
- As discussed above, it is preferable that the end IS_T of the first shielding electrode TM protrudes further towards the first data line DL1 than the end IS_G of the gate electrode DG, in order to give the first capacitor C1 a higher capacitance value than that of the parasitic capacitor Cgd and to shield the upward electric field E formed between the gate electrode DG of the driving TFT DT and the first data line DL1. Also, it is preferable that the end IS_B of the second shielding electrode BM protrudes further towards the first data line DL1 than the end IS_G of the gate electrode DG, in order to give the second capacitor C2 a higher capacitance value than that of the parasitic capacitor Cgd and to shield the downward electric field E formed between the gate electrode DG of the driving TFT DT and the first data line DL1. With the first shielding electrode TM and the second shielding electrode BM both extending further towards the first data line DL1, the present invention can minimize the effect of the data voltage on the gate electrode DG of the driving TFT DT and, as a result, prevent a vertical crosstalk that occurs when the gate voltage at the driving TFT DT changes with a change in data voltage.
- The first capacitor C1 and the second capacitor C2 both function as a storage capacitor. It is preferable that both the first shielding electrode TM and the second shielding electrode BM overlap the gate electrode DG of the driving TFT DT across a wide area, in order for the storage capacitor to have a sufficient capacitance. Therefore, with the storage capacitor having a sufficient capacitance, the present invention can improve the data maintainability of the pixels and suppress pixel voltage discharge when the pixels run at a low refresh rate for reduced power consumption, thereby enhancing the picture quality even with the low refresh rate.
- Moreover, the present invention allows the storage capacitor to have a sufficient capacitance in a limited area since a dual storage capacitor can be formed, or located, vertically. Accordingly, the second exemplary embodiment of the present invention may be applicable to organic light emitting diode displays with high resolution that require a storage capacitor in a limited area.
- The second exemplary embodiment of the present invention is characterized by having a first shielding electrode TM and a second shielding electrode BM, in order that a gate voltage applied to the driving TFT DT's gate electrode DG is not affected by changes in the voltage of an adjacent line. The adjacent line is not limited to the above-described data line to which a data voltage is applied. The adjacent line may include any line, as long as a signal different from the gate voltage applied to the gate electrode DG of the driving TFT DT is applied to the adjacent line and the adjacent line is located adjacent to the gate electrode DG of the driving TFT DT. For example, referring to the drawing, the adjacent line may include the 1a gate line GL1a, the 1b gate line GL1b, and the 1c gate line GL1c.
- Although embodiments have been described with reference to a number of illustrative embodiments thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the scope of the principles of this disclosure. More particularly, numerous variations and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the appended claims. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.
- The following is a list of exemplary aspects of the present invention.
-
Aspect 1. An organic light emitting display in which each pixel has a driving thin film transistor for adjusting the current flowing through an organic light emitting diode based on a voltage applied to a gate electrode, the organic light emitting diode display comprising:- the gate electrode of the driving thin film transistor;
- a signal line adjacent to the gate electrode of the driving thin film transistor; and
- a first shielding electrode located above the gate electrode of the driving thin film transistor, with a first insulating layer therebetween,
- wherein the first shielding electrode protrudes further towards the signal line than the gate electrode of the driving thin film transistor does.
-
Aspect 2. The organic light emitting diode display ofaspect 1, wherein the distance between the signal line and the first shielding electrode is shorter than the distance between the signal line and the gate electrode of the driving thin film transistor. - Aspect 3. The organic light emitting diode display of
aspect 1, wherein the first shielding electrode is electrically connected to a static voltage source. - Aspect 4. The organic light emitting diode display of aspect 3, further comprising:
- a parasitic capacitor formed between the signal line and the gate electrode of the driving thin film transistor; and
- a first capacitor formed by the overlapping of the first shielding electrode and the gate electrode of the driving thin film transistor,
- wherein the first capacitor has a higher capacitance than the parasitic capacitor.
- Aspect 5. The organic light emitting diode display of aspect 4, further comprising a second shielding electrode located below the gate electrode of the driving thin film transistor, with a second insulating layer therebetween,
wherein the second shielding electrode protrudes further towards the signal line than the gate electrode of the driving thin film transistor does. - Aspect 6. The organic light emitting diode display of aspect 5, wherein the distance between the signal line and the second shielding electrode is shorter than the distance between the signal line and the gate electrode of the driving thin film transistor.
- Aspect 7. The organic light emitting diode display of aspect 5, wherein the second shielding electrode is electrically connected to a static voltage source.
- Aspect 8. The organic light emitting diode display of aspect 7, further comprising:
- a second capacitor formed by the overlapping of the second shielding electrode and the gate electrode of the driving thin film transistor,
- wherein the second capacitor has a higher capacitance than the parasitic capacitor.
Claims (15)
- An organic light emitting display (10) comprising pixels in which each pixel has a driving thin film transistor (DT) for adjusting the current flowing through an organic light emitting diode (10) based on a voltage applied to a gate electrode (DG) of the driving thin film transistor (DT), the organic light emitting diode display (10) further comprising:a signal line (DL1) adjacent to the gate electrode (DG) of the driving thin film transistor (DT); anda first shielding electrode (TM) located above the gate electrode (DG) of the driving thin film transistor (DT), with a first insulating layer (IN2) therebetween,wherein the first shielding electrode (TM) protrudes further towards the signal line (DL1) than the gate electrode (DG) of the driving thin film transistor (DT).
- The organic light emitting diode display of claim 1, wherein the distance between the signal line (DL1) and the first shielding electrode (TM) is shorter than the distance between the signal line (DL1) and the gate electrode (DG) of the driving thin film transistor (DT).
- The organic light emitting display of claims 1 or 2, wherein the first shielding electrode (TM) is configured to be connected to a first constant voltage source (EVDD).
- The organic light emitting display of any one of the preceding claim, wherein the first shielding electrode (TM) is configured to be a first capacitor (C1).
- The organic light emitting diode display of claim 4, wherein:a parasitic capacitor is formed between the signal line (DL1) and the gate electrode (DG) of the driving thin film transistor (DT);the first capacitor (C1) is formed by the overlapping of the first shielding electrode (TM) and the gate electrode (DG) of the driving thin film transistor (TM); andthe first capacitor (C1) has a higher capacitance than the parasitic capacitor.
- The organic light emitting display of claims 4 or 5, wherein the first capacitor (C1) is configured to suppress pixel voltage discharge.
- The organic light emitting display of any one of the preceding claim, wherein the organic light emitting diode display (10) further comprises:a second shielding electrode (BM) located below the gate electrode (DG) of the driving thin film transistor (DT) with a second insulating layer (IN1) therebetween,wherein the second shielding electrode (BM) protrudes further towards the signal line (DL1) than the gate electrode (DG) of the driving thin film transistor (DT).
- The organic light emitting diode display of claim 7, wherein the distance between the signal line (DL1) and the second shielding electrode (BM) is shorter than the distance between the signal line (DL1) and the gate electrode (DG) of the driving thin film transistor (DT).
- The organic light emitting display of claims 7 or 8, wherein the second shielding electrode (BM) is configured to be connected to a second constant voltage source (EVDD).
- The organic light emitting display of any one of claims 7 to 9, wherein the second shielding electrode (BM) is configured to be a second capacitor (C2).
- The organic light emitting diode display of claim 10, wherein:a parasitic capacitor is formed between the signal line (DL1) and the gate electrode (DG) of the driving thin film transistor (DT);the second capacitor (C2) is formed by the overlapping of the second shielding electrode (BM) and the gate electrode (DG) of the driving thin film transistor (DT); andthe second capacitor (C2) has a higher capacitance than the parasitic capacitor.
- The organic light emitting display of claims 10 or 11, wherein the second capacitor (C2) is configured to suppress pixel voltage discharge.
- The organic light emitting display of claim 9 to 12 when dependent on claims 3 and 9, wherein the first constant voltage source and the second constant voltage source are the same.
- The organic light emitting display of any one of the preceding claims, wherein each pixel is configured in a six transistor and one capacitor (6T1C) structure.
- The organic light emitting display of claim 14, wherein the six transistor and one capacitor (6T1C) structure comprises:a first thin film transistor (T1) comprising a gate electrode connected to a first gate line (GL1a), a first electrode connected to a first data line (DL1), and a second electrode connected to one end of a storage capacitor (Cstg);a second thin film transistor (T2) comprising a gate electrode connected to a second gate line (GL1b), a first electrode connected to the gate electrode of the driving thin film transistor (DT), and a second electrode connected to a second electrode of the driving thin film transistor (DT);a third thin film transistor (T3) comprising a gate electrode connected to a third gate line (GL1c), a first electrode connected to a reference voltage line (VREF), and a second electrode connected to one end of the storage capacitor (Cstg);a fourth thin film transistor (T4) comprising a gate electrode connected to a third gate line (GL1c), a first electrode connected to the second electrode of the driving thin film transistor (DT), and a second electrode connected to the anode of the organic light emitting diode (OLED);a fifth thin film transistor (T5) comprising a gate electrode connected to the second gate line (GL1b), a first electrode connected to the reference voltage line (VREF), and a second electrode connected to the anode of the organic light emitting diode (OLED); andthe driving thin film transistor (DT) comprising the gate electrode connected to the other end of the storage capacitor (Cstg), a first electrode connected to a first power supply (EVDD), and a second electrode connected to the first electrode of the fourth thin film transistor (T4).
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US10453834B2 (en) * | 2016-12-09 | 2019-10-22 | Samsung Display Co., Ltd. | Display device with electrostatic dispersion line |
CN108010944A (en) * | 2017-11-28 | 2018-05-08 | 武汉天马微电子有限公司 | Array substrate and display device |
CN108597374B (en) | 2018-04-20 | 2021-02-02 | 上海天马有机发光显示技术有限公司 | Display panel and display device |
KR102584303B1 (en) | 2018-06-25 | 2023-10-04 | 삼성디스플레이 주식회사 | Display device |
KR102622421B1 (en) | 2018-12-31 | 2024-01-05 | 엘지디스플레이 주식회사 | Light emitting diode display apparatus and multi screen display apparatus using the same |
CN109872690B (en) * | 2019-03-27 | 2020-09-08 | 武汉华星光电半导体显示技术有限公司 | Display panel |
CN111834375B (en) | 2019-05-23 | 2022-11-08 | 昆山国显光电有限公司 | Display substrate, display panel and display device |
US11469291B2 (en) | 2019-11-29 | 2022-10-11 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Display panel, method of manufacturing the same, and display device |
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CN113299244B (en) * | 2021-05-24 | 2023-02-07 | 京东方科技集团股份有限公司 | Voltage control module, driving method and display device |
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