EP3062443A1 - Sensor device - Google Patents

Sensor device Download PDF

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Publication number
EP3062443A1
EP3062443A1 EP14856600.3A EP14856600A EP3062443A1 EP 3062443 A1 EP3062443 A1 EP 3062443A1 EP 14856600 A EP14856600 A EP 14856600A EP 3062443 A1 EP3062443 A1 EP 3062443A1
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EP
European Patent Office
Prior art keywords
transistor
sensor device
gnd
field
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP14856600.3A
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German (de)
French (fr)
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EP3062443B1 (en
EP3062443A4 (en
Inventor
Satoshi Asano
Masahiro Matsumoto
Hiroshi Nakano
Shinobu Tashiro
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Hitachi Astemo Ltd
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Hitachi Automotive Systems Ltd
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Publication of EP3062443A1 publication Critical patent/EP3062443A1/en
Publication of EP3062443A4 publication Critical patent/EP3062443A4/en
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    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02HEMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H02H3/18Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to reversal of direct current
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R15/00Details of measuring arrangements of the types provided for in groups G01R17/00 - G01R29/00, G01R33/00 - G01R33/26 or G01R35/00
    • G01R15/14Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks
    • G01R15/146Measuring arrangements for current not covered by other subgroups of G01R15/14, e.g. using current dividers, shunts, or measuring a voltage drop
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0641Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
    • H01L27/0647Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/20Resistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02HEMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H11/00Emergency protective circuit arrangements for preventing the switching-on in case an undesired electric working condition might result
    • H02H11/002Emergency protective circuit arrangements for preventing the switching-on in case an undesired electric working condition might result in case of inverted polarity or connection; with switching for obtaining correct connection
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02HEMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H02H3/24Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to undervoltage or no-voltage

Definitions

  • the present invention relates to a sensor device supplied with power from the outside, and particularly to a sensor device having breakdown resistance and malfunction resistance to a negative surge that occurs in a power line.
  • the technique described in PTL 1 is configured to divide supply voltage to a P-type FET provided between a power source and a load circuit, and to the load circuit, via a resistor, and to input intermediate voltage thereof to a gate of the P-type FET.
  • the load circuit is protected in the following manner. When an input-side polarity is normally connected, the P-type FET enters an ON state to supply source voltage to the load circuit, and when the input-side polarity is reversely connected, the P-type FET enters an OFF state so that reverse polarity voltage is not applied to the load circuit.
  • the present invention has been devised in view of the above-described situations, and the object of the present invention is to provide a sensor device that has high malfunction resistance, and suppresses a voltage drop in a load circuit even if a negative surge or a voltage drop that continues for a relatively long time occurs in a power line.
  • a sensor device includes a sensor element having an electrical characteristic varying according to a physical amount, a signal processing circuit configured to process an output signal of the sensor element, a transistor element interposed between a power source terminal and the signal processing circuit, a resistive element configured to connect a drain and a gate of the transistor element, or a collector and a base of the transistor element, and an element having threshold voltage for connecting the gate or the base of the transistor element to a GND.
  • the element regulates current flowing from the resistive element in a direction of the GND, in a case in which supply voltage to the signal processing circuit falls below the threshold voltage.
  • the present invention can provide a sensor device that has high malfunction resistance, and can suppress a voltage drop in a load circuit even if a negative surge or a voltage drop that continues for a relatively long time occurs in a power line.
  • FIG. 1 illustrates a configuration of the sensor device according to the first embodiment.
  • FIG. 6 illustrates an example of an internal power source voltage fluctuation waveform obtainable when a negative surge is applied, according to the technique of the present invention.
  • FIG. 7 illustrates an example of an internal power source voltage fluctuation waveform obtainable when a negative surge is applied, according to a conventional configuration.
  • FIG. 8 illustrates a configuration of a conventional sensor device.
  • a sensor device 1 includes a power source terminal 2 for supplying voltage Vb, a GND terminal 3, a sensor element 20 for generating an electric signal according to a physical amount, and a sensor circuit 10 for supplying power to the sensor element 20 and processing an output signal from the sensor element 20.
  • the sensor circuit 10 includes a signal processing circuit 11 for processing an output signal from the sensor element 20, a P-type field-effect transistor (hereinafter, referred to as "PMOS”) 12 interposed between the power source terminal 2 and the signal processing circuit 11, a resistor 14 for connecting a drain and a gate of the PMOS 12, and a PMOS 13 for connecting the gate of the PMOS 12 to a GND.
  • PMOS P-type field-effect transistor
  • a gate and a drain of the PMOS 13 are connected to the GND, and a source thereof is connected to the gate of the PMOS 12.
  • the PMOS 13 has threshold voltage Vth1, and when source voltage of the PMOS 13 is larger than the threshold voltage Vth1, the PMOS 13 turns ON.
  • the source voltage of the PMOS 13 is larger than the threshold voltage Vth1.
  • the PMOS 13 turns ON, and current Is flows from the drain of the PMOS 12 to the GND via the PMOS 13.
  • a resistance value of the resistor 14 is sufficiently larger than ON resistance of the PMOS 13
  • the PMOS 12 enters an ON state, so that conduction is established between the power source terminal 2 and the signal processing circuit 11.
  • supply voltage Vs is supplied from the power source terminal 2 to the processing circuit 11.
  • the sensor device 1 according to the first embodiment is configured to supply source voltage to the signal processing circuit 11 via the PMOS 12 in normal times, and can supply the stable supply voltage Vs to the processing circuit 11 irrespective of temperature because the PMOS 12 has a smaller voltage drop as compared with a parasitic diode.
  • the PMOS 13 autonomously turns OFF at the time when the source voltage of the PMOS 13 reaches the threshold voltage Vth1.
  • the current Is that has been flowing in the PMOS 13 stops. Accordingly, the gate and the drain of the PMOS 12 have the same potential.
  • the PMOS 13 autonomously turns OFF at the time when the source voltage of the PMOS 13 reaches the threshold voltage Vth1. It is therefore possible to surely turn OFF the PMOS 12.
  • the PMOS 13 turns OFF at the time when the source voltage reaches the threshold voltage Vth1.
  • the PMOS 13 thereby regulates the flow of the current Is.
  • the supply voltage Vs of the processing circuit 11 is maintained in the vicinity of threshold voltage Vth.
  • the well of the PMOS 12 is connected to the drain, and the well of the PMOS 13 is connected to the source.
  • the function of the sensor device according the conventional configuration will be described with reference to FIGS. 8 and 9 .
  • the PMOS 12 if the source voltage Vb falls below threshold voltage Vth2 of the PMOS 12, the PMOS 12 turns OFF. At this time, the supply voltage Vs drops to about the threshold voltage Vth2. Then, electrical charge accumulated in the signal processing circuit 11 continues to be discharged via resistors 14a and 14b. Finally, all the electrical charge is lost. Thus, the supply voltage Vs fails to be maintained, so that the malfunction of the sensor device may be caused.
  • the first effect lies in that the sensor device is configured to supply source voltage to the signal processing circuit 11 via the PMOS 12 in normal times, and can supply the stable supply voltage Vs to the processing circuit 11 irrespective of temperature because the PMOS 12 has a smaller voltage drop as compared with a parasitic diode.
  • the second effect lies in that the malfunction of the sensor can be prevented because the drop in the supply voltage Vs to the signal processing circuit 11 can be maintained in the vicinity of the threshold voltage Vth1 of the PMOS 13 even if a negative surge or a source voltage drop that continues for a long time occurs.
  • the third effect lies in that the PMOS 12 can be surely turned OFF because the PMOS 13 autonomously turns OFF at the time when the source voltage of the PMOS 13 falls below the threshold voltage Vth1.
  • FIG. 2 illustrates a configuration of the sensor device according to the second embodiment.
  • the description of the points overlapped with the first embodiment of the present invention will be omitted.
  • a sensor device 1 according to the second embodiment is characterized in that a capacitor 16 is connected in series to the signal processing circuit 11 in the sensor device 1 according to the first embodiment.
  • a low-pass filter including ON resistance of the PMOS 12 and the capacitor 16 is thereby formed. This can make it difficult to transmit a fluctuation in the source voltage Vb to the supply voltage Vs.
  • the amount of electrical charge that can be accumulated is increased by the capacitor 16. It is therefore possible to suppress the drop amount of the supply voltage Vs with respect to a discharge amount.
  • the second embodiment of the present invention can further improve negative surge resistance.
  • FIG. 3 illustrates a configuration of the sensor device according to the third embodiment.
  • the description of the points overlapped with the first embodiment of the present invention will be omitted.
  • a sensor device 1 according to the third embodiment includes a PNP bipolar transistor (hereinafter, referred to as "PNP transistor") 15 and a PNP transistor 17, instead of the PMOS 12 and the PMOS 13 in the sensor device 1 according to the first embodiment.
  • PNP transistor PNP bipolar transistor
  • An emitter of the PNP transistor 15 and a power source terminal 2 are connected, a collector of the PNP transistor 15 and a signal processing circuit 11 are connected, and a base of the PNP transistor 15 and an emitter of the PNP transistor 17 are connected.
  • a collector and a base of the PNP transistor 17 are connected to the GND. In normal times, base currents Ib1 and Ib2 flow in the PNP transistors 15 and 17.
  • the PNP transistors 15 and 17 accordingly enter the ON state.
  • the PNP transistor 17 If the supply voltage Vs falls below threshold voltage Vth of the PNP transistor 17, the PNP transistor 17 enters an OFF state. At the same time, base voltage and collector voltage of the PNP transistor 15 have the same potential. Thus, even if emitter voltage of the PNP transistor 15 fluctuates toward a negative side with respect to collector voltage, the PNP transistor 15 does not turn ON, and electrical charge accumulated in the signal processing circuit 11 is maintained.
  • the supply voltage Vs can be accordingly maintained in the vicinity of the threshold voltage Vth of the PNP transistor 17.
  • the sensor device according to the present embodiment can obtain the effects similar to those of the sensor device according to the first embodiment. Furthermore, since bipolar transistors can flow larger current than that in MOSFETs, bipolar transistors are suitable for a sensor device with large power consumption.
  • FIG. 4 illustrates a configuration of the sensor device according to the fourth embodiment.
  • the description of the points overlapped with the first embodiment of the present invention will be omitted.
  • a sensor device 1 according to the fourth embodiment includes a PN junction diode 18 instead of the PMOS 13 in the sensor device 1 according to the first embodiment.
  • a connection point between a resistor 14 and a gate of a PMOS 12 is connected to an anode of the PN junction diode 18, and a cathode of the PN junction diode 18 is connected to the GND.
  • forward current Id flows in the PN junction diode 18.
  • the PMOS 12 accordingly turns ON. If supply voltage Vs falls below forward voltage Vd of the PN junction diode 18, the forward current Id is regulated by the PN junction diode 18, so that a gate and a drain of the PMOS 12 have the same potential.
  • the sensor device according to the present embodiment can obtain the effects similar to those of the sensor device according to the first embodiment.
  • FIG. 5 illustrates a configuration of the sensor device according to the fifth embodiment.
  • the description of the points overlapped with the first embodiment of the present invention will be omitted.
  • a sensor device 1 according to the fifth embodiment includes a PN junction diode 18b connected in series to the PN junction diode 18 in the sensor device 1 according to the fourth embodiment.
  • forward current Id is regulated, so that a gate and a drain of the PMOS 12 have the same potential.
  • the supply voltage Vs can be accordingly maintained in the vicinity of the doubled value of the forward voltage Vd of the PN junction diodes 18 and 18b.
  • the sensor device according to the present embodiment can obtain the following effect in addition to the effects of the sensor device according to the first embodiment. More specifically, the effect lies in that hold voltage of the supply voltage Vs can be adjusted according to the number of series-connected PN junction diodes.
  • the above-described technique of adjusting hold voltage can be realized by using a P-type field-effect transistor or a PNP bipolar transistor.
  • a P-type field-effect transistor or a PNP bipolar transistor For example, as illustrated in FIG. 9 , there is a method of further adding a PMOS 13b between the GND and the drain of the PMOS 13 of the sensor device 1 according to the first embodiment, connecting the gate and the drain of the PMOS 13 to a source of the PMOS 13b, and connecting a gate and a drain of the PMOS 13b to the GND.
  • FIG. 9 there is a method of further adding a PMOS 13b between the GND and the drain of the PMOS 13 of the sensor device 1 according to the first embodiment, connecting the gate and the drain of the PMOS 13 to a source of the PMOS 13b, and connecting a gate and a drain of the PMOS 13b to the GND.
  • sensor circuit 1: sensor device, 2: power source terminal, 3: GND terminal, 10: sensor circuit, 11: signal processing circuit, 12: MOSFET, 13: MOSFET, 14: resistor, 15: transistor, 16: capacitor, 17: transistor, 18: diode, 19: diode, 20: sensor element

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
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  • Semiconductor Integrated Circuits (AREA)
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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

Provided is a sensor device that suppresses a malfunction caused by a negative surge or a voltage drop. A sensor device includes a sensor element having an electrical characteristic varying according to a physical amount, a signal processing circuit configured to process an output signal of the sensor element, a transistor element interposed between a power source terminal and the signal processing circuit, a resistive element configured to connect a drain and a gate of the transistor element, or a collector and a base of the transistor element, and an element having threshold voltage for connecting the gate or the base of the transistor element to a GND. The element regulates current flowing from the resistive element in a direction of the GND, in a case in which supply voltage to the signal processing circuit falls below the threshold voltage.

Description

    Technical Field
  • The present invention relates to a sensor device supplied with power from the outside, and particularly to a sensor device having breakdown resistance and malfunction resistance to a negative surge that occurs in a power line.
  • Background Art
  • If a negative surge or a voltage fluctuation occurs in a power line, supply voltage to a load circuit becomes negative voltage, and reverse current flows in the load circuit, so that breakdown may occur. As a conventional technique addressing such an issue, there is a technique described in PTL 1.
  • The technique described in PTL 1 is configured to divide supply voltage to a P-type FET provided between a power source and a load circuit, and to the load circuit, via a resistor, and to input intermediate voltage thereof to a gate of the P-type FET. The load circuit is protected in the following manner. When an input-side polarity is normally connected, the P-type FET enters an ON state to supply source voltage to the load circuit, and when the input-side polarity is reversely connected, the P-type FET enters an OFF state so that reverse polarity voltage is not applied to the load circuit.
  • Citation List Patent Literature
  • PTL 1: JP-2000-341848-A
  • Summary of Invention Technical Problem
  • In recent years, however, there has been an increasing demand for cost reduction, and it is necessary to simplify a protection circuit provided on the outside of a conductor chip. In this case, a negative surge or a voltage drop that continues for a relatively longer time than that in conventional circuits occurs in a power line. If load circuit side voltage falls below threshold voltage of the P-type FET, the P-type FET turns OFF. As a result, electrical charge accumulated in the load circuit stops being discharged to a power source side via the P-type FET. Nevertheless, if the negative surge continues even after this state, electrical charge accumulated in the load circuit via voltage division resistors continues to be discharged. Finally, the accumulated electrical charge is fully discharged. In response to the full discharge, the load circuit is reset. Thus, a malfunction such as an abnormal value output and a restarting operation may occur.
  • The present invention has been devised in view of the above-described situations, and the object of the present invention is to provide a sensor device that has high malfunction resistance, and suppresses a voltage drop in a load circuit even if a negative surge or a voltage drop that continues for a relatively long time occurs in a power line.
  • Solution to Problem
  • To achieve the above-described object, a sensor device according to the present invention includes a sensor element having an electrical characteristic varying according to a physical amount, a signal processing circuit configured to process an output signal of the sensor element, a transistor element interposed between a power source terminal and the signal processing circuit, a resistive element configured to connect a drain and a gate of the transistor element, or a collector and a base of the transistor element, and an element having threshold voltage for connecting the gate or the base of the transistor element to a GND. The element regulates current flowing from the resistive element in a direction of the GND, in a case in which supply voltage to the signal processing circuit falls below the threshold voltage.
  • Advantageous Effects of Invention
  • The present invention can provide a sensor device that has high malfunction resistance, and can suppress a voltage drop in a load circuit even if a negative surge or a voltage drop that continues for a relatively long time occurs in a power line.
  • Brief Description of Drawings
    • [FIG. 1] FIG. 1 illustrates a configuration of a sensor device according to a first embodiment.
    • [FIG. 2] FIG. 2 illustrates a configuration of a sensor device according to a second embodiment.
    • [FIG. 3] FIG. 3 illustrates a configuration of a sensor device according to a third embodiment.
    • [FIG. 4] FIG. 4 illustrates a configuration of a sensor device according to a fourth embodiment.
    • [FIG. 5] FIG. 5 illustrates a configuration of a sensor device according to a fifth embodiment.
    • [FIG. 6] FIG. 6 illustrates an example of an internal power source voltage fluctuation waveform obtainable when a negative surge is applied, according to the technique of the present invention.
    • [FIG. 7] FIG. 7 illustrates an example of an internal power source voltage fluctuation waveform obtainable when a negative surge is applied, according to a conventional configuration.
    • [FIG. 8] FIG. 8 illustrates a configuration of a conventional sensor device.
    • [FIG. 9] FIG. 9 illustrates an application example of the sensor device according to the fifth embodiment.
    • [FIG. 10] FIG. 10 illustrates an application example of the sensor device according to the fifth embodiment.
    Description of Embodiments
  • Embodiments of the present invention will be described below with reference to the drawings.
  • A sensor device according to a first embodiment of the present invention will be described with reference to FIGS. 1, 6, 7, and 8. FIG. 1 illustrates a configuration of the sensor device according to the first embodiment. FIG. 6 illustrates an example of an internal power source voltage fluctuation waveform obtainable when a negative surge is applied, according to the technique of the present invention. FIG. 7 illustrates an example of an internal power source voltage fluctuation waveform obtainable when a negative surge is applied, according to a conventional configuration. FIG. 8 illustrates a configuration of a conventional sensor device.
  • The configuration of the sensor device according to the first embodiment will be described with reference to FIG. 1.
  • A sensor device 1 according to the first embodiment includes a power source terminal 2 for supplying voltage Vb, a GND terminal 3, a sensor element 20 for generating an electric signal according to a physical amount, and a sensor circuit 10 for supplying power to the sensor element 20 and processing an output signal from the sensor element 20. The sensor circuit 10 includes a signal processing circuit 11 for processing an output signal from the sensor element 20, a P-type field-effect transistor (hereinafter, referred to as "PMOS") 12 interposed between the power source terminal 2 and the signal processing circuit 11, a resistor 14 for connecting a drain and a gate of the PMOS 12, and a PMOS 13 for connecting the gate of the PMOS 12 to a GND. A gate and a drain of the PMOS 13 are connected to the GND, and a source thereof is connected to the gate of the PMOS 12. The PMOS 13 has threshold voltage Vth1, and when source voltage of the PMOS 13 is larger than the threshold voltage Vth1, the PMOS 13 turns ON.
  • The function of the sensor device according to the first embodiment will be described with reference to FIGS. 1 and 7.
  • In normal times, the source voltage of the PMOS 13 is larger than the threshold voltage Vth1. Thus, the PMOS 13 turns ON, and current Is flows from the drain of the PMOS 12 to the GND via the PMOS 13. When a resistance value of the resistor 14 is sufficiently larger than ON resistance of the PMOS 13, the PMOS 12 enters an ON state, so that conduction is established between the power source terminal 2 and the signal processing circuit 11. Then, supply voltage Vs is supplied from the power source terminal 2 to the processing circuit 11. The sensor device 1 according to the first embodiment is configured to supply source voltage to the signal processing circuit 11 via the PMOS 12 in normal times, and can supply the stable supply voltage Vs to the processing circuit 11 irrespective of temperature because the PMOS 12 has a smaller voltage drop as compared with a parasitic diode.
  • On the other hand, if the supply voltage Vs abnormally drops due to a negative surge or the like, the PMOS 13 autonomously turns OFF at the time when the source voltage of the PMOS 13 reaches the threshold voltage Vth1. Upon the PMOS 13 turning OFF, the current Is that has been flowing in the PMOS 13 stops. Accordingly, the gate and the drain of the PMOS 12 have the same potential. Thus, even if the source voltage of the PMOS 12 fluctuates toward a negative side with respect to drain voltage of the PMOS 12, the PMOS 12 does not turn ON, and electrical charge accumulated in the signal processing circuit 11 is maintained. The PMOS 13 autonomously turns OFF at the time when the source voltage of the PMOS 13 reaches the threshold voltage Vth1. It is therefore possible to surely turn OFF the PMOS 12.
  • The PMOS 13 turns OFF at the time when the source voltage reaches the threshold voltage Vth1. The PMOS 13 thereby regulates the flow of the current Is. Thus, even if a negative surge or the like occurs and continues for a relatively long time, electrical charge accumulated in the processing circuit via the resistor 14 can be prevented from being fully discharged. The supply voltage Vs of the processing circuit 11 is maintained in the vicinity of threshold voltage Vth. Thus, by setting the threshold voltage Vth to a voltage value equal to or larger than stored information of a memory provided in the processing circuit 11, the malfunction of the sensor device can be prevented.
  • In addition, for preventing the operation delays of the PMOS 12 and the PMOS 13, it is desirable to connect a well of the PMOS 12 and a well of the PMOS 13 to a node on the supply voltage Vs side to stabilize voltage of each well. Thus, the well of the PMOS 12 is connected to the drain, and the well of the PMOS 13 is connected to the source.
  • In contrast, the function of the sensor device according the conventional configuration will be described with reference to FIGS. 8 and 9. According to the conventional configuration, if the source voltage Vb falls below threshold voltage Vth2 of the PMOS 12, the PMOS 12 turns OFF. At this time, the supply voltage Vs drops to about the threshold voltage Vth2. Then, electrical charge accumulated in the signal processing circuit 11 continues to be discharged via resistors 14a and 14b. Finally, all the electrical charge is lost. Thus, the supply voltage Vs fails to be maintained, so that the malfunction of the sensor device may be caused.
  • The effects of the sensor device according to the first embodiment will be summarized.
  • The first effect lies in that the sensor device is configured to supply source voltage to the signal processing circuit 11 via the PMOS 12 in normal times, and can supply the stable supply voltage Vs to the processing circuit 11 irrespective of temperature because the PMOS 12 has a smaller voltage drop as compared with a parasitic diode.
  • The second effect lies in that the malfunction of the sensor can be prevented because the drop in the supply voltage Vs to the signal processing circuit 11 can be maintained in the vicinity of the threshold voltage Vth1 of the PMOS 13 even if a negative surge or a source voltage drop that continues for a long time occurs.
  • The third effect lies in that the PMOS 12 can be surely turned OFF because the PMOS 13 autonomously turns OFF at the time when the source voltage of the PMOS 13 falls below the threshold voltage Vth1.
  • A sensor device according to a second embodiment of the present invention will be described with reference to FIG. 2. FIG. 2 illustrates a configuration of the sensor device according to the second embodiment. In addition, the description of the points overlapped with the first embodiment of the present invention will be omitted.
  • A sensor device 1 according to the second embodiment is characterized in that a capacitor 16 is connected in series to the signal processing circuit 11 in the sensor device 1 according to the first embodiment. A low-pass filter including ON resistance of the PMOS 12 and the capacitor 16 is thereby formed. This can make it difficult to transmit a fluctuation in the source voltage Vb to the supply voltage Vs. In addition, the amount of electrical charge that can be accumulated is increased by the capacitor 16. It is therefore possible to suppress the drop amount of the supply voltage Vs with respect to a discharge amount. Thus, the second embodiment of the present invention can further improve negative surge resistance.
  • A sensor device according to a third embodiment of the present invention will be described with reference to FIG. 3. FIG. 3 illustrates a configuration of the sensor device according to the third embodiment. In addition, the description of the points overlapped with the first embodiment of the present invention will be omitted.
  • A sensor device 1 according to the third embodiment includes a PNP bipolar transistor (hereinafter, referred to as "PNP transistor") 15 and a PNP transistor 17, instead of the PMOS 12 and the PMOS 13 in the sensor device 1 according to the first embodiment. An emitter of the PNP transistor 15 and a power source terminal 2 are connected, a collector of the PNP transistor 15 and a signal processing circuit 11 are connected, and a base of the PNP transistor 15 and an emitter of the PNP transistor 17 are connected. A collector and a base of the PNP transistor 17 are connected to the GND. In normal times, base currents Ib1 and Ib2 flow in the PNP transistors 15 and 17. The PNP transistors 15 and 17 accordingly enter the ON state. If the supply voltage Vs falls below threshold voltage Vth of the PNP transistor 17, the PNP transistor 17 enters an OFF state. At the same time, base voltage and collector voltage of the PNP transistor 15 have the same potential. Thus, even if emitter voltage of the PNP transistor 15 fluctuates toward a negative side with respect to collector voltage, the PNP transistor 15 does not turn ON, and electrical charge accumulated in the signal processing circuit 11 is maintained. The supply voltage Vs can be accordingly maintained in the vicinity of the threshold voltage Vth of the PNP transistor 17. The sensor device according to the present embodiment can obtain the effects similar to those of the sensor device according to the first embodiment. Furthermore, since bipolar transistors can flow larger current than that in MOSFETs, bipolar transistors are suitable for a sensor device with large power consumption.
  • A sensor device according to a fourth embodiment of the present invention will be described with reference to FIG. 4. FIG. 4 illustrates a configuration of the sensor device according to the fourth embodiment. In addition, the description of the points overlapped with the first embodiment of the present invention will be omitted.
  • A sensor device 1 according to the fourth embodiment includes a PN junction diode 18 instead of the PMOS 13 in the sensor device 1 according to the first embodiment. A connection point between a resistor 14 and a gate of a PMOS 12 is connected to an anode of the PN junction diode 18, and a cathode of the PN junction diode 18 is connected to the GND. In normal times, forward current Id flows in the PN junction diode 18. The PMOS 12 accordingly turns ON. If supply voltage Vs falls below forward voltage Vd of the PN junction diode 18, the forward current Id is regulated by the PN junction diode 18, so that a gate and a drain of the PMOS 12 have the same potential. Thus, even if the source voltage of the PMOS 12 fluctuates toward a negative side with respect to drain voltage, the PMOS 12 does not turn ON, and electrical charge accumulated in the signal processing circuit 11 is maintained. The supply voltage Vs can be accordingly maintained in the vicinity of the forward voltage Vd of the PN junction diode 18. The sensor device according to the present embodiment can obtain the effects similar to those of the sensor device according to the first embodiment.
  • A sensor device according to a fifth embodiment of the present invention will be described with reference to FIG. 5. FIG. 5 illustrates a configuration of the sensor device according to the fifth embodiment. In addition, the description of the points overlapped with the first embodiment of the present invention will be omitted.
  • A sensor device 1 according to the fifth embodiment includes a PN junction diode 18b connected in series to the PN junction diode 18 in the sensor device 1 according to the fourth embodiment. With this configuration, if supply voltage Vs drops to fall below a doubled value of forward voltage Vd of the PN junction diodes 18 and 18b, forward current Id is regulated, so that a gate and a drain of the PMOS 12 have the same potential. Thus, even if the source voltage of the PMOS 12 fluctuates toward a negative side with respect to drain voltage, the PMOS 12 does not turn ON, and electrical charge accumulated in the signal processing circuit 11 is maintained. The supply voltage Vs can be accordingly maintained in the vicinity of the doubled value of the forward voltage Vd of the PN junction diodes 18 and 18b. The sensor device according to the present embodiment can obtain the following effect in addition to the effects of the sensor device according to the first embodiment. More specifically, the effect lies in that hold voltage of the supply voltage Vs can be adjusted according to the number of series-connected PN junction diodes.
  • In addition, the above-described technique of adjusting hold voltage can be realized by using a P-type field-effect transistor or a PNP bipolar transistor. For example, as illustrated in FIG. 9, there is a method of further adding a PMOS 13b between the GND and the drain of the PMOS 13 of the sensor device 1 according to the first embodiment, connecting the gate and the drain of the PMOS 13 to a source of the PMOS 13b, and connecting a gate and a drain of the PMOS 13b to the GND. In addition, as illustrated in FIG. 10, there is a method of further adding a PNP transistor 17b between the GND and the collector of the PNP transistor 17 of the sensor device 1 according to the third embodiment, connecting the base and the collector of the PNP transistor 17 to an emitter of the PNP transistor 17b, and connecting a base and a collector of the PNP transistor 17b to the GND. Also in the case of using each of the above-described configurations, hold voltage of the supply voltage Vs can be adjusted.
  • Reference Signs List
  • 1: sensor device, 2: power source terminal, 3: GND terminal, 10: sensor circuit, 11: signal processing circuit, 12: MOSFET, 13: MOSFET, 14: resistor, 15: transistor, 16: capacitor, 17: transistor, 18: diode, 19: diode, 20: sensor element

Claims (14)

  1. A sensor device comprising:
    a sensor element having an electrical characteristic varying according to a physical amount;
    a signal processing circuit configured to process an output signal of the sensor element;
    a transistor element interposed between a power source terminal and the signal processing circuit;
    a resistive element configured to connect a drain and a gate of the transistor element, or a collector and a base of the transistor element; and
    an element having threshold voltage for connecting the gate or the base of the transistor element to a GND,
    wherein the element regulates current flowing from the resistive element in a direction of the GND, in a case in which supply voltage to the signal processing circuit falls below the threshold voltage.
  2. The sensor device according to claim 1,
    wherein the transistor element is a first field-effect transistor, and
    wherein a source of the first field-effect transistor and the power source terminal are connected, a drain of the first field-effect transistor and the signal processing circuit are connected, and a gate of the first field-effect transistor is connected to the GND via the element.
  3. The sensor device according to claim 2,
    wherein the element is a second field-effect transistor, and
    wherein a source of the second field-effect transistor and the gate of the first field-effect transistor are connected, and a drain and a gate of the second field-effect transistor and the GND are connected.
  4. The sensor device according to claim 3,
    wherein a well of the first field-effect transistor is connected to a drain of the first field-effect transistor, and a well of the second field-effect transistor is connected to the source of the second field-effect transistor.
  5. The sensor device according to claim 2,
    wherein the element is a transistor circuit including a plurality of series-connected field-effect transistors, and
    wherein a source of the transistor circuit and the gate of the first transistor are connected, and a drain and a gate of the transistor circuit and the GND are connected.
  6. The sensor device according to claim 2,
    wherein the element is a PN junction diode, and wherein an anode of the diode and the gate of the first field-effect transistor are connected, and a cathode of the diode and the GND are connected.
  7. The sensor device according to claim 2,
    wherein the element is a diode circuit including a plurality of series-connected PN junction diodes, and
    wherein an anode of the diode circuit and the gate of the first field-effect transistor are connected, and a cathode of the diode circuit and the GND are connected.
  8. The sensor device according to claim 1,
    wherein the transistor element is a first PNP transistor, and
    wherein an emitter of the first PNP transistor and the power source terminal are connected, a collector of the first PNP transistor and the signal processing circuit are connected, and a base of the first PNP transistor is connected to the GND via the element.
  9. The sensor device according to claim 8,
    wherein the element is a second PNP transistor, and
    wherein an emitter of the second PNP transistor and the base of the first PNP transistor are connected, and a collector and a base of the second PNP transistor are connected to the GND.
  10. The sensor device according to claim 8,
    wherein the element is a transistor circuit including a plurality of series-connected PNP transistors, and
    wherein an emitter of the transistor circuit and the base of the first PNP transistor are connected, and a collector and a base of the transistor circuit and the GND are connected.
  11. The sensor device according to claim 8,
    wherein the element is a PN junction diode, and
    wherein an anode of the diode and the base of the first PNP transistor are connected, and a cathode of the diode and the GND are connected.
  12. The sensor device according to claim 8,
    wherein the element is a diode circuit including a plurality of series-connected PN junction diodes, and
    wherein an anode of the diode circuit and the base of the first PNP transistor are connected, and a cathode of the diode circuit and the GND are connected.
  13. The sensor device according to claim 1,
    wherein the sensor device includes a capacitor series-connected to the signal processing circuit.
  14. The sensor device according to claim 1,
    wherein threshold voltage of the element is a voltage value equal to or larger than information stored in a memory of the processing circuit.
EP14856600.3A 2013-10-23 2014-10-03 Sensor device Active EP3062443B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013219737A JP6393470B2 (en) 2013-10-23 2013-10-23 Sensor device
PCT/JP2014/076487 WO2015060095A1 (en) 2013-10-23 2014-10-03 Sensor device

Publications (3)

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EP3062443A1 true EP3062443A1 (en) 2016-08-31
EP3062443A4 EP3062443A4 (en) 2017-06-14
EP3062443B1 EP3062443B1 (en) 2020-08-12

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CN107578739A (en) * 2017-09-26 2018-01-12 惠科股份有限公司 Protection circuit and display device

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3022457A (en) * 1960-02-19 1962-02-20 Texas Instruments Inc Transistor voltage regulator
US4480226A (en) * 1979-09-12 1984-10-30 Nippon Soken, Inc. Apparatus for indicating the direction of a vehicle with abnormal field sensing circuits
US5537038A (en) * 1988-12-15 1996-07-16 Nkk Corporation Magnetic flux measuring method and apparatus for detecting high frequency components of magnetic flux with high speed orientation
US5422570A (en) * 1993-12-30 1995-06-06 Whirlpool Corporation Speed sensing for the third harmonic stator voltage signal
JP3231003B2 (en) * 1996-06-05 2001-11-19 株式会社エヌ・ティ・ティ・データ electric circuit
JPH10336905A (en) * 1997-06-02 1998-12-18 Harness Sogo Gijutsu Kenkyusho:Kk Battery reverse connection protecting equipment
JP2000341848A (en) 1999-05-28 2000-12-08 Nichicon Corp Reverse-polarity input protective device
JP3719587B2 (en) * 2000-03-28 2005-11-24 株式会社日立製作所 Semiconductor devices and IC cards
JP2003037933A (en) * 2001-07-24 2003-02-07 Koito Mfg Co Ltd Protection apparatus of electronic equipment
US20040119470A1 (en) * 2002-09-13 2004-06-24 Sankyo Seiki Mfg. Co., Ltd. Winding type magnetic sensor device and coin discriminating sensor device
US20060001567A1 (en) * 2004-07-01 2006-01-05 Valter Nilsson Sensor with improved voltage protection
JP2008032424A (en) * 2006-07-26 2008-02-14 Rohm Co Ltd Sensor circuit, semiconductor device, electronic equipment
US20080298784A1 (en) * 2007-06-04 2008-12-04 Mark Allen Kastner Method of Sensing Speed of Electric Motors and Generators
CN101989852B (en) * 2009-07-30 2013-01-02 华为技术有限公司 Single board, communication equipment, device for controlling power on/off of single board and method thereof
JP5514314B2 (en) * 2010-07-30 2014-06-04 パナソニック株式会社 Magnetic field detection microcomputer and magnetic field detection method
JP5610484B2 (en) * 2011-07-14 2014-10-22 オムロンオートモーティブエレクトロニクス株式会社 Power supply reverse connection protection circuit

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WO2015060095A1 (en) 2015-04-30
US9941686B2 (en) 2018-04-10
EP3062443B1 (en) 2020-08-12
JP6393470B2 (en) 2018-09-19
US20160241014A1 (en) 2016-08-18
CN105659498A (en) 2016-06-08
EP3062443A4 (en) 2017-06-14
JP2015082743A (en) 2015-04-27
CN105659498B (en) 2019-04-05

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