EP2820562A4 - Using cost estimation to improve performance of tile rendering for image processing - Google Patents
Using cost estimation to improve performance of tile rendering for image processingInfo
- Publication number
- EP2820562A4 EP2820562A4 EP12869652.3A EP12869652A EP2820562A4 EP 2820562 A4 EP2820562 A4 EP 2820562A4 EP 12869652 A EP12869652 A EP 12869652A EP 2820562 A4 EP2820562 A4 EP 2820562A4
- Authority
- EP
- European Patent Office
- Prior art keywords
- image processing
- improve performance
- cost estimation
- tile rendering
- tile
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T15/00—3D [Three Dimensional] image rendering
- G06T15/005—General purpose rendering architectures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T15/00—3D [Three Dimensional] image rendering
- G06T15/10—Geometric effects
- G06T15/40—Hidden part removal
- G06T15/405—Hidden part removal using Z-buffer
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T2210/00—Indexing scheme for image generation or computer graphics
- G06T2210/52—Parallel processing
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computer Graphics (AREA)
- Geometry (AREA)
- Image Generation (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US2012/026677 WO2013130030A1 (en) | 2012-02-27 | 2012-02-27 | Using cost estimation to improve performance of tile rendering for image processing |
Publications (3)
Publication Number | Publication Date |
---|---|
EP2820562A1 EP2820562A1 (en) | 2015-01-07 |
EP2820562A4 true EP2820562A4 (en) | 2015-11-18 |
EP2820562B1 EP2820562B1 (en) | 2017-08-09 |
Family
ID=49083080
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP12869652.3A Not-in-force EP2820562B1 (en) | 2012-02-27 | 2012-02-27 | Using cost estimation to improve performance of tile rendering for image processing |
Country Status (4)
Country | Link |
---|---|
US (1) | US10134101B2 (en) |
EP (1) | EP2820562B1 (en) |
TW (1) | TWI515580B (en) |
WO (1) | WO2013130030A1 (en) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101511273B1 (en) * | 2008-12-29 | 2015-04-10 | 삼성전자주식회사 | System and method for 3d graphic rendering based on multi-core processor |
US20150170317A1 (en) * | 2013-12-18 | 2015-06-18 | Eric C. Samson | Load Balancing for Consumer-Producer and Concurrent Workloads |
EP3161793B1 (en) * | 2014-06-30 | 2019-05-08 | Intel Corporation | Adaptive partition mechanism with arbitrary tile shape for tile based rendering gpu architecture |
US10249079B2 (en) * | 2014-12-11 | 2019-04-02 | Intel Corporation | Relaxed sorting in a position-only pipeline |
KR102426669B1 (en) * | 2015-08-03 | 2022-07-28 | 삼성전자주식회사 | Method and apparatus for performing a path rendering |
GB2558885B (en) | 2017-01-12 | 2021-04-07 | Imagination Tech Ltd | Graphics processing units and methods for subdividing a set of one or more tiles of a rendering space for rendering |
GB2561807B (en) * | 2017-01-12 | 2019-09-25 | Imagination Tech Ltd | Computing systems and methods for processing graphics data using cost indications for sets of tiles of a rendering space |
GB2558886B (en) | 2017-01-12 | 2019-12-25 | Imagination Tech Ltd | Graphics processing units and methods for controlling rendering complexity using cost indications for sets of tiles of a rendering space |
GB2570743B (en) * | 2018-06-29 | 2021-06-23 | Imagination Tech Ltd | Tile assignment to processing cores within a graphics processing unit |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110298813A1 (en) * | 2010-06-08 | 2011-12-08 | Rasmus Barringer | Tile Rendering for Image Processing |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7023437B1 (en) * | 1998-07-22 | 2006-04-04 | Nvidia Corporation | System and method for accelerating graphics processing using a post-geometry data stream during multiple-pass rendering |
WO2000011607A1 (en) * | 1998-08-20 | 2000-03-02 | Apple Computer, Inc. | Deferred shading graphics pipeline processor |
US7301537B2 (en) | 2002-12-20 | 2007-11-27 | Telefonaktiebolaget Lm Ericsson (Publ) | Graphics processing apparatus, methods and computer program products using minimum-depth occlusion culling and zig-zag traversal |
GB2406184B (en) * | 2003-09-17 | 2006-03-15 | Advanced Risc Mach Ltd | Data processing system |
US6980216B2 (en) * | 2004-01-27 | 2005-12-27 | Honeywell International Inc. | Graphics driver and method with time partitioning |
US7307628B1 (en) * | 2004-08-06 | 2007-12-11 | Nvidia Corporation | Diamond culling of small primitives |
US8004517B1 (en) | 2005-06-24 | 2011-08-23 | Geomagic, Inc. | Methods, apparatus and computer program products that model three-dimensional surface structures |
US8144149B2 (en) | 2005-10-14 | 2012-03-27 | Via Technologies, Inc. | System and method for dynamically load balancing multiple shader stages in a shared pool of processing units |
US7502035B1 (en) * | 2005-12-19 | 2009-03-10 | Nvidia Corporation | Apparatus, system, and method for multi-sample pixel coalescing |
US7620267B2 (en) * | 2006-04-28 | 2009-11-17 | Hewlett-Packard Development Company, L.P. | Collage generation with occlusion costing |
US7659893B1 (en) * | 2006-10-02 | 2010-02-09 | Nvidia Corporation | Method and apparatus to ensure consistency of depth values computed in different sections of a graphics processor |
US8139069B1 (en) * | 2006-11-03 | 2012-03-20 | Nvidia Corporation | Method and system for improving data coherency in a parallel rendering system |
EP2263190A2 (en) * | 2008-02-13 | 2010-12-22 | Ubisoft Entertainment S.A. | Live-action image capture |
US8086037B2 (en) * | 2008-02-15 | 2011-12-27 | Microsoft Corporation | Tiling and merging framework for segmenting large images |
KR101511273B1 (en) * | 2008-12-29 | 2015-04-10 | 삼성전자주식회사 | System and method for 3d graphic rendering based on multi-core processor |
US9189242B2 (en) * | 2009-09-24 | 2015-11-17 | Nvidia Corporation | Credit-based streaming multiprocessor warp scheduling |
US8497876B2 (en) | 2009-11-02 | 2013-07-30 | Pacific Data Images Llc | Infinite complexity deep-framebuffer rendering |
TWI443603B (en) | 2009-11-23 | 2014-07-01 | Inst Information Industry | Two dimensional vector graphics triangulation system and method thereof |
KR101683556B1 (en) * | 2010-01-06 | 2016-12-08 | 삼성전자주식회사 | Apparatus and method for tile-based rendering |
TWI474280B (en) | 2010-04-21 | 2015-02-21 | Via Tech Inc | System and method for improving throughput of a graphics processing unit |
US8982136B2 (en) * | 2011-05-16 | 2015-03-17 | Qualcomm Incorporated | Rendering mode selection in graphics processing units |
CN102208112B (en) | 2011-05-25 | 2015-08-05 | 威盛电子股份有限公司 | Depth of field blanking method, three-dimensional graph process method and device thereof |
CN103608850B (en) * | 2011-06-23 | 2017-05-10 | 英特尔公司 | Stochastic rasterization with selective culling |
US8970587B2 (en) * | 2012-01-16 | 2015-03-03 | Intel Corporation | Five-dimensional occlusion queries |
-
2012
- 2012-02-27 EP EP12869652.3A patent/EP2820562B1/en not_active Not-in-force
- 2012-02-27 US US13/991,960 patent/US10134101B2/en active Active
- 2012-02-27 WO PCT/US2012/026677 patent/WO2013130030A1/en active Application Filing
-
2013
- 2013-02-26 TW TW102106680A patent/TWI515580B/en not_active IP Right Cessation
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110298813A1 (en) * | 2010-06-08 | 2011-12-08 | Rasmus Barringer | Tile Rendering for Image Processing |
Non-Patent Citations (3)
Title |
---|
BENGT OLAF SCHNEIDER: "Bengt- Parallel Polygon Parallel Polygon Rendering Rendering Problem Definition and General Concepts Problem Definition and General Concepts Classification of Parallel Rendering Algorithms Classification of Parallel Rendering Algorithms Load Balancing Load Balancing Practical Issues Practical Issues", SIGGRAPH COURSE, 1 January 2000 (2000-01-01), pages 1 - 19, XP055209293, Retrieved from the Internet <URL:http://www.gris.uni-tuebingen.de/people/staff/bartz/tutorials/sig2000course/s5.pdf> [retrieved on 20150825] * |
ROBLE D R: "A Load Balanced Parallel Scanline Z-Buffer Algorithm for the iPSC Hypercube", ACTES DU 1ER COLLOQUE SCIENTIFIQUE INTERNATIONAL PIXIM 88, L'IMAGE NUMÉRIQUE GBP A PARIS, 24 - 28 OCTOBRE 1988, GRANDE HALLE DE LA VILLETTE, PARIS = PROCEEDINGS OF THE 1ST INTERNATIONAL CONFERENCE PIXIM 88, COMPUTER GRAPHICS IN PARIS, OCTOBER 24TH -, 24 October 1988 (1988-10-24), pages 177 - 192, XP009185854 * |
See also references of WO2013130030A1 * |
Also Published As
Publication number | Publication date |
---|---|
EP2820562B1 (en) | 2017-08-09 |
TWI515580B (en) | 2016-01-01 |
TW201348982A (en) | 2013-12-01 |
EP2820562A1 (en) | 2015-01-07 |
US10134101B2 (en) | 2018-11-20 |
WO2013130030A1 (en) | 2013-09-06 |
US20130335429A1 (en) | 2013-12-19 |
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