EP2658102B1 - Multilevel NPC Inverter - Google Patents

Multilevel NPC Inverter Download PDF

Info

Publication number
EP2658102B1
EP2658102B1 EP13154035.3A EP13154035A EP2658102B1 EP 2658102 B1 EP2658102 B1 EP 2658102B1 EP 13154035 A EP13154035 A EP 13154035A EP 2658102 B1 EP2658102 B1 EP 2658102B1
Authority
EP
European Patent Office
Prior art keywords
voltage level
way
diode
semiconductor switch
choke
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
EP13154035.3A
Other languages
German (de)
French (fr)
Other versions
EP2658102A2 (en
EP2658102A3 (en
Inventor
Markus Schönlinner
Michael Wichmann
Christian Von Le Suire
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dr Johannes Heidenhain GmbH
Original Assignee
Dr Johannes Heidenhain GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dr Johannes Heidenhain GmbH filed Critical Dr Johannes Heidenhain GmbH
Publication of EP2658102A2 publication Critical patent/EP2658102A2/en
Publication of EP2658102A3 publication Critical patent/EP2658102A3/en
Application granted granted Critical
Publication of EP2658102B1 publication Critical patent/EP2658102B1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/487—Neutral point clamped inverters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the invention relates to an inverter for feeding electrical energy into a supply network.
  • Inverters are used to convert a direct voltage into an alternating voltage. Particularly in the field of photovoltaics, the highest possible levels of efficiency are required.
  • Solar modules for converting sunlight into electrical energy first deliver a direct current, which must be converted into alternating current before being fed into the power supply networks.
  • Inverters such as those in the US 6392907 B1 are described.
  • the electrical energy stored in the capacitors of an intermediate circuit is transferred to the network via a series connection of several semiconductor switches.
  • 3-level inverters during the positive half-cycle of the network and to feed in active power, switching back and forth between a medium voltage level and an upper, positive voltage level of the intermediate circuit, for example by means of Pulse width modulation (PWM) to approximate the voltage currently required.
  • PWM Pulse width modulation
  • switching takes place between the average and negative voltage level of the intermediate circuit.
  • the grid is fed into the grid via a line choke, with the help of which the alternating voltage generated by rapid switching between the three voltage levels is smoothed. In this way, an alternating voltage suitable for feeding is generated separately for each phase of the network.
  • inverters used to feed into supply networks are required to be able to feed in a certain proportion of reactive power if necessary in order to be able to ensure the stability of the supply networks even with a high proportion of decentralized energy sources. Since the control of an inverter for feeding in reactive power differs significantly from the control for feeding in active power, passive solutions for avoiding the reverse recovery effect are not optimal with regard to the efficiency of an inverter either.
  • the object of the invention is to provide an inverter for the optional feeding of active and reactive power into a supply network in which there is a possibility of avoiding the reverse recovery effect in every operating state.
  • the inverter for optionally feeding active and reactive power into a supply network has two series-connected intermediate circuit capacitors, the common connection of which defines an average voltage level between a positive voltage level and a negative voltage level. It also has first, second, third and fourth semiconductor switches each with free-wheeling diodes connected in parallel, which lie in series in this order between the positive and negative voltage level, the common connection of the second and third semiconductor switch being connected to the supply network via a choke.
  • the inverter also has series-connected first and second diodes whose common connection is at the medium voltage level and whose second connection is connected to the common connection of the first and second semiconductor switch or the third and fourth semiconductor switch. Common connections of two of the first to fourth semiconductor switches are connected to additional chokes, which by means of additional semiconductor switches form switchable paths to take over freewheeling currents.
  • the inverter is operated as a three-point inverter by switching the common connection of the second and third semiconductor switches by switching operations of the first to fourth semiconductor switches according to the voltage in the supply network either between the medium voltage level and the positive voltage level or between the medium voltage level and the lower voltage level is switched forth, switching operations of the first to fourth semiconductor switches being accompanied by switching operations of the additional semiconductor switches, so that the additional chokes connected to the common connections take over freewheeling currents that occur at times.
  • First, second, third and fourth semiconductor switches S1, S2, S3, S4, each with free-wheeling diodes connected in parallel, are connected in series between the positive voltage level + Uz and the negative voltage level -Uz.
  • the common connection SWP of the second and third semiconductor switches S2, S3 is connected to the supply network Uac via a choke L1.
  • the common connection of two series-connected first and second diodes D1, D2 is connected to the average voltage level 0V, the The second connection of the first diode D1 is connected to the common connection of the first and second semiconductor switches S1, S2, the second connection of the second diode D2 is connected to the common connection of the third and fourth semiconductor switches S3, S4.
  • the choke L1 filters the high switching frequency (PWM frequency, usually a few kHz) with which the first semiconductor switch S1 is clocked, and smooths the fast switching between the two voltage levels 0V and + Uz to a sinusoidal current curve on the network side.
  • PWM frequency usually a few kHz
  • a sinusoidal current curve can be set during the negative half-wave of the mains voltage by clocking switch S4 according to a PWM pattern when switches S1, S2 are open and switch S3 is closed.
  • the first semiconductor switch S1 is clocked during a positive half-cycle of the network Uac, while the second semiconductor switch S2 remains permanently closed.
  • the Figure 1a you can see that when S1 is closed, a current of the positive voltage level + Uz flows into the network via the choke L1. If current flows into the network from the positive voltage level when the network voltage is positive, the current and voltage have the same sign and active power is transferred to the network.
  • the common connection A12 of the first and second semiconductor switches S1, S2 is connected to a second choke L2, the second connection of which is connected to the average voltage level 0V via a third diode D3 and to the positive voltage level + Uz via a fifth semiconductor switch S5.
  • the common connection A34 of the third and fourth semiconductor switches S3, S4 is also connected to a third choke L3, the second connection of which is connected to the average voltage level 0V via a fourth diode D4 and to the negative voltage level -Uz via a sixth semiconductor switch S6.
  • a decaying free-wheeling current flows through L2, which is fed from the mean voltage level 0V via D3.
  • a current from the positive voltage level + Uz flows into the grid again, and the cycle begins again.
  • Feeding in reactive power means that with a positive grid voltage, a current flows from the grid Uac to the inverter, or with a negative grid voltage, a current flows from the inverter into the grid.
  • the common connection SWP of the second and third semiconductor switches S2, S3 is connected to a fourth choke L4, the second connection of which via a seventh semiconductor switch S7 with the average voltage level 0V and via a fifth and sixth diode D5, D6 is connected to the positive voltage level + Uz or to the negative voltage level -Uz, so that the fifth and sixth diode are connected in series and in reverse direction between the positive and negative voltage level + Uz, -Uz .
  • S1, S3 and S4 are open, S2 is operated clocked.
  • SWP is on -Uz. If one were to close S2 again without further measures and thus switch SWP hard to the mean voltage level 0V, the two free-wheeling diodes of S3 and S4 would not be able to block immediately because of the reverse recovery effect - there would be a conductive connection between 0V and -Uz. The freewheeling diodes would be destroyed.
  • the seventh semiconductor switch S7 with which the circuit expansion of the Figures 2a - d is controlled, is to be implemented as a bidirectional switch.
  • the Figure 3 two different variants indicated.
  • two MOSFETs S7 'and S7 are connected in opposite directions in series. If only one switch is conducting, the overall switch functions as a diode.
  • an anti-parallel connection of two MOSFETs S7' can also be used (lower circuit).
  • FIG. 4 is a first alternative for the circuit expansion according to FIG Figures 2a - d shown.
  • the common connection SWP of the second and third semiconductor switches S2, S3 is connected to a fourth choke L4, the second connection of which is connected via an eighth semiconductor switch S8 and via the second diode D2, as well as via a ninth semiconductor switch S9 and via the first diode D1 to the middle one Voltage level 0V is connected.
  • This second connection of the fourth choke is also connected via a fifth or sixth diode D5, D6 to the positive voltage level + Uz or negative voltage level -Uz, the fifth and sixth diode in series and in the reverse direction between the positive and negative voltage level + Uz, -Uz are switched.
  • FIG. 5 Another alternative to the circuit expansion according to the Figures 2a - d or.
  • Figure 4 is in Figure 5 shown.
  • the common connection SWP of the second and third semiconductor switches S2, S3 is connected to a fifth choke L5 and a sixth choke L6, the second connection of the fifth choke L5 via an eighth semiconductor switch S8 and via the second diode D2 with the average voltage level 0V and is connected to the positive voltage level + Uz via an eighth diode D8, and the second connection of the sixth choke L6 via a ninth semiconductor switch S9 and via the first diode D1 with the average voltage level 0V and via a ninth diode D9 with the negative voltage level -Uz is connected.
  • the Figure 6 briefly explains the connections between the feed-in of active and reactive power. If current I and voltage U in the network are exactly in phase, only real power is transported. However, if inductances or capacitances act in the network, then current I and voltage U are as in Figure 6 shown no longer in phase, but shifted against each other by a certain phase angle. This phase angle of mutual shift is usually only a few degrees, so that the current and voltage are the same in the larger areas W Have signs. In areas B, however, the signs are different, so here the direction of energy transport is reversed. So active and reactive power is transported. In the course of time of the Figure 6 So 4 different states can be recognized, each of which makes a different operating mode of the inverter necessary.
  • semiconductor switches S1 - S9 e.g. MOSFETs, IGBTs, SiC-MOSFETs or SiC-JFETs can be used, which may have to be paired with a separate free-wheeling diode.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)
  • Control Of Electrical Variables (AREA)

Description

Die Erfindung betrifft einen Wechselrichter zur Einspeisung von elektrischer Energie in ein Versorgungsnetz. Wechselrichter dienen dazu, eine Gleichspannung in eine Wechselspannung umzuwandeln. Insbesondere im Bereich der Photovoltaik sind hierbei möglichst hohe Wirkungsgrade gefordert.The invention relates to an inverter for feeding electrical energy into a supply network. Inverters are used to convert a direct voltage into an alternating voltage. Particularly in the field of photovoltaics, the highest possible levels of efficiency are required.

Solarmodule zur Umwandlung von Sonnenlicht in elektrische Energie liefern zunächst einen Gleichstrom, der vor der Einspeisung in die Netze der Energieversorger in Wechselstrom umgewandelt werden muss. Hierzu dienen Wechselrichter, wie sie beispielsweise in der US 6392907 B1 beschrieben sind. Die in den Kondensatoren eines Zwischenkreises gespeicherte elektrische Energie wird über eine Reihenschaltung aus mehreren Halbleiterschaltern an das Netz abgegeben. Bei sogenannten 3-Level-Wechselrichtern wird dabei während der positiven Halbwelle des Netzes und zur Einspeisung von Wirkleistung zwischen einem mittleren Spannungsniveau und einem oberen, positiven Spannungsniveau des Zwischenkreises hin und her geschaltet, um beispielsweise mittels Pulsweitenmodulation (PWM) die gerade benötigte Spannung anzunähern. Während der negativen Halbwelle des Netzes erfolgt die Umschaltung zwischen dem mittleren und einem negativen Spannungsniveau des Zwischenkreises. Die Einspeisung ins Netz erfolgt über eine Netzdrossel, mit deren Hilfe die durch schnelles Schalten zwischen den drei Spannungsniveaus erzeugte Wechselspannung geglättet wird. Auf diese Weise wird separat für jede Phase des Netzes eine zur Einspeisung geeignete Wechselspannung erzeugt.Solar modules for converting sunlight into electrical energy first deliver a direct current, which must be converted into alternating current before being fed into the power supply networks. Inverters such as those in the US 6392907 B1 are described. The electrical energy stored in the capacitors of an intermediate circuit is transferred to the network via a series connection of several semiconductor switches. In the case of so-called 3-level inverters, during the positive half-cycle of the network and to feed in active power, switching back and forth between a medium voltage level and an upper, positive voltage level of the intermediate circuit, for example by means of Pulse width modulation (PWM) to approximate the voltage currently required. During the negative half-cycle of the network, switching takes place between the average and negative voltage level of the intermediate circuit. The grid is fed into the grid via a line choke, with the help of which the alternating voltage generated by rapid switching between the three voltage levels is smoothed. In this way, an alternating voltage suitable for feeding is generated separately for each phase of the network.

Die oben zitierte US 6392907 B1 erklärt bereits ein Problem, das durch die schnellen Schaltvorgänge in einem solche Wechselrichter auftritt. Ein Wechselrichter benötigt verschiedenste Dioden und Halbleiterschalter, die in gewissen Betriebszuständen von der Zerstörung bedroht sind, nämlich wenn ein in der Diode fließender Strom durch Umpolen der Diode in Sperrrichtung zu schnell abgeschaltet wird. Denn für einen kurzen Moment nach dem Umpolen ist eine Diode in Sperrrichtung leitend, weil sich noch Ladungsträger in der Sperrzone befinden. Wegen dieses auch als Reverse-Recovery bezeichneten Effektes ist notwendig, die zeitliche Änderung des Stromes und damit die Änderung der über der Diode liegenden Spannung zu begrenzen. In der US 6392907 B1 wird hierzu eine passive Schaltung vorgeschlagen, die diese Aufgabe übernimmt.The one quoted above US 6392907 B1 already explains a problem that occurs due to the fast switching processes in such an inverter. An inverter requires a wide variety of diodes and semiconductor switches, which are threatened with destruction in certain operating states, namely if a current flowing in the diode is switched off too quickly by reversing the polarity of the diode in the reverse direction. Because for a short moment after the polarity has been reversed, a diode is conducting in the reverse direction because there are still charge carriers in the blocking zone. Because of this effect, also known as reverse recovery, it is necessary to limit the change in the current over time and thus the change in the voltage across the diode. In the US 6392907 B1 a passive circuit is proposed for this purpose, which takes on this task.

Eine solche passive Schaltung ist aber nicht in allen Betriebszuständen optimal. So wird heutzutage von zur Einspeisung in Versorgungsnetze dienenden Wechselrichtern verlangt, dass sie bei Bedarf auch einen gewissen Anteil Blindleistung einspeisen können, um die Stabilität der Versorgungsnetze auch bei einem hohen Anteil von dezentral einspeisenden Energiequellen sicherstellen zu können. Da die Ansteuerung eines Wechselrichters zur Einspeisung von Blindleistung sich deutlich von der Ansteuerung zur Einspeisung von Wirkleistung unterscheidet, sind passive Lösungen zur Vermeidung des Reverse-Recovery-Effektes auch hinsichtlich des Wirkungsgrades eines Wechselrichters nicht optimal.However, such a passive circuit is not optimal in all operating states. Nowadays, inverters used to feed into supply networks are required to be able to feed in a certain proportion of reactive power if necessary in order to be able to ensure the stability of the supply networks even with a high proportion of decentralized energy sources. Since the control of an inverter for feeding in reactive power differs significantly from the control for feeding in active power, passive solutions for avoiding the reverse recovery effect are not optimal with regard to the efficiency of an inverter either.

Aus der EP 1047180 A2 und aus der EP 0727870 A2 sind bereits Wechselrichter bekannt, mit denen wahlweise Wirk- und Blindleistung in ein Versorgungsnetz eingespeist werden kann.From the EP 1047180 A2 and from the EP 0727870 A2 Inverters are already known with which active and reactive power can be fed into a supply network.

Aufgabe der Erfindung ist es, einen Wechselrichter für die wahlweise Einspeisung von Wirk- und Blindleistung in ein Versorgungsnetz zu schaffen, bei dem in jedem Betriebszustand eine Möglichkeit zur Vermeidung des Reverse-Recovery-Effektes besteht.The object of the invention is to provide an inverter for the optional feeding of active and reactive power into a supply network in which there is a possibility of avoiding the reverse recovery effect in every operating state.

Diese Aufgabe wird gelöst durch eine Vorrichtung mit den Merkmalen des Anspruches 1. Vorteilhafte Ausführungsformen ergeben sich aus den Merkmalen, die in den von Anspruch 1 abhängigen Ansprüchen aufgeführt sind.This object is achieved by a device with the features of claim 1. Advantageous embodiments result from the features that are listed in the claims dependent on claim 1.

Der Wechselrichter zur wahlweisen Einspeisung von Wirk- und Blindleistung in ein Versorgungsnetz weist zwei in Reihe geschaltete Zwischenkreiskondensatoren auf, deren gemeinsamer Anschluss ein mittleres Spannungsniveau zwischen einem positiven Spannungsniveau und einem negativen Spannungsniveau definiert. Er weist außerdem erste, zweite, dritte und vierte Halbleiterschalter mit jeweils parallel geschalteten Freilaufdioden auf, die seriell in dieser Reihenfolge zwischen dem positiven und dem negativen Spannungsniveau liegen, wobei der gemeinsame Anschluss des zweiten und dritten Halbleiterschalters über eine Drossel mit dem Versorgungsnetz verbunden ist. Der Wechselrichter weist außerdem in Reihe geschaltete erste und zweite Dioden auf, deren gemeinsamer Anschluss auf dem mittleren Spannungsniveau liegt, und deren jeweils zweiter Anschluss mit dem gemeinsamen Anschluss des ersten und zweiten Halbleiterschalters bzw. des dritten und vierten Halbleiterschalters verbunden ist. Gemeinsame Anschlüsse von je zwei der ersten bis vierten Halbleiterschalter sind mit zusätzlichen Drosseln verbunden, die mittels zusätzlicher Halbleiterschalter schaltbare Pfade zur Übernahme von Freilaufströmen bilden.The inverter for optionally feeding active and reactive power into a supply network has two series-connected intermediate circuit capacitors, the common connection of which defines an average voltage level between a positive voltage level and a negative voltage level. It also has first, second, third and fourth semiconductor switches each with free-wheeling diodes connected in parallel, which lie in series in this order between the positive and negative voltage level, the common connection of the second and third semiconductor switch being connected to the supply network via a choke. The inverter also has series-connected first and second diodes whose common connection is at the medium voltage level and whose second connection is connected to the common connection of the first and second semiconductor switch or the third and fourth semiconductor switch. Common connections of two of the first to fourth semiconductor switches are connected to additional chokes, which by means of additional semiconductor switches form switchable paths to take over freewheeling currents.

Der Wechselrichter wird als Dreipunkt-Wechselrichter betrieben, indem der gemeinsame Anschluss des zweiten und dritten Halbleiterschalters durch Schaltvorgänge der ersten bis vierten Halbleiterschalter entsprechend der Spannung im Versorgungsnetz entweder zwischen dem mittleren Spannungsniveau und dem positiven Spanungsniveau oder zwischen dem mittleren Spannungsniveau und dem unteren Spannungsniveau hin und her geschaltet wird, wobei Schaltvorgänge der ersten bis vierten Halbleiterschalter begleitet werden von Schaltvorgängen der zusätzlichen Halbleiterschalter, so dass die mit den gemeinsamen Anschlüssen verbundenen zusätzlichen Drosseln zeitweise anfallende Freilaufströme übernehmen.The inverter is operated as a three-point inverter by switching the common connection of the second and third semiconductor switches by switching operations of the first to fourth semiconductor switches according to the voltage in the supply network either between the medium voltage level and the positive voltage level or between the medium voltage level and the lower voltage level is switched forth, switching operations of the first to fourth semiconductor switches being accompanied by switching operations of the additional semiconductor switches, so that the additional chokes connected to the common connections take over freewheeling currents that occur at times.

Auf diese Weise kann sichergestellt werden, dass rechtzeitig vor kritischen Schaltvorgängen der ersten bis vierten Halbleiterschalter eine langsame Änderung der über den gefährdeten Dioden liegenden Spannung erzeugt wird, indem nämlich Freilaufströme von einer der zusätzlichen Drosseln übernommen werden und dabei eine langsamere Potentialänderung an der gefährdeten Diode bewirken. Ein Reverse-Recovery-Effekt kann so unabhängig davon, ob gerade Wirk- oder Blindleistung eingespeist wird, effektiv verhindert werden, und die jeweils verwendete Schaltung kann auf den jeweiligen Betriebszustand optimiert werden, so dass der Wechselrichter mit insgesamt gutem Wirkungsgrad betrieben werden kann. Weitere Vorteile sowie Einzelheiten der vorliegenden Erfindung ergeben sich aus der nachfolgenden Beschreibung einer bevorzugten Ausführungsform anhand der Figuren. Dabei zeigt

Figur 1a - d
eine Teilschaltung des Wechselrichters zum Einspeisen von Wirkleistung, zusammen mit den hierzu nötigen Verfahrensschritten,
Figur 2a -
d eine Teilschaltung des Wechselrichters zum Einspeisen von Blindleistung, zusammen mit den hierzu nötigen Verfahrensschritten,
Figur 3
alternative Realisierungsformen für einen bidirektionalen Halbleiterschalter,
Figur 4
ein zweites Ausführungspiel für eine Teilschaltung des Wechselrichters zum Einspeisen von Blindleistung,
Figur 5
ein drittes Ausführungspiel für eine Teilschaltung des Wechselrichters zum Einspeisen von Blindleistung,
Figur 6
ein Schaubild zur Erklärung von Wirk- und Blindleistung.
In this way, it can be ensured that a slow change in the voltage across the endangered diodes is generated in good time before critical switching operations of the first to fourth semiconductor switches, namely by taking over freewheeling currents from one of the additional chokes and thereby causing a slower change in potential at the endangered diode . A reverse recovery effect can thus be effectively prevented regardless of whether active or reactive power is being fed in, and the circuit used in each case can be optimized for the respective operating state, so that the inverter can be operated with an overall good efficiency. Further advantages and details of the present invention emerge from the following description of a preferred embodiment based on the figures. It shows
Figure 1a - d
a partial circuit of the inverter for feeding in active power, together with the necessary procedural steps,
Figure 2a -
d a partial circuit of the inverter for feeding in reactive power, together with the process steps required for this,
Figure 3
alternative forms of implementation for a bidirectional semiconductor switch,
Figure 4
a second execution game for a partial circuit of the inverter for feeding in reactive power,
Figure 5
a third execution game for a partial circuit of the inverter for feeding in reactive power,
Figure 6
a diagram to explain active and reactive power.

In der Figur 1a (ebenso wie in den Figuren 1b - d) ist zunächst die Grundschaltung eines 3-Level-Wechselrichters zu erkennen. Zwei in Reihe geschaltete Zwischenkreiskondensatoren C1, C2, deren gemeinsamer Anschluss ein mittleres Spannungsniveau 0V zwischen einem positiven Spannungsniveau +Uz und einem negativen Spannungsniveau -Uz definiert, bilden den Zwischenkreis, in dem elektrische Energie aus den angeschlossenen Solarmodulen gespeichert werden kann. Das mittlere Spannungsniveau 0V ist dabei nicht unbedingt gleichzusetzen mit dem Erdpotential.In the Figure 1a (as well as in the Figures 1b - d ) the basic circuit of a 3-level inverter can be seen first. Two series-connected intermediate circuit capacitors C1, C2, whose common connection defines an average voltage level of 0V between a positive voltage level + Uz and a negative voltage level -Uz, form the intermediate circuit in which electrical energy from the connected solar modules can be stored. The mean voltage level 0V is not necessarily to be equated with the earth potential.

Zwischen dem positiven Spannungsniveau +Uz und dem negativen Spannungsniveau -Uz sind seriell erste, zweite, dritte und vierte Halbleiterschalter S1, S2, S3, S4 mit jeweils parallel geschalteten Freilaufdioden geschaltet.First, second, third and fourth semiconductor switches S1, S2, S3, S4, each with free-wheeling diodes connected in parallel, are connected in series between the positive voltage level + Uz and the negative voltage level -Uz.

Der gemeinsame Anschluss SWP des zweiten und dritten Halbleiterschalters S2, S3 ist über eine Drossel L1 mit dem Versorgungsnetz Uac verbunden.The common connection SWP of the second and third semiconductor switches S2, S3 is connected to the supply network Uac via a choke L1.

Der gemeinsame Anschluss zweier in Reihe geschalteter erster und zweiter Dioden D1, D2 ist mit dem mittleren Spannungsniveau 0V verbunden, der zweite Anschluss der ersten Diode D1 ist mit dem gemeinsamen Anschluss des ersten und zweiten Halbleiterschalters S1, S2 verbunden, der zweite Anschluss der zweiten Diode D2 ist mit dem gemeinsamen Anschluss des dritten und vierten Halbleiterschalters S3, S4 verbunden.The common connection of two series-connected first and second diodes D1, D2 is connected to the average voltage level 0V, the The second connection of the first diode D1 is connected to the common connection of the first and second semiconductor switches S1, S2, the second connection of the second diode D2 is connected to the common connection of the third and fourth semiconductor switches S3, S4.

Während einer positiven Halbwelle im Netz Uac kann nun durch Öffnen der Schalter S3 und S4 und schließen des Schalters S2, sowie durch getakteten Betrieb des Schalters S1 am gemeinsame Anschluss SWP des zweiten und dritten Halbleiterschalters S2, S3 zwischen dem mittleren Spannungsniveau 0V und dem oberen Spannungsniveau +Uz hin und her geschaltet werden. Ist S1 geschlossen, sperrt D1 und SWP liegt auf +Uz. Ist S1 geöffnet, liegt SWP über D1 auf 0V. Die Ansteuerung von S1 kann dabei zum Beispiel mit einer Pulsweitenmodulation (PWM) erfolgen, so dass im zeitlichen Mittel eine Spannung eingestellt werden kann, die der Netzspannung derart folgt, dass sich ein annähernd sinusförmiger Wechselstrom in der Drossel L1 einstellt und an das Netz abgegeben wird. Anders gesagt filtert die Drossel L1 die hohe Schaltfrequenz (PWM-Frequenz, üblicher Weise einige kHz), mit der der erste Halbleiterschalter S1 getaktet wird, und glättet netzseitig die schnelle Umschaltung zwischen den beiden Spannungsniveaus 0V und +Uz zu einem sinusförmigen Stromverlauf.During a positive half-cycle in the network Uac, by opening the switches S3 and S4 and closing the switch S2, as well as by clocked operation of the switch S1 at the common connection SWP of the second and third semiconductor switches S2, S3 between the average voltage level 0V and the upper voltage level + Uz can be switched back and forth. If S1 is closed, D1 blocks and SWP is at + Uz. If S1 is open, SWP is at 0V via D1. The control of S1 can take place, for example, with a pulse width modulation (PWM), so that on average over time a voltage can be set that follows the mains voltage in such a way that an approximately sinusoidal alternating current is established in the choke L1 and is output to the mains . In other words, the choke L1 filters the high switching frequency (PWM frequency, usually a few kHz) with which the first semiconductor switch S1 is clocked, and smooths the fast switching between the two voltage levels 0V and + Uz to a sinusoidal current curve on the network side.

Ganz analog lässt sich während der negativen Halbwelle der Netzspannung ein sinusförmiger Stromverlauf einstellen, indem bei geöffneten Schaltern S1, S2 und geschlossenem Schalter S3 der Schalter S4 nach einem PWM-Muster getaktet wird.In a completely analogous manner, a sinusoidal current curve can be set during the negative half-wave of the mains voltage by clocking switch S4 according to a PWM pattern when switches S1, S2 are open and switch S3 is closed.

Wie gerade erläutert, wird während einer positiven Halbwelle des Netzes Uac der erste Halbleiterschalter S1 getaktet, während der zweite Halbleiterschalter S2 dauerhaft geschlossen bleibt. In der Figur 1a erkennt man, dass dann bei geschlossenem S1 ein Strom vom positiven Spannungsniveau +Uz über die Drossel L1 ins Netz fließt. Fließt bei positiver Netzspannung Strom aus dem positiven Spannungsniveau ins Netz, so haben Strom und Spannung gleiches Vorzeichen, es wird Wirkleistung ans Netz abgegeben.As just explained, the first semiconductor switch S1 is clocked during a positive half-cycle of the network Uac, while the second semiconductor switch S2 remains permanently closed. In the Figure 1a you can see that when S1 is closed, a current of the positive voltage level + Uz flows into the network via the choke L1. If current flows into the network from the positive voltage level when the network voltage is positive, the current and voltage have the same sign and active power is transferred to the network.

In Figur 1b ist die Situation nach dem Öffnen des ersten Halbleiterschalters S1 dargestellt. Der Strom durch L1 wird ab dem Moment des Öffnens von S1 als Freilaufstrom aus dem mittleren Spannungsniveau 0V gezogen und fließt über D1 und S2. Würde man nun S1 im nächsten Schritt einfach wieder schließen, würde D1 nicht sofort sperren, sondern wäre wegen des Reverse-Recovery-Effektes für einen kurzen Moment leitend. Durch die hohe Spannungsdifferenz zwischen 0V und +Uz (einige 100V in einer typischen Photovoltaik-Anlage) würde die Diode D1 stark belastet.In Figure 1b the situation after opening the first semiconductor switch S1 is shown. From the moment S1 is opened, the current through L1 is drawn as a freewheeling current from the mean voltage level 0V and flows through D1 and S2. If you were to simply close S1 again in the next step, D1 would not lock immediately, but would be conductive for a brief moment because of the reverse recovery effect. Due to the high voltage difference between 0V and + Uz (several 100V in a typical photovoltaic system), diode D1 would be heavily loaded.

In der Figur 1a (ebenso wie in den Figuren 1b - d) ist nun außerdem die Schaltungserweiterung dargestellt, die im Falle der Abgabe von Wirkleistung eine Belastung von Dioden durch den Reverse-Recovery-Effekt vermeiden kann.In the Figure 1a (as well as in the Figures 1b - d ), the circuit expansion is now also shown, which can avoid a load on diodes due to the reverse recovery effect in the event of the delivery of active power.

Hierzu ist der gemeinsame Anschluss A12 des ersten und zweiten Halbleiterschalters S1, S2 mit einer zweiten Drossel L2 verbunden, deren zweiter Anschluss über eine dritte Diode D3 mit dem mittleren Spannungsniveau 0V und über einen fünften Halbeiterschalter S5 mit dem positiven Spannungsniveau +Uz verbunden ist. Ebenso ist der gemeinsame Anschluss A34 des dritten und vierten Halbleiterschalters S3, S4 mit einer dritten Drossel L3 verbunden, deren zweiter Anschluss über eine vierte Diode D4 mit dem mittleren Spannungsniveau 0V und über einen sechsten Halbeiterschalter S6 mit dem negativen Spannungsniveau -Uz verbunden ist.For this purpose, the common connection A12 of the first and second semiconductor switches S1, S2 is connected to a second choke L2, the second connection of which is connected to the average voltage level 0V via a third diode D3 and to the positive voltage level + Uz via a fifth semiconductor switch S5. The common connection A34 of the third and fourth semiconductor switches S3, S4 is also connected to a third choke L3, the second connection of which is connected to the average voltage level 0V via a fourth diode D4 and to the negative voltage level -Uz via a sixth semiconductor switch S6.

Wenn wie in Figur 1b der Freilaufstrom aus dem mittleren Spannungsniveau 0V über D1, S2 und L1 ins Netz Uac fließt, wird im nächsten Schritt nicht der Schalter S1 geschlossen, sondern zunächst der bis dahin offene fünfte Halbleiterschalter S5, so dass der in diesem Moment fließende Freilaufstrom wie in der Figur 1c dargestellt von der zweiten Drossel L2 über den fünften Halbleiterschalter S5 vom positiven Spannungsniveau +Uz kommend kontinuierlich ansteigend übernommen wird. Der gemeinsame Anschluss A12 von erstem und zweitem Halbleiterschalter S1, S2 wird so wieder auf das oder nahe an das positive Spannungsniveau +Uz gebracht, bevor dann der erste Halbleiterschalter S1 erneut geschlossen und der fünfte Halbleiterschalter S5 wieder geöffnet wird.If like in Figure 1b If the freewheeling current flows from the mean voltage level 0V via D1, S2 and L1 into the Uac network, switch S1 is not closed in the next step, but rather the fifth semiconductor switch S5, which was open until then, so that the freewheeling current flowing at this moment is as shown in Figure 1c shown is taken from the second choke L2 via the fifth semiconductor switch S5 coming from the positive voltage level + Uz continuously increasing. The common connection A12 of the first and second semiconductor switches S1, S2 is brought back to or close to the positive voltage level + Uz before then the first semiconductor switch S1 is closed again and the fifth semiconductor switch S5 is opened again.

Wie in Figur 1d dargestellt fließt dann ein abklingender Freilaufstrom durch L2, der über D3 aus dem mittleren Spannungsniveau 0V gespeist wird. Außerdem fließt wieder ein Strom aus dem positiven Spannungsniveau +Uz ins Netz, der Zyklus beginnt von neuem.As in Figure 1d As shown, a decaying free-wheeling current flows through L2, which is fed from the mean voltage level 0V via D3. In addition, a current from the positive voltage level + Uz flows into the grid again, and the cycle begins again.

Entscheidend ist also, dass hier vor dem erneuten Einschalten von S1 kurzzeitig der zusätzliche fünfte Halbleiterschalter S5 geschlossen wurde, und somit ein Freilaufstrom, der zunächst über D1 floss, von der zusätzlichen Drossel L2 übernommen wurde. Der langsam ansteigende Strom durch diese Drossel sorgt für einen langsamen Anstieg des Potentials am gemeinsamen Anschluss A12, und vermeidet somit den Reverse-Recovery-Effekt in der Diode D1 beim erneuten Schließen von S1.It is therefore crucial that the additional fifth semiconductor switch S5 was briefly closed before S1 was switched on again, and thus a freewheeling current, which initially flowed via D1, was taken over by the additional choke L2. The slowly increasing current through this choke ensures a slow increase in the potential at the common connection A12, and thus avoids the reverse recovery effect in the diode D1 when S1 is closed again.

Ganz analog sind die Bedingungen und Verfahrensschritte beim Betrieb des Wechselrichters während einer negativen Halbwelle des Netzes Uac.The conditions and process steps when operating the inverter during a negative half-cycle of the grid Uac are completely analogous.

Zunächst fließt bei geschlossenem S4 Strom vom Netz zum negativen Spannungsniveau -Uz, es wird also wieder Wirkleistung ans Netz abgegeben. Nach dem Öffnen von S4 fließt ein Freilaufstrom über D2 zum mittleren Spannungsniveau 0V. Ein sofortiges erneutes Schließen von S4 würde D2 wegen des Reverse-Recovery-Effektes stark belasten, daher wird zunächst S6 geschlossen und der Freilaufstrom von L3 übernommen. Der gemeinsame Anschluss A34 wird so wieder langsam auf das negative Potential -Uz geladen, bevor S4 geschlossen und S6 zeitgleich wieder geöffnet wird. Ein abklingender Freilaufstrom kann dann noch über D4 fließen.First, when S4 is closed, current flows from the grid to the negative voltage level -Uz, so real power is released back into the grid. After opening S4, a freewheeling current flows via D2 to the mean voltage level 0V. Closing S4 again immediately would put a heavy load on D2 because of the reverse recovery effect, so S6 is closed first and the freewheeling current is taken over from L3. The common connection A34 is slowly charged again to the negative potential -Uz before S4 is closed and S6 is opened again at the same time. A decaying freewheeling current can then still flow via D4.

In den Figuren 1a - 1d wurden die Verhältnisse während der Einspeisung von Wirkleistung dargestellt. In den Figuren 2a - 2d sind nun die Verhältnisse bei der Einspeisung von Blindleistung gezeigt. Einspeisung von Blindleistung bedeutet, dass bei positiver Netzspannung ein Strom vom Netz Uac zum Wechselrichter fließt, bzw. bei negativer Netzspannung ein Strom vom Wechselrichter ins Netz fließt.In the Figures 1a - 1d the relationships during the feed-in of active power were shown. In the Figures 2a - 2d the conditions for the feed-in of reactive power are now shown. Feeding in reactive power means that with a positive grid voltage, a current flows from the grid Uac to the inverter, or with a negative grid voltage, a current flows from the inverter into the grid.

Während der Abgabe von Blindleistung sind andere Dioden des Wechselrichters gefährdet, weswegen für diesen Fall auch eine andere Schaltungserweiterung nötig ist. Auch wenn die Erweiterungen der Grundschaltung eines 3-Level-Wechselrichters für die beiden Betriebszustände "Wirkleistung" und "Blindleistung" in den Figuren 1a - d bzw. 2a - d der Übersichtlichkeit halber getrennt dargestellt sind, so sind sie doch in einer einzigen Schaltung realisiert und werden je nach Bedarf mittels der in den Schaltungserweiterungen enthalten zusätzlichen Halbleiterschaltern aktiviert.During the delivery of reactive power, other diodes of the inverter are at risk, which is why another circuit expansion is necessary for this case. Even if the extensions to the basic circuit of a 3-level inverter for the two operating states "active power" and "reactive power" are in the Figures 1a - d or. 2a - d are shown separately for the sake of clarity, they are nevertheless implemented in a single circuit and are activated as required by means of the additional semiconductor switches contained in the circuit expansions.

Gemäß einer besonders einfachen Schaltungserweiterung zur Übernahme von Freilaufströmen während der Abgabe von Blindleistung ist der gemeinsame Anschluss SWP des zweiten und dritten Halbleiterschalters S2, S3 mit einer vierten Drossel L4 verbunden, deren zweiter Anschluss über einen siebten Halbleiterschalter S7 mit dem mittleren Spannungsniveau 0V und über eine fünfte bzw. sechste Diode D5, D6 mit dem positiven Spannungsniveau +Uz bzw. mit dem negativen Spannungsniveau -Uz verbunden ist, so dass die fünfte und sechste Diode in Reihe und in Sperrrichtung zwischen dem positiven und negativen Spannungsniveau +Uz, -Uz geschaltet sind.According to a particularly simple circuit expansion for taking over freewheeling currents during the delivery of reactive power, the common connection SWP of the second and third semiconductor switches S2, S3 is connected to a fourth choke L4, the second connection of which via a seventh semiconductor switch S7 with the average voltage level 0V and via a fifth and sixth diode D5, D6 is connected to the positive voltage level + Uz or to the negative voltage level -Uz, so that the fifth and sixth diode are connected in series and in reverse direction between the positive and negative voltage level + Uz, -Uz .

Analog zu den Figuren 1a - d ist in den Figuren 2a - d die Ansteuerung des Wechselrichters dargestellt, in diesem Fall bei der Einspeisung von Blindleistung während der negativen Halbwelle des Netzes Uac.Analogous to the Figures 1a - d is in the Figures 2a - d the control of the inverter is shown, in this case when reactive power is fed in during the negative half-cycle of the grid Uac.

Zur Einspeisung von Blindleistung während der negativen Halbwelle des Netzes Uac sind S1, S3 und S4 geöffnet, S2 wird getaktet betrieben.To feed in reactive power during the negative half-cycle of the network Uac, S1, S3 and S4 are open, S2 is operated clocked.

Im ersten, in der Figur 2a dargestellten Schritt fließt Strom durch die Drossel L1 ins Netz Uac, während dort negatives Potential herrscht. Dieser Strom wird vom mittleren Potential 0V des Zwischenkreises gezogen und fließt über D1 und den geschlossenen zweiten Halbleiterschalter S2. Im nächsten Schritt gemäß Figur 2b wird S2 geöffnet, der Freilaufstrom wird dann vom negativen Potential -Uz über die dem dritten bzw. vierten Halbleiterschalter S3, S4 parallel geschalteten Freilaufdioden gezogen.In the first, in the Figure 2a In the step shown, current flows through the inductor L1 into the Uac network, while negative potential prevails there. This current is drawn from the mean potential 0V of the intermediate circuit and flows via D1 and the closed second semiconductor switch S2. In the next step according to Figure 2b if S2 is opened, the freewheeling current is then drawn from the negative potential -Uz via the freewheeling diodes connected in parallel to the third and fourth semiconductor switches S3, S4.

Zum Ende dieser zweiten Phase liegt SWP auf -Uz. Würde man nun ohne weitere Maßnahmen S2 wieder schließen und SWP damit hart auf das mittlere Spannungsniveau 0V schalten, könnten die beiden Freilaufdioden von S3 und S4 wegen des Reverse-Recovery-Effektes nicht sofort sperren - es bestünde eine leitende Verbindung zwischen 0V und -Uz. Die Freilaufdioden würden zerstört.At the end of this second phase, SWP is on -Uz. If one were to close S2 again without further measures and thus switch SWP hard to the mean voltage level 0V, the two free-wheeling diodes of S3 and S4 would not be able to block immediately because of the reverse recovery effect - there would be a conductive connection between 0V and -Uz. The freewheeling diodes would be destroyed.

Daher wird im dritten, in Figur 2c dargestellten Schritt, zunächst der bis dahin geöffnete siebte Halbleiterschalter S7 geschlossen. Der Freilaufstrom durch L1 wird dann langsam ansteigend von L4 übernommen, und das Potential von SWP langsam auf das mittlere Spannungsniveau 0V angehoben.Hence, in the third, in Figure 2c illustrated step, initially the seventh semiconductor switch S7, which has been open until then, is closed. The freewheeling current through L1 is then taken over by L4, slowly increasing, and the potential of SWP is slowly raised to the mean voltage level 0V.

Erst dann wird S2 wieder geschlossen und S7 zeitgleich geöffnet, was nun erneut einen Strom aus dem mittleren Potential 0V über D1 und S2 fließen lässt, außerdem klingt der Strom durch L4 - nun von -Uz über D6 kommend - ab, und die in Figur 2a dargestellte Phase beginnt erneut.Only then is S2 closed again and S7 opened at the same time, which now allows a current to flow again from the mean potential 0V via D1 and S2, and the current through L4 - now coming from -Uz via D6 - decays, and the in Figure 2a phase shown begins again.

Für die Einspeisung von Blindleistung bei positivem Potential im Netz Uac gilt: Strom fließt nun durch L1 in den Wechselrichter. S1, S2 und S4 sind geöffnet, S3 wird getaktet betrieben, um z.B. über ein PWM-Verfahren die nötige Spannung einzustellen. Der Freilauf nach dem Öffnen von S3 fließt über die Freilaufdioden von S1 und S2, so dass sich SWP auf +Uz lädt. Vor dem erneuten Schließen von S3 wird S7 geschlossen, um über L4 ein langsames absenken des Potentials an SWP auf 0V zu erreichen. Erst dann wird S3 geschlossen und S7 zeitgleich geöffnet, der Freilaufstrom in L4 klingt über D5 von +Uz kommend ab, der Zyklus beginnt von neuem.The following applies to the feed-in of reactive power when there is a positive potential in the grid Uac: Current now flows through L1 into the inverter. S1, S2 and S4 are open, S3 is operated clocked, e.g. to set the required voltage using a PWM process. The freewheeling after opening S3 flows through the freewheeling diodes of S1 and S2, so that SWP charges to + Uz. Before S3 closes again, S7 is closed in order to achieve a slow lowering of the potential at SWP to 0V via L4. Only then is S3 closed and S7 opened at the same time, the freewheeling current in L4 decays via D5 coming from + Uz, the cycle begins again.

Versieht man also die Grundschaltung eines 3-Level-Wechselrichters mit den Schaltungserweiterungen der Figuren 1a bzw. 2a, so erhält man einen Wechselrichter, mit dem sowohl Wirkleistung als auch Blindleistung in ein Netz eingespeist werden können, indem durch eine aktive Ansteuerung der Schaltungserweiterung eine Belastung von Dioden durch den Reverse-Recovery-Effekt vermieden werden kann. Die jeweils nicht benötigte und damit nicht angesteuerte Erweiterung ist inaktiv und beeinträchtigt den Wirkungsgrad des Wechselrichters nicht unnötig.So if you provide the basic circuit of a 3-level inverter with the circuit expansions of the Figures 1a or 2a, an inverter is obtained with which both active power and reactive power can be fed into a network by actively controlling the circuit expansion, in which the reverse recovery effect can prevent the diodes from being loaded. The respectively not required and Any expansion that is not activated is inactive and does not unnecessarily impair the efficiency of the inverter.

Der siebte Halbleiterschalter S7, mit dem die Schaltungserweiterung der Figuren 2a - d gesteuert wird, ist als bidirektionaler Schalter auszuführen. Hierzu sind in der Figur 3 zwei verschiedene Varianten angegeben. Einmal (obere Schaltung) sind zwei MOSFETs S7' und S7" gegensinnig in Serie geschaltet. Ist nur ein Schalter leitend, funktioniert der Gesamtschalter als Diode. Um die Diodeneigenschaft noch zu verbessern, kann auch (untere Schaltung) eine antiparallele Schaltung zweier MOSFETs S7', S7" verwendet werden, die außerdem noch in Serie jeweils eine Diode gegensinnig zur internen Bodydiode des jeweiligen MOSFETs aufweisen.The seventh semiconductor switch S7, with which the circuit expansion of the Figures 2a - d is controlled, is to be implemented as a bidirectional switch. For this purpose, the Figure 3 two different variants indicated. Once (upper circuit), two MOSFETs S7 'and S7 "are connected in opposite directions in series. If only one switch is conducting, the overall switch functions as a diode. To improve the diode properties, an anti-parallel connection of two MOSFETs S7' can also be used (lower circuit). , S7 "are used, which also each have a diode in series in the opposite direction to the internal body diode of the respective MOSFET.

In der Figur 4 ist eine erste Alternative für die Schaltungserweiterung gemäß der Figuren 2a - d gezeigt. Der gemeinsame Anschluss SWP des zweiten und dritten Halbleiterschalters S2, S3 ist mit einer vierten Drossel L4 verbunden, deren zweiter Anschluss über einen achten Halbleiterschalter S8 und über die zweite Diode D2, sowie über einen neunten Halbleiterschalter S9 und über die erste Diode D1 mit dem mittleren Spannungsniveau 0V verbunden ist. Dieser zweite Anschluss der vierten Drossel ist außerdem über eine fünfte bzw. sechste Diode D5, D6 mit dem positiven Spannungsniveau +Uz bzw. negativen Spannungsniveau -Uz verbunden, wobei die fünfte und sechste Diode in Reihe und in Sperrrichtung zwischen dem positiven und negativen Spannungsniveau +Uz, -Uz geschaltet sind.In the Figure 4 is a first alternative for the circuit expansion according to FIG Figures 2a - d shown. The common connection SWP of the second and third semiconductor switches S2, S3 is connected to a fourth choke L4, the second connection of which is connected via an eighth semiconductor switch S8 and via the second diode D2, as well as via a ninth semiconductor switch S9 and via the first diode D1 to the middle one Voltage level 0V is connected. This second connection of the fourth choke is also connected via a fifth or sixth diode D5, D6 to the positive voltage level + Uz or negative voltage level -Uz, the fifth and sixth diode in series and in the reverse direction between the positive and negative voltage level + Uz, -Uz are switched.

Die Ansteuerung dieser alternativen Schaltungserweiterung zur Einspeisung von Blindleistung erfolgt analog zur Ansteuerung im Falle der Figuren 2a - d. Während dort nach dem Schließen von S7 der Freilaufstrom durch L4 direkt aus dem mittleren Potential 0V gezogen wurde, fließt der Freilaufstrom hier über D1, S9 und L4 ins Netz (während der negativen Halbwelle des Netzes Uac), bzw. über L4, S8 und D2 aus dem Netz zum mittleren Potential 0V (während der positiven Halbwelle des Netzes Uac). Entsprechend wird also während der negativen Halbwelle S9 getaktet betätigt, während der positiven Halbwelle S8.The control of this alternative circuit expansion for feeding in reactive power takes place in the same way as the control in the case of the Figures 2a - d . While there, after the closing of S7, the freewheeling current was drawn directly from the mean potential 0V through L4, the freewheeling current flows into the grid via D1, S9 and L4 (during the negative half-cycle of the grid Uac), or via L4, S8 and D2 from the network to the mean potential 0V (during the positive half-wave of the network Uac). Accordingly, S9 is actuated in a clocked manner during the negative half-wave, while S8 is actuated during the positive half-wave.

Eine weitere Alternative zur Schaltungserweiterung nach den Figuren 2a - d bzw. Figur 4 ist in Figur 5 gezeigt. Hier ist der gemeinsame Anschluss SWP des zweiten und dritten Halbleiterschalters S2, S3 mit einer fünften Drossel L5 und einer sechsten Drossel L6 verbunden, wobei der zweite Anschluss der fünften Drossel L5 über einen achten Halbleiterschalter S8 und über die zweite Diode D2 mit dem mittleren Spannungsniveau 0V und über eine achte Diode D8 mit dem positiven Spannungsniveau +Uz verbunden ist, und wobei der zweite Anschluss der sechsten Drossel L6 über einen neunten Halbleiterschalter S9 und über die erste Diode D1 mit dem mittleren Spannungsniveau 0V und über eine neunte Diode D9 mit dem negativen Spannungsniveau -Uz verbunden ist.Another alternative to the circuit expansion according to the Figures 2a - d or. Figure 4 is in Figure 5 shown. Here the common connection SWP of the second and third semiconductor switches S2, S3 is connected to a fifth choke L5 and a sixth choke L6, the second connection of the fifth choke L5 via an eighth semiconductor switch S8 and via the second diode D2 with the average voltage level 0V and is connected to the positive voltage level + Uz via an eighth diode D8, and the second connection of the sixth choke L6 via a ninth semiconductor switch S9 and via the first diode D1 with the average voltage level 0V and via a ninth diode D9 with the negative voltage level -Uz is connected.

Mit dieser Abänderung, die ausgehend von der Variante der Figur 4 im Wesentlichen aus einer doppelten Ausführung der zusätzlichen Drossel L4 besteht, werden Probleme mit dem Reverse-Recovery-Effekt vermieden, die sich in der Schaltungserweiterung gemäß Figur 4 ergeben können, wenn S8 und S9 als MOSFETs ausgebildet sind. Entsprechend fließt der Freilaufstrom bei der Einspeisung von Blindleistung während der negativen Halbwelle im Netz über D1, S9 und L6 vom mittleren Niveau 0V ins Netz, und während der positiven Halbwelle über L5, S8 und D2 aus dem Netz zum mittleren Niveau.With this amendment, based on the variant of the Figure 4 consists essentially of a double design of the additional choke L4, problems with the reverse recovery effect, which are in accordance with the circuit extension, are avoided Figure 4 can result if S8 and S9 are designed as MOSFETs. Correspondingly, when reactive power is fed in, the free-wheeling current flows into the network during the negative half-cycle via D1, S9 and L6 from the mean level 0V, and during the positive half-cycle via L5, S8 and D2 from the network to the mean level.

Es sei noch einmal erwähnt, dass die in den Figuren 1a - d erklärte Schaltungserweiterung zur Einspeisung von Wirkleistung kombiniert werden muss mit einer der in den Figuren 2a - d, 4 oder 5 erklärten Alternativen für eine Schaltungserweiterung zur Einspeisung von Blindleistung.It should be mentioned again that the Figures 1a - d The declared circuit extension for the infeed of active power must be combined with one of the in the Figures 2a - d , 4th or 5 declared alternatives for a circuit expansion for feeding in reactive power.

Die Figur 6 erklärt kurz die Zusammenhänge der Einspeisung von Wirk- und Blindleistung. Sind Strom I und Spannung U im Netz genau in Phase, so wird nur Wirkleistung transportiert. Wirken jedoch Induktivitäten bzw. Kapazitäten im Netz, so sind Strom I und Spannung U wie in Figur 6 dargestellt nicht mehr Phasengleich, sondern um einen bestimmten Phasenwinkel gegeneinander verschoben. Üblicherweise ist dieser Phasenwinkel der gegenseitigen Verschiebung nur wenige Grad groß, so dass in den größeren Bereichen W Strom und Spannung das gleiche Vorzeichen haben. In den Bereichen B sind die Vorzeichen jedoch unterschiedlich, hier dreht sich also die Richtung des Energietransportes um. Es wird also Wirk- und Blindleistung transportiert. Im zeitlichen Verlauf der Figur 6 sind also 4 verschiedene Zustände zu erkennen, die jeweils eine unterschiedliche Betriebsart des Wechselrichters notwendig machen. Zunächst wird bei positiver Halbwelle der Netzspannung U Strom in positiver Richtung in das Netz eingespeist (positiver Leistungsbeitrag, hier als Wirkleistung bezeichnet), dann bei positiver Netzspannung die Stromrichtung umgekehrt (negativer Leistungsbeitrag, hier als Blindleistung bezeichnet), sodann bei negativer Netzspannung Strom weiterhin in negativer Richtung Netz entnommen (positiver Leistungsbeitrag) und zuletzt bei negativer Netzspannung die Stromrichtung wiederum umgekehrt (negativer Leistungsbeitrag). Die jeweilige Ansteuerung aller Halbleiterschalter des Wechselrichters für jede Betriebsart wurde oben erklärt. Während einer Periode des Netzes kommen also nacheinander alle vier Betriebsarten zum Einsatz.The Figure 6 briefly explains the connections between the feed-in of active and reactive power. If current I and voltage U in the network are exactly in phase, only real power is transported. However, if inductances or capacitances act in the network, then current I and voltage U are as in Figure 6 shown no longer in phase, but shifted against each other by a certain phase angle. This phase angle of mutual shift is usually only a few degrees, so that the current and voltage are the same in the larger areas W Have signs. In areas B, however, the signs are different, so here the direction of energy transport is reversed. So active and reactive power is transported. In the course of time of the Figure 6 So 4 different states can be recognized, each of which makes a different operating mode of the inverter necessary. First, with a positive half-wave of the grid voltage U, current is fed into the grid in a positive direction (positive power contribution, here referred to as active power), then with a positive grid voltage the direction of the current is reversed (negative power contribution, here referred to as reactive power), then with a negative grid voltage, power continues in in the negative direction of the grid (positive power contribution) and finally with a negative grid voltage the direction of the current is reversed again (negative power contribution). The respective control of all semiconductor switches of the inverter for each operating mode was explained above. During one period of the network, all four operating modes are used one after the other.

Als Halbleiterschalter S1 - S9 können z.B. MOSFETs , IGBTs, SiC-MOSFETs oder SiC-JFETs verwendet werden, die gegebenenfalls mit einer separaten Freilaufdiode gepaart werden müssen.As semiconductor switches S1 - S9, e.g. MOSFETs, IGBTs, SiC-MOSFETs or SiC-JFETs can be used, which may have to be paired with a separate free-wheeling diode.

Alle in den Figuren 1a - d, 2a - d, 4 und 5 gezeigten Schaltungen betrafen die Einspeisung in eine Netzphase. Für ein mehrphasiges Netz wird die Schaltung nach den Zwischenkreiskondensatoren entsprechend mehrfach ausgeführt.All in the Figures 1a - d , 2a - d , 4th and 5 The circuits shown concerned the feed into a network phase. For a multi-phase network, the circuit after the intermediate circuit capacitors is carried out several times accordingly.

Claims (5)

  1. Inverter for selectively supplying active power and reactive power to a power supply system, having two intermediate circuit capacitors (C1, C2) connected in series, the common terminal of which defines an average voltage level (0V) between a positive voltage level (+Uz) and a negative voltage level (-Uz), and having first, second, third and fourth semiconductor switches (S1, S2, S3, S4) with free-wheeling diodes respectively connected in parallel, which semiconductor switches are arranged in series in this order between the positive and the negative voltage level, wherein the common terminal (SWP) of the second and third semiconductor switch (S2, S3) is connected to the power supply system (Uac) by way of a choke (L1), and having first and second diodes (D1, D2) connected in series, the common terminal of which is at the average voltage level (0V), and the respective second terminal of which is connected to the common terminal of the first and second semiconductor switch (S1, S2) or of the third and fourth semiconductor switch (S3, S4), characterized in that common terminals (A12, SWP, A34) of in each case two of the first to fourth semiconductor switches (S1, S2, S3, S4) are connected to additional chokes (L2, L3, L4, L5) which form switchable paths for accepting free-wheeling currents by means of additional semiconductor switches (S5, S6, S7, S8, S9), and in that the common terminal (A12) of the first and second semiconductor switch (S1, S2) is connected to a second choke (L2) in order to accept free-wheeling currents during the output of active power, the second terminal of which is connected to the average voltage level (0V) by way of a third diode (D3) and to the positive voltage level (+Uz) by way of a fifth semiconductor switch (S5), and in that the common terminal (A34) of the third and fourth semiconductor switch (S3, S4) is connected to a third choke (L3), the second terminal of which is connected to the average voltage level (0V) by way of a fourth diode (D4) and to the negative voltage level (-Uz) by way of a sixth semiconductor switch (S6).
  2. Inverter according to Claim 1, characterized in that the common terminal (SWP) of the second and third semiconductor switch (S2, S3) is connected to a fourth choke (L4) in order to accept free-wheeling currents during the output of reactive power, the second terminal of which is connected to the average voltage level (0V) by way of a seventh semiconductor switch (S7) and to the positive voltage level (+Uz) or negative voltage level (-Uz) by way of a fifth or sixth diode (D5, D6), wherein the fifth and sixth diode are connected in series and are reverse-biased between the positive and negative voltage level (+Uz, -Uz).
  3. Inverter according to Claim 1, characterized in that the common terminal (SWP) of the second and third semiconductor switch (S2, S3) is connected to a fourth choke (L4), the second terminal of which is connected to the average voltage level (0V) by way of an eighth semiconductor switch (S8) and by way of the second diode (D2), and also by way of a ninth semiconductor switch (S9) and by way of the first diode (D1), and is also connected to the positive voltage level (+Uz) or negative voltage level (-Uz) by way of a fifth or sixth diode (D5, D6), wherein the fifth and sixth diode are connected in series and are reverse-biased between the positive and negative voltage level (+Uz, -Uz).
  4. Inverter according to Claim 1, characterized in that the common terminal (SWP) of the second and third semiconductor switch (S2, S3) is connected to a fifth choke (L5) and a sixth choke (L6), wherein the second terminal of the fifth choke (L5) is connected to the average voltage level (0V) by way of an eighth semiconductor switch (S8) and by way of the second diode (D2) and to the positive voltage level (+Uz) by way of an eighth diode (D8), and wherein the second terminal of the sixth choke (L6) is connected to the average voltage level (0V) by way of a ninth semiconductor switch (S9) and by way of the first diode (D1) and to the negative voltage level (-Uz) by way of a ninth diode (D9).
  5. Inverter according to one of the preceding claims, characterized in that the intermediate circuit capacitors (C1, C2) are fed from a photovoltaic installation.
EP13154035.3A 2012-04-02 2013-02-05 Multilevel NPC Inverter Active EP2658102B1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE102012205335A DE102012205335A1 (en) 2012-04-02 2012-04-02 inverter

Publications (3)

Publication Number Publication Date
EP2658102A2 EP2658102A2 (en) 2013-10-30
EP2658102A3 EP2658102A3 (en) 2018-01-03
EP2658102B1 true EP2658102B1 (en) 2021-04-07

Family

ID=47678629

Family Applications (1)

Application Number Title Priority Date Filing Date
EP13154035.3A Active EP2658102B1 (en) 2012-04-02 2013-02-05 Multilevel NPC Inverter

Country Status (5)

Country Link
US (1) US9667172B2 (en)
EP (1) EP2658102B1 (en)
JP (1) JP6114601B2 (en)
CN (1) CN103368434A (en)
DE (1) DE102012205335A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AT512409B1 (en) * 2012-02-06 2013-08-15 Fronius Int Gmbh AC / DC VOLTAGE CONVERTER AND OPERATING PROCEDURES THEREFOR
DE102015207454A1 (en) * 2015-04-23 2016-10-27 Dr. Johannes Heidenhain Gmbh Switching power supply for supplying an inverter
TWI627828B (en) 2017-03-13 2018-06-21 台達電子工業股份有限公司 Power inverter and power inverting method
DE102017125548A1 (en) * 2017-11-01 2019-05-02 Sma Solar Technology Ag CIRCUIT ARRANGEMENT AND POWER ELECTRONIC TRANSFORMER

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69610000T2 (en) * 1995-02-14 2001-05-17 Toshiba Kawasaki Kk Power converter
JPH08289561A (en) * 1995-02-14 1996-11-01 Toshiba Corp Power converter
US5684688A (en) * 1996-06-24 1997-11-04 Reliance Electric Industrial Company Soft switching three-level inverter
SE512795C2 (en) * 1998-09-18 2000-05-15 Abb Ab VSCconverter
EP1047180A3 (en) * 1999-04-20 2001-04-11 ABBPATENT GmbH ARCP three-point power converter or multi-point power converter
JP3745561B2 (en) * 1999-06-28 2006-02-15 東芝三菱電機産業システム株式会社 Multi-level neutral point potential fixed power converter
DE10143279B4 (en) * 2001-09-04 2009-05-28 Semikron Elektronik Gmbh & Co. Kg frequency converter
TWI346441B (en) * 2006-11-10 2011-08-01 Delta Electronics Inc Three-level ac generating circuit and control method thereof
US8867248B2 (en) * 2011-12-20 2014-10-21 Kohler Co. High-efficiency, three-level, single-phase inverter

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
None *

Also Published As

Publication number Publication date
CN103368434A (en) 2013-10-23
EP2658102A2 (en) 2013-10-30
JP6114601B2 (en) 2017-04-12
DE102012205335A1 (en) 2013-10-02
US20130258737A1 (en) 2013-10-03
US9667172B2 (en) 2017-05-30
EP2658102A3 (en) 2018-01-03
JP2013215087A (en) 2013-10-17

Similar Documents

Publication Publication Date Title
DE102011108920B4 (en) Electric drive system
DE102010052934B4 (en) New multilevel converter topology with the possibility of dynamic serial and parallel connection of individual modules
EP3014725B1 (en) Energy storage device having a dc voltage supply circuit and method for providing a dc voltage from an energy storage device
EP2023475B1 (en) Inversion for a grounded DC source, in particular a photovoltaic generator
EP2647119B1 (en) Novel multi-level converter topology with the possibility of dynamically connecting individual modules in series and in parallel
EP2309639B1 (en) Reactive power-capable inverter
DE102006010694B4 (en) Inverter circuit for extended input voltage range
DE102019120615B3 (en) Process and circuit for providing extended switching states for modular multilevel converters with half bridges
EP2030299B1 (en) Inverter for feeding electrical energy into a power supply system
WO2017016674A1 (en) Individual module, electrical converter system, and battery system
EP2026457A1 (en) Inverter with two intermediate circuits
EP2852044B1 (en) Bidirectional converter with preferred direction and inverter with reactive power capability
EP2026456A1 (en) Inverter
EP2658102B1 (en) Multilevel NPC Inverter
DE102011052768A1 (en) Inverters with coupled inductors
DE102011116593B4 (en) Inverter with asymmetrical chokes and a control unit for asymmetric operation of the chokes
EP1976103B1 (en) Soft switching converter and method for its operation
WO2017025490A1 (en) Polarity reverser, inverter having reactive-power capability, and polarity reversing method
WO2013186006A2 (en) Multicell converter
EP4150753A1 (en) 3-phase pv inverter with 2-phase isolated operation in the event of a network fault
EP3363091A1 (en) Device and method for controlling a load flow in an alternating-voltage network
WO2016012465A1 (en) Switching assembly for an npc multi-point inverter having relief network
WO2013092286A2 (en) Commutation cell having a statically relieved diode
DE202010007787U1 (en) DC voltage regulator
DE102015113247A1 (en) Inverter with a discharge capacitor and photovoltaic system comprising an inverter

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

AX Request for extension of the european patent

Extension state: BA ME

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

AX Request for extension of the european patent

Extension state: BA ME

RIC1 Information provided on ipc code assigned before grant

Ipc: H02M 7/487 20070101AFI20171124BHEP

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE

17P Request for examination filed

Effective date: 20180703

RBV Designated contracting states (corrected)

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: GRANT OF PATENT IS INTENDED

RIC1 Information provided on ipc code assigned before grant

Ipc: H02M 7/487 20070101AFI20200924BHEP

INTG Intention to grant announced

Effective date: 20201021

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE PATENT HAS BEEN GRANTED

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

Free format text: NOT ENGLISH

REG Reference to a national code

Ref country code: AT

Ref legal event code: REF

Ref document number: 1380973

Country of ref document: AT

Kind code of ref document: T

Effective date: 20210415

Ref country code: CH

Ref legal event code: EP

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 502013015620

Country of ref document: DE

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

Free format text: LANGUAGE OF EP DOCUMENT: GERMAN

REG Reference to a national code

Ref country code: LT

Ref legal event code: MG9D

REG Reference to a national code

Ref country code: NL

Ref legal event code: MP

Effective date: 20210407

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: HR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210407

Ref country code: BG

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210707

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210407

Ref country code: LT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210407

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210407

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210407

Ref country code: PL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210407

Ref country code: PT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210809

Ref country code: NO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210707

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210807

Ref country code: LV

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210407

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210708

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210407

Ref country code: RS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210407

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 502013015620

Country of ref document: DE

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: RO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210407

Ref country code: EE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210407

Ref country code: CZ

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210407

Ref country code: DK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210407

Ref country code: SM

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210407

Ref country code: SK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210407

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed

Effective date: 20220110

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210807

Ref country code: AL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210407

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210407

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MC

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210407

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

REG Reference to a national code

Ref country code: BE

Ref legal event code: MM

Effective date: 20220228

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20220205

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LU

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20220205

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20220228

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20220228

Ref country code: IE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20220205

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20220205

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20220228

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: BE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20220228

REG Reference to a national code

Ref country code: AT

Ref legal event code: MM01

Ref document number: 1380973

Country of ref document: AT

Kind code of ref document: T

Effective date: 20220205

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: AT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20220205

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: HU

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT; INVALID AB INITIO

Effective date: 20130205

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210407

Ref country code: CY

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210407

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20240219

Year of fee payment: 12

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: TR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210407