EP2625558B1 - Opto-electronic assembly for a line card - Google Patents
Opto-electronic assembly for a line card Download PDFInfo
- Publication number
- EP2625558B1 EP2625558B1 EP11831336.0A EP11831336A EP2625558B1 EP 2625558 B1 EP2625558 B1 EP 2625558B1 EP 11831336 A EP11831336 A EP 11831336A EP 2625558 B1 EP2625558 B1 EP 2625558B1
- Authority
- EP
- European Patent Office
- Prior art keywords
- optical
- photo
- detectors
- layer
- support plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000005693 optoelectronics Effects 0.000 title description 10
- 230000003287 optical effect Effects 0.000 claims description 112
- 239000000758 substrate Substances 0.000 claims description 50
- 125000006850 spacer group Chemical group 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 230000004044 response Effects 0.000 claims description 4
- 230000003595 spectral effect Effects 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims 2
- 239000000463 material Substances 0.000 description 12
- 238000000034 method Methods 0.000 description 9
- 239000000919 ceramic Substances 0.000 description 7
- 230000006870 function Effects 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000002955 isolation Methods 0.000 description 5
- 230000003993 interaction Effects 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 238000004891 communication Methods 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 229910010293 ceramic material Inorganic materials 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000010348 incorporation Methods 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000001338 self-assembly Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4201—Packages, e.g. shape, construction, internal or external details
- G02B6/4204—Packages, e.g. shape, construction, internal or external details the coupling comprising intermediate optical elements, e.g. lenses, holograms
- G02B6/4214—Packages, e.g. shape, construction, internal or external details the coupling comprising intermediate optical elements, e.g. lenses, holograms the intermediate optical element having redirecting reflective means, e.g. mirrors, prisms for deflecting the radiation from horizontal to down- or upward direction toward a device
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/36—Mechanical coupling means
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B6/12004—Combinations of two or more optical elements
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B6/12007—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind forming wavelength selective elements, e.g. multiplexer, demultiplexer
- G02B6/12009—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind forming wavelength selective elements, e.g. multiplexer, demultiplexer comprising arrayed waveguide grating [AWG] devices, i.e. with a phased array of waveguides
- G02B6/12026—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind forming wavelength selective elements, e.g. multiplexer, demultiplexer comprising arrayed waveguide grating [AWG] devices, i.e. with a phased array of waveguides characterised by means for reducing the temperature dependence
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0203—Containers; Encapsulations, e.g. encapsulation of photodiodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
Definitions
- the present invention relates to optical communication equipment and, more specifically but not exclusively, to line cards.
- An optical line card is used for interfacing optical communication lines, e.g., carrying optical signals to and from the subscribers, to the rest of the telecommunications access network.
- a typical optical line card is a modular opto-electronic circuit assembled on a printed circuit board. Its representative modules may include an optical transmitter, an optical receiver, an optical add/drop multiplexer, a digital signal processor, a controller, a power-management unit, a performance monitor, various optical and electrical interfaces, etc.
- a monolithic integrated circuit is usually fabricated on a single piece of semiconductor substrate, e.g., by (i) incorporating dopants into the substrate, (ii) depositing and patterning additional layers of material, and (iii) metallizing and packaging the resulting chip
- US20060239605 discloses a stepped substrate with mounted optical components.
- US20050249509 discloses the use of heaters to control the temperature of a laser and a modulator to maintain wavelength control.
- a hybrid integrated circuit is a multi-component circuit constructed of multiple monolithic integrated circuits.
- one circuit may include semiconductor and optical devices, and the other circuit may include one or more passive components, with both monolithic circuits being arranged over the same mechanical sub-mount.
- neither monolithic nor hybrid integration has allowed straightforward production of both the passive optical elements and the electro-optical elements of an optical transmitter or receiver.
- the opto-electronic assembly is a hybrid integrated circuit having an array of avalanche photodiodes (APDs) that are electrically coupled to a corresponding array of transimpedance amplifiers (TIAs), with both the APDs and TIAs being mounted on a common ceramic substrate.
- the opto-electronic assembly further has an optical subassembly comprising an arrayed waveguide grating (AWG) and an array of turning mirrors, both attached to a temperature-control unit in a side-by-side arrangement and flip-chip mounted on the substrate over the APDs.
- ASG arrayed waveguide grating
- turning mirrors both attached to a temperature-control unit in a side-by-side arrangement and flip-chip mounted on the substrate over the APDs.
- the opto-electronic assembly employs a silicon-based submount inserted between the APDs and the substrate to accommodate the height difference between the APDs and the TIAs.
- the submount advantageously enables the placement of APDs in relatively close proximity to the turning mirrors while providing good control of the APD's tilt and offset distance with respect to the substrate.
- the temperature-control unit enables independent temperature control of the AWG and of the array of turning mirrors, which helps to achieve good optical-coupling efficiency between the AWG and the APDs even when the turning mirrors have a relatively small size.
- an apparatus comprising: a support structure having a planar surface; a first planar substrate located at an offset distance from the planar surface and having a first optical device, the first optical device having an array of first optical ports along an edge of the first planar substrate; a second planar substrate located at an offset distance from the planar surface and having one or more second optical devices with second optical ports along a second edge of the second planar substrate, the second edge facing the first edge; a first heater thermally coupled to the first planar substrate; and a second heater thermally coupled to the second planar substrate.
- the first planar substrate has a substantially different thermal expansivity than the second planar substrate.
- the first heater and the second heater are configured to be separately controllable.
- an apparatus having a support plate, a plurality of photo-detectors mounted on the support plate, a plurality of amplifiers mounted on the support plate and electrically connected to receive electrical signals generated by the photo-detectors in response to received light, and an optical subassembly mounted on the support plate.
- the photo-detectors are positioned between the optical sub-assembly and the support plate.
- the optical subassembly is configured to direct light to the photo-detectors.
- FIG. 1 shows a block diagram of an optical receiver 100 that can be used in an optical line card according to one embodiment of the invention.
- Receiver 100 has an optical-to-electrical (O/E) converter 110 and a signal processor 150.
- O/E converter 110 receives, e.g., from an external optical communications link, an N-component wavelength-division-multiplexed (WDM) signal 102 and transforms it into N electrical analog signals 142 1 -142 N so that each signal 142 represents a corresponding WDM component of signal 102, where N is an integer greater than one.
- WDM wavelength-division-multiplexed
- Processor 150 processes signals received on corresponding electrical lines 142 1 -142 N , as known in the art, to recover the data carried by the N individually modulated WDM components of signal 102 and outputs the recovered data via digital output signals 152 1 -152 N .
- the signal processing implemented in signal processor 150 includes analog-to-digital conversion and may optionally include one or more of clock recovery, electronic dispersion-compensation (EDC), and forward-error correction (FEC).
- EDC electronic dispersion-compensation
- FEC forward-error correction
- N 10, but, in other embodiments, can be as small or as large as needed for the particular application.
- O/E converter 110 is a hybrid integrated circuit that can be implemented, e.g., as further described below in reference to FIG. 2 .
- O/E converter 110 has an optical demultiplexer 120 that decomposes WDM signal 102 into its N constituent WDM components labeled ⁇ 1 - ⁇ N .
- Each WDM component ⁇ i is applied to a respective one of photo-detectors (PDs) 130 1 -130 N .
- PD 130 converts the received WDM component into a corresponding one of electrical signals on lines 132 1 -132 N .
- Each electrical signal 132 is then amplified in a corresponding one of amplifiers 140 1 -140 N to produce a corresponding one of electrical analog signals on electrical lines 142 1 - 142 N .
- optical demultiplexer 120 is a monolithic integrated optical circuit, and each of PDs 130 1 -130 N and amplifiers 140 1 -140 N is an individual semiconductor device. PDs 130 1 -130 N may be spatially arranged in any desired manner, e.g., in a linear lateral array, as indicated in FIG. 1 .
- Demultiplexer 120, PD devices 130 1 -130 N , and amplifier devices 140 1 -140 N are mounted on or over a planar surface of a (common) support plate 104, for example, made of a ceramic, composite, or polymeric material. Support plate 104 can be used to attach O/E converter 110, either directly or via additional structural elements, to a printed circuit board of the corresponding optical line card.
- FIG. 2 shows a partial side view of a cross-section of an opto-electronic assembly 200 that can be used in O/E converter 110 according to one embodiment of the invention.
- Opto-electronic assembly 200 has, e.g., a ceramic substrate (support plate) 204 that provides structural support for other components of the assembly.
- Substrate 204 can be one of possible implementations of support plate 104.
- Directly mounted on substrate 204 are a plurality of transimpedance amplifiers (TIAs) 240 1 - 240 N arranged in a linear lateral array. This linear lateral array arrangement causes only one of TIAs 240 1 -240 N , i.e., TIA 240 i , to be visible in the view of FIG.
- TIAs transimpedance amplifiers
- TIA 240 i is electrically connected to receive signals from an avalanche photodiode (APD) 230 i via a wire lead 238 i . Similar to TIA 240 i , APD 230 i is part of a plurality of APDs 230 1 -230 N arranged in a linear-lateral array, which causes only APD 230 i to be visible in FIG. 2 .
- APD avalanche photodiode
- APDs 230 1 -230 N are mounted on a submount 222 that is attached to substrate 204.
- Submount 222 serves at least two different functions and may comprise, e.g., a base layer 224, an isolation layer 226, and a conducting layer 228.
- a first function of submount 222 is to reduce optical losses by accommodating the height difference between APDs 230 1 -230 N and TIAs 240 1 -240 N .
- the term height refers to the thickness of the corresponding piece or component along the Z axis (as represented in FIG. 2 ).
- an APD such as APD 230 i
- TIA such as TIA 240 i
- APD 230 i were to be mounted directly on substrate 204, then a photosensitive area 234 of the APD would be located at a relatively large distance from an optical subassembly 290 (which projects light onto the photosensitive area) because TIA 240 i and wire lead 238 i would prevent the optical subassembly from being positioned any closer to the APD than the highest point of the TIA and/or the wire lead.
- this relatively large distance could cause a relatively high optical loss or could require the incorporation of one or more additional optical elements, such as a lens.
- Submount 222 can address this problem by enabling a significant reduction in the distance between photosensitive area 234 and optical subassembly 290. For that reason, in some embodiments, the optical loss can be kept to an acceptably low level without the incorporation of additional optical elements into assembly 200.
- a second function of submount 222 is to provide good control of height and tilt across the array of APDs 230 1 -230 N .
- substrate 204 is a ceramic carrier
- a relatively large (e.g., N>5) linear APD array may require the ceramic carrier to have a relatively large size and/or large aspect ratio, e.g., 1 cm x 1 mm. Large aspect ratios, such as this one, can reduce the fabrication yield due to the brittle nature of ceramics.
- this type of a mounting surface may cause unacceptable height and tilt variations among the APDs of the APD array.
- assembly 200 this problem can be addressed by using a non-ceramic material for submount 222, which can enable the surface of the submount to be sufficiently flat to meet relatively tight specifications with respect to the height uniformity and tilt in the positioning of APDs 230 1 -230 N .
- base layer 224 of submount 222 is made of silicon
- isolation layer 226 of the submount is made of silicon oxide or silicon nitride. Since the silicon-processing technology is mature and well developed, the flatness of external surfaces of submount 222 can often be well controlled, e.g., to within ⁇ 2 ⁇ m, so that the specifications with respect to the height uniformity and tilt in the positioning of APDs 230 1 -230 N are easily met.
- Isolation layer 226 serves as an electrically non-conducting spacer between APD 230 i and silicon base layer 224 and may be sufficiently thick to be able to inhibit the generation of radio-frequency (RF)-induced parasitic currents in the silicon base layer when the APD receives a modulated optical signal and generates a corresponding electrical RF signal for TIA 240 i .
- a typical thickness of isolation layer 226 is between about 10 ⁇ m and about 30 ⁇ m. Isolation layer 226 can also enable convenient deposition, patterning, and soldering of conducting layer 228 to provide appropriate electrical connections between APDs 230 and the corresponding wire leads 238.
- Optical subassembly 290 is mounted on substrate 204 using two spacers 236 positioned at the two (Y-axis) ends of the optical subassembly so as to form a ⁇ -shaped structure, with the spacers being the two legs of the ⁇ and the optical subassembly being the top horizontal bar of the ⁇ .
- the spacers being the two legs of the ⁇
- the optical subassembly being the top horizontal bar of the ⁇ .
- spacers 236 may be attached directly to substrate 204 or to submount 222.
- the height of spacers 236 and the thickness of submount 222 are selected so as to make the air gap between the lower surface of optical subassembly 290 and the upper surface of photosensitive area 234 as small as practically possible (to keep optical losses low) while providing sufficient clearance with appropriate tolerances for APDs 230 and wire leads 238.
- Optical subassembly 290 comprises an arrayed waveguide-grating device (AWGD) 220, a planar structure 260 having an array of mirrors 262 on a surface thereof, and a temperature-control unit 270.
- AWGD 220 serves as a WDM wavelength demultiplexer (also see demultiplexer 120 in FIG. 1 ) and is a monolithic planar integrated circuit having a substrate layer 214 and a waveguide layer 218.
- AWGD 220 is oriented so that optical waveguide layer 218 has a smaller offset distance with respect to substrate 204 than substrate layer 214.
- Optical waveguide layer 218 has the various optical waveguides that implement the optical-grating functionality of AWGD 220.
- An input WDM signal (such as optical signal 102, FIG. 1 ) is applied to an input waveguide (not explicitly shown in FIG. 2 ).
- AWGD 220 decomposes the input WDM signal into its N constituent WDM components and directs each WDM component into a respective one of N output waveguides 216 1 to 216 N in layer 218.
- WDM component ⁇ i is directed into output waveguide 216 i , as indicated in FIG. 2 .
- An edge 221 of AWGD 220 which has the termini of output waveguides 216 1 to 216 N , faces mirror array 260 so that each output waveguide is optically coupled to a corresponding one of N mirrors 262.
- Each mirror 262 serves as a turning mirror that redirects light coming out of output waveguides 216 along the X axis to propagate along the Z axis toward APDs 230.
- mirror 262 i which receives WDM component ⁇ i from output waveguide 216 i , redirects that WDM component toward photosensitive area 234 of APD 230 i , as indicated in FIG. 2 .
- mirror array 260 is a substantially rectangular piece of glass or silicon having one of its edges polished off to form a slanted surface that is oriented at a non-90-degree angle with respect to the two adjacent surfaces.
- the slanted surface may have a thin metal layer deposited over it to form a reflective surface of mirrors 262 1 to 262 N .
- the thickness of the glass piece and the width of the slanted surface are selected so that the cores of output waveguides 216 are aligned with a middle portion of the slanted surface.
- mirror array 260 may be slightly thicker than AWGD 220, which helps to accommodate the expansion of the optical beams in the free space between the termini of output waveguides 216 and the slanted surface of the mirror array.
- spacers 236 are attached to a surface 264 of mirror array 260 that faces substrate 204. Since surface 264 has a smaller offset distance from substrate 204 than the outer surface (i.e., the lower surface in the view shown in FIG. 2 ) of optical waveguide layer 218 in AWG 220, there is a small gap between spacer 236 and the optical waveguide layer.
- Other spacer configurations are also possible.
- mirror array 260 can be any suitable array of micromirrors, including possible implementations as a MEMS device.
- temperature-control unit 270 may serve as a structural base for optical subassembly 290 that enables appropriate positioning of AWGD 220 and mirror array 260 with respect to one another for flip-chip mounting over APDs 230 1 -230 N .
- temperature-control unit 270 controls the temperature(s) of AWGD 220 and mirror array 260.
- temperature-control unit 270 may incorporate one or more temperature sensors and one or more resistive heaters (not explicitly shown in FIG. 2 ) to maintain the temperature of AWGD 220 to within ⁇ 1 K of a specified temperature.
- spectral transmission characteristics of an AWGD such as AWGD 220, are relatively sensitive to temperature, and good temperature control can ensure that the AWGD has relatively low optical-insertion losses at the ITU wavelengths ⁇ i .
- temperature-control unit 270 delivers, using different resistive heaters, different respective rates of heat flow to AWGD 220 and mirror array 260, e.g., to avoid detrimental temperature gradients and/or to keep the AWG and mirror array at different respective temperatures.
- This feature can be used, e.g., to enable implementations in which AWGD 220 and mirror array 260 are made of different materials, thereby enabling the use of low-cost materials, e.g., for the mirror array, without the detriment of increased optical losses.
- possible optical misalignments induced by non-uniform heating induced by external heat sources can be mitigated or avoided.
- FIG. 3 shows a cross-sectional side view of an optical subassembly 390 that can be used as optical subassembly 290 according to one embodiment of the invention.
- Optical subassembly 390 comprises an AWGD 320, a planar structure 360 having an array of mirrors 362 on a surface thereof, and a temperature-control unit 370.
- Each mirror 362 has a relatively small vertical size, which is only slightly larger than the thickness of output waveguides 316 in AWGD 320. The small vertical size may be advantageous for enabling the middle portion of mirror 362 to be positioned (i) in relatively close proximity to the terminus of output waveguide 316 and/or (ii) in relatively close proximity to photosensitive area 234 (see FIG. 2 ).
- Planar structure 360 and AWGD 320 are implemented using different respective sets of materials.
- AWGD 320 may have a planar substrate 314 made of a first material (e.g., silicon), and planar structure 360 may have a planar substrate 364 made of a second material (e.g., glass) different from the first material.
- planar structure 360 and AWGD 320 have different thermal expansion coefficients.
- planar structure 360 is designed to have a thickness that places the middle portion of mirrors 362 in optical alignment with output waveguides 316 at the nominal operating temperature, a difference in the thermal expansion coefficients and a deviation of the actual operating temperature from the nominal operating temperature may cause mirrors 362 to go out of good optical alignment with output waveguides 316 in some instances of optical subassembly 390 if planar structure 360 has the same temperature as AWGD 320.
- temperature-control unit 370 has two independently controlled heaters 372 and 374.
- Heater 372 provides temperature control for AWGD 320 and is configured to keep the AWGD at the appropriate operating temperature, T 1 , selected so that the optical insertion losses in the AWGD are kept close to a minimum.
- temperature T 1 may differ from the nominal operating temperature.
- Heater 374 provides independent temperature control for planar structure 360 and is configured to keep the planar structure at temperature T 2 , which may differ from temperature T 1 . More specifically, temperature T 2 is selected so that, if necessary, the difference in the thermal expansion coefficients for AWGD 320 and planar structure 360 is properly compensated by the difference between temperatures T 1 and T 2 .
- mirrors 362 and output waveguides 316 are placed in good optical alignment with each other, thereby enabling optical subassembly 390 to have a relatively high optical throughput (or low optical losses) despite the deviation of temperature T 1 from the nominal operating temperature.
- different mirrors 362 of planar structure 360 are implemented as different (e.g., separate) optical devices integrated into planar structure 360, with planar structure 360 having a corresponding plurality of optical ports along its edge to enable optical coupling between the output ports of AWGD 320 (e.g., the termini of output waveguides 316 ) and the corresponding mirrors 362.
- the term "offset distance” refers to a minimum distance between two elements.
- the offset distance between substrate 204 and mirror array 260 is the distance between the upper surface of the substrate and the lower surface of the mirror array.
- the offset distance between substrate 204 and AWGD 220 is the distance between the upper surface of the substrate and the lower surface of the AWGD. Therefore, the offset distance between AWGD 220 and substrate 204 is greater than the offset distance between mirror array 260 and substrate 204.
- TIA 240 i has been described as being directly attached to substrate 204, an alternative embodiment that uses a submount inserted between the TIA and the substrate is also possible.
- TIAs 240 connected to different APDs 230 may be arranged in a staggered rather than linear configuration. More specifically, in the view shown in FIG.
- the staggered configuration means that TIA 240 i is located to the right of APD 230 i (as shown), whereas TIA 240 i +1 is located to the left of APD 230 i +1 , with this alternation being repeated across the TIA array.
- Planar substrate 314 may primarily be formed of a first semiconductor, and planar substrate 364 may primarily be formed of a second semiconductor, e.g., having a different alloy composition than the first semiconductor.
- a MEMS device is a device having two or more parts adapted to move relative to one another, where the motion is based on any suitable interaction or combination of interactions, such as mechanical, thermal, electrical, magnetic, optical, and/or chemical interactions.
- MEMS devices are fabricated using micro- or smaller fabrication techniques (including nano-fabrication techniques) that may include, but are not necessarily limited to: (1) self-assembly techniques employing, e.g., self-assembling monolayers, chemical coatings having high affinity to a desired chemical substance, and production and saturation of dangling chemical bonds and (2) wafer/material processing techniques employing, e.g., lithography, chemical vapor deposition, patterning and selective etching of materials, and treating, shaping, plating, and texturing of surfaces.
- MEMS devices include, without limitation, NEMS (nano-electromechanical systems) devices, MOEMS (micro-opto-electromechanical systems) devices, micromachines, microsystems, and devices produced using microsystems technology or microsystems integration.
- height does not imply only a vertical rise limitation, but is used to identify one of the three dimensions of a three-dimensional structure as shown in the figures.
- Such "height" would be vertical where the electrodes are horizontal but would be horizontal where the electrodes are vertical, and so on.
- all figures show the different layers as horizontal layers such orientation is for descriptive purposes only and not to be construed as a limitation.
- processors may be provided through the use of dedicated hardware as well as hardware capable of executing software in association with appropriate software.
- the functions may be provided by a single dedicated processor, by a single shared processor, or by a plurality of individual processors, some of which may be shared.
- explicit use of the term "processor” or “controller” should not be construed to refer exclusively to hardware capable of executing software, and may implicitly include, without limitation, digital signal processor (DSP) hardware, network processor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), read only memory (ROM) for storing software, random access memory (RAM), and non volatile storage.
- DSP digital signal processor
- ASIC application specific integrated circuit
- FPGA field programmable gate array
- ROM read only memory
- RAM random access memory
- any switches shown in the figures are conceptual only. Their function may be carried out through the operation of program logic, through dedicated logic, through the interaction of program control and dedicated logic, or even manually, the particular technique being selectable by the implementer as more specifically understood from the context.
- Couple refers to any manner known in the art or later developed in which energy is allowed to be transferred between two or more elements, and the interposition of one or more additional elements is contemplated, although not required. Conversely, the terms “directly coupled,” “directly connected,” etc., imply the absence of such additional elements.
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Optical Couplings Of Light Guides (AREA)
- Optical Integrated Circuits (AREA)
Description
- This application claims priority from
U.S. Provisional Patent Application No. 61/390,837 filed October 7, 2010 - U.S. patent application "OPTICAL ASSEMBLY FOR A WDM RECEIVER OR TRANSMITTER" by David Neilson, Nagesh Basavanhally, and Mark Earnshaw (Docket No. 807934-US-NP); U.S. patent application "DIRECT LASER i MODULATION" by Pietro Bernasconi and David Neilson (Docket No. 807932-US-NP); U.S. patent application "OPTICAL TRANSMITTER WITH FLIP-CHIP MOUNTED LASER OR INTEGRATED ARRAYED WAVEGUIDE GRATING WAVELENTH DIVISION MULTIPLEXER" by Mark Earnshaw and Flavio Pardo (Docket No. 807931-US-NP); U.S. patent application "THERMALLY CONTROLLED SEMICONDUCTOR OPTICAL WAVEGUIDE" by Mahmoud Rasras (Docket No. 808553-US-NP); and U.S. patent application "WAVELENGTH ALIGNING MULTI-CHANNEL OPTICAL TRANSMITTERS" by Douglas Gill (Docket No. 808555-US-NP), all filed on the same day as the present application. One or more of the above-cited applications may describe optical receiver structures, optical transmitter structures, methods of making optical receiver and/or optical transmitter structures and/or methods of using optical receiver and/or transmitter components that may be suitable for making and/or using embodiments described herein.
- The present invention relates to optical communication equipment and, more specifically but not exclusively, to line cards.
- This section introduces aspects that may help facilitate a better understanding of the invention(s). Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is in the prior art or what is not in the prior art.
- An optical line card is used for interfacing optical communication lines, e.g., carrying optical signals to and from the subscribers, to the rest of the telecommunications access network. A typical optical line card is a modular opto-electronic circuit assembled on a printed circuit board. Its representative modules may include an optical transmitter, an optical receiver, an optical add/drop multiplexer, a digital signal processor, a controller, a power-management unit, a performance monitor, various optical and electrical interfaces, etc.
- Different modules of an optical line card may be implemented using monolithic integration. A monolithic integrated circuit is usually fabricated on a single piece of semiconductor substrate, e.g., by (i) incorporating dopants into the substrate, (ii) depositing and patterning additional layers of material, and (iii) metallizing and packaging the resulting chip
-
US20060239605 discloses a stepped substrate with mounted optical components. -
US20050249509 discloses the use of heaters to control the temperature of a laser and a modulator to maintain wavelength control. - A hybrid integrated circuit is a multi-component circuit constructed of multiple monolithic integrated circuits. For example, one circuit may include semiconductor and optical devices, and the other circuit may include one or more passive components, with both monolithic circuits being arranged over the same mechanical sub-mount. In the prior art, neither monolithic nor hybrid integration has allowed straightforward production of both the passive optical elements and the electro-optical elements of an optical transmitter or receiver.
- Disclosed herein are various embodiments of an opto-electronic assembly that can be used in an optical receiver of a line card. In one embodiment, the opto-electronic assembly is a hybrid integrated circuit having an array of avalanche photodiodes (APDs) that are electrically coupled to a corresponding array of transimpedance amplifiers (TIAs), with both the APDs and TIAs being mounted on a common ceramic substrate. The opto-electronic assembly further has an optical subassembly comprising an arrayed waveguide grating (AWG) and an array of turning mirrors, both attached to a temperature-control unit in a side-by-side arrangement and flip-chip mounted on the substrate over the APDs. The opto-electronic assembly employs a silicon-based submount inserted between the APDs and the substrate to accommodate the height difference between the APDs and the TIAs. The submount advantageously enables the placement of APDs in relatively close proximity to the turning mirrors while providing good control of the APD's tilt and offset distance with respect to the substrate. The temperature-control unit enables independent temperature control of the AWG and of the array of turning mirrors, which helps to achieve good optical-coupling efficiency between the AWG and the APDs even when the turning mirrors have a relatively small size.
- According to another embodiment, provided is an apparatus comprising: a support structure having a planar surface; a first planar substrate located at an offset distance from the planar surface and having a first optical device, the first optical device having an array of first optical ports along an edge of the first planar substrate; a second planar substrate located at an offset distance from the planar surface and having one or more second optical devices with second optical ports along a second edge of the second planar substrate, the second edge facing the first edge; a first heater thermally coupled to the first planar substrate; and a second heater thermally coupled to the second planar substrate. The first planar substrate has a substantially different thermal expansivity than the second planar substrate. The first heater and the second heater are configured to be separately controllable.
- According to yet another embodiment, provided is an apparatus having a support plate, a plurality of photo-detectors mounted on the support plate, a plurality of amplifiers mounted on the support plate and electrically connected to receive electrical signals generated by the photo-detectors in response to received light, and an optical subassembly mounted on the support plate. The photo-detectors are positioned between the optical sub-assembly and the support plate. The optical subassembly is configured to direct light to the photo-detectors.
- Other aspects, features, and benefits of various embodiments of the invention will become more fully apparent, by way of example, from the following detailed description and the accompanying drawings, in which:
-
FIG. 1 shows a block diagram of an optical receiver according to one embodiment of the invention; -
FIG. 2 shows a partial cross-sectional side view of an opto-electronic assembly that can be used in the optical receiver ofFIG. 1 according to one embodiment of the invention; and -
FIG. 3 shows a cross-sectional side view of an optical subassembly that can be used in the opto-electronic assembly ofFIG. 2 according to one embodiment of the invention. -
FIG. 1 shows a block diagram of anoptical receiver 100 that can be used in an optical line card according to one embodiment of the invention.Receiver 100 has an optical-to-electrical (O/E)converter 110 and asignal processor 150. O/E converter 110 receives, e.g., from an external optical communications link, an N-component wavelength-division-multiplexed (WDM)signal 102 and transforms it into N electrical analog signals 1421-142N so that eachsignal 142 represents a corresponding WDM component ofsignal 102, where N is an integer greater than one.Processor 150 processes signals received on corresponding electrical lines 1421-142N, as known in the art, to recover the data carried by the N individually modulated WDM components ofsignal 102 and outputs the recovered data via digital output signals 1521-152N . The signal processing implemented insignal processor 150 includes analog-to-digital conversion and may optionally include one or more of clock recovery, electronic dispersion-compensation (EDC), and forward-error correction (FEC). In a representative embodiment, N=10, but, in other embodiments, can be as small or as large as needed for the particular application. - O/
E converter 110 is a hybrid integrated circuit that can be implemented, e.g., as further described below in reference toFIG. 2 . O/E converter 110 has anoptical demultiplexer 120 that decomposesWDM signal 102 into its N constituent WDM components labeled λ1-λN. Each WDM component λ i is applied to a respective one of photo-detectors (PDs) 1301-130N. EachPD 130 converts the received WDM component into a corresponding one of electrical signals on lines 1321-132N. Eachelectrical signal 132 is then amplified in a corresponding one of amplifiers 1401-140N to produce a corresponding one of electrical analog signals on electrical lines 1421 -142N. - In a representative embodiment,
optical demultiplexer 120 is a monolithic integrated optical circuit, and each of PDs 1301-130N and amplifiers 1401-140N is an individual semiconductor device. PDs 1301-130N may be spatially arranged in any desired manner, e.g., in a linear lateral array, as indicated inFIG. 1 . Demultiplexer 120, PD devices 1301-130N, and amplifier devices 1401-140N are mounted on or over a planar surface of a (common)support plate 104, for example, made of a ceramic, composite, or polymeric material.Support plate 104 can be used to attach O/E converter 110, either directly or via additional structural elements, to a printed circuit board of the corresponding optical line card. -
FIG. 2 shows a partial side view of a cross-section of an opto-electronic assembly 200 that can be used in O/E converter 110 according to one embodiment of the invention. Opto-electronic assembly 200 has, e.g., a ceramic substrate (support plate) 204 that provides structural support for other components of the assembly.Substrate 204 can be one of possible implementations ofsupport plate 104. Directly mounted onsubstrate 204 are a plurality of transimpedance amplifiers (TIAs) 2401 -240N arranged in a linear lateral array. This linear lateral array arrangement causes only one of TIAs 2401-240 N, i.e., TIA 240 i , to be visible in the view ofFIG. 2 . TIA 240 i is electrically connected to receive signals from an avalanche photodiode (APD) 230 i via awire lead 238 i . Similar to TIA 240 i , APD 230 i is part of a plurality of APDs 2301-230 N arranged in a linear-lateral array, which causes only APD 230 i to be visible inFIG. 2 . - APDs 2301-230 N are mounted on a
submount 222 that is attached tosubstrate 204. Submount 222 serves at least two different functions and may comprise, e.g., abase layer 224, anisolation layer 226, and a conductinglayer 228. - In some embodiments, a first function of
submount 222 is to reduce optical losses by accommodating the height difference between APDs 2301-230 N and TIAs 2401-240 N. Herein, the term height refers to the thickness of the corresponding piece or component along the Z axis (as represented inFIG. 2 ). Typically, an APD (such as APD 230 i ) has a smaller height than a TIA (such as TIA 240 i ). IfAPD 230 i were to be mounted directly onsubstrate 204, then aphotosensitive area 234 of the APD would be located at a relatively large distance from an optical subassembly 290 (which projects light onto the photosensitive area) becauseTIA 240 i andwire lead 238 i would prevent the optical subassembly from being positioned any closer to the APD than the highest point of the TIA and/or the wire lead. Disadvantageously, this relatively large distance could cause a relatively high optical loss or could require the incorporation of one or more additional optical elements, such as a lens.Submount 222 can address this problem by enabling a significant reduction in the distance betweenphotosensitive area 234 andoptical subassembly 290. For that reason, in some embodiments, the optical loss can be kept to an acceptably low level without the incorporation of additional optical elements intoassembly 200. - In some embodiments, a second function of
submount 222 is to provide good control of height and tilt across the array of APDs 2301-230 N. For example, ifsubstrate 204 is a ceramic carrier, a relatively large (e.g., N>5) linear APD array may require the ceramic carrier to have a relatively large size and/or large aspect ratio, e.g., 1 cm x 1 mm. Large aspect ratios, such as this one, can reduce the fabrication yield due to the brittle nature of ceramics. Also, the thermal treatment that ceramic materials undergo during fabrication often causes a relatively large shrinkage of the material so that the surface of the resulting ceramic carrier becomes somewhat "wavy." Disadvantageously, this type of a mounting surface may cause unacceptable height and tilt variations among the APDs of the APD array. Inassembly 200, this problem can be addressed by using a non-ceramic material forsubmount 222, which can enable the surface of the submount to be sufficiently flat to meet relatively tight specifications with respect to the height uniformity and tilt in the positioning of APDs 2301-230 N. - In one embodiment,
base layer 224 ofsubmount 222 is made of silicon, andisolation layer 226 of the submount is made of silicon oxide or silicon nitride. Since the silicon-processing technology is mature and well developed, the flatness of external surfaces ofsubmount 222 can often be well controlled, e.g., to within ±2 µm, so that the specifications with respect to the height uniformity and tilt in the positioning of APDs 2301-230 N are easily met.Isolation layer 226 serves as an electrically non-conducting spacer betweenAPD 230 i andsilicon base layer 224 and may be sufficiently thick to be able to inhibit the generation of radio-frequency (RF)-induced parasitic currents in the silicon base layer when the APD receives a modulated optical signal and generates a corresponding electrical RF signal forTIA 240 i . A typical thickness ofisolation layer 226 is between about 10 µm and about 30 µm.Isolation layer 226 can also enable convenient deposition, patterning, and soldering of conductinglayer 228 to provide appropriate electrical connections betweenAPDs 230 and the corresponding wire leads 238. -
Optical subassembly 290 is mounted onsubstrate 204 using twospacers 236 positioned at the two (Y-axis) ends of the optical subassembly so as to form a Π-shaped structure, with the spacers being the two legs of the Π and the optical subassembly being the top horizontal bar of the Π. In the view shown inFIG. 2 , only one of the twospacers 236 is visible, i.e., the spacer connected to the distal end ofoptical subassembly 290. In various embodiments,spacers 236 may be attached directly tosubstrate 204 or to submount 222. The height ofspacers 236 and the thickness ofsubmount 222 are selected so as to make the air gap between the lower surface ofoptical subassembly 290 and the upper surface ofphotosensitive area 234 as small as practically possible (to keep optical losses low) while providing sufficient clearance with appropriate tolerances forAPDs 230 and wire leads 238. -
Optical subassembly 290 comprises an arrayed waveguide-grating device (AWGD) 220, aplanar structure 260 having an array ofmirrors 262 on a surface thereof, and a temperature-control unit 270.AWGD 220 serves as a WDM wavelength demultiplexer (also see demultiplexer 120 inFIG. 1 ) and is a monolithic planar integrated circuit having asubstrate layer 214 and awaveguide layer 218.AWGD 220 is oriented so thatoptical waveguide layer 218 has a smaller offset distance with respect tosubstrate 204 thansubstrate layer 214.Optical waveguide layer 218 has the various optical waveguides that implement the optical-grating functionality ofAWGD 220. An input WDM signal (such asoptical signal 102,FIG. 1 ) is applied to an input waveguide (not explicitly shown inFIG. 2 ).AWGD 220 decomposes the input WDM signal into its N constituent WDM components and directs each WDM component into a respective one ofN output waveguides 2161 to 216 N inlayer 218. For example, WDM component λ i is directed intooutput waveguide 216 i , as indicated inFIG. 2 . - An
edge 221 ofAWGD 220, which has the termini ofoutput waveguides 2161 to 216 N , facesmirror array 260 so that each output waveguide is optically coupled to a corresponding one of N mirrors 262. Eachmirror 262 serves as a turning mirror that redirects light coming out ofoutput waveguides 216 along the X axis to propagate along the Z axis towardAPDs 230. For example,mirror 262 i , which receives WDM component λ i fromoutput waveguide 216 i , redirects that WDM component towardphotosensitive area 234 ofAPD 230 i , as indicated inFIG. 2 . - In one embodiment,
mirror array 260 is a substantially rectangular piece of glass or silicon having one of its edges polished off to form a slanted surface that is oriented at a non-90-degree angle with respect to the two adjacent surfaces. The slanted surface may have a thin metal layer deposited over it to form a reflective surface ofmirrors 2621 to 262 N . The thickness of the glass piece and the width of the slanted surface are selected so that the cores ofoutput waveguides 216 are aligned with a middle portion of the slanted surface. As a result,mirror array 260 may be slightly thicker thanAWGD 220, which helps to accommodate the expansion of the optical beams in the free space between the termini ofoutput waveguides 216 and the slanted surface of the mirror array. In one configuration,spacers 236 are attached to asurface 264 ofmirror array 260 that facessubstrate 204. Sincesurface 264 has a smaller offset distance fromsubstrate 204 than the outer surface (i.e., the lower surface in the view shown inFIG. 2 ) ofoptical waveguide layer 218 inAWG 220, there is a small gap betweenspacer 236 and the optical waveguide layer. Other spacer configurations are also possible. - In an alternative embodiment,
mirror array 260 can be any suitable array of micromirrors, including possible implementations as a MEMS device. - Both
mirror array 260 andAWGD 220 are attached to temperature-control unit 270, which can serve at least two functions. First, temperature-control unit 270 may serve as a structural base foroptical subassembly 290 that enables appropriate positioning ofAWGD 220 andmirror array 260 with respect to one another for flip-chip mounting over APDs 2301-230 N. Second, temperature-control unit 270 controls the temperature(s) ofAWGD 220 andmirror array 260. For example, temperature-control unit 270 may incorporate one or more temperature sensors and one or more resistive heaters (not explicitly shown inFIG. 2 ) to maintain the temperature ofAWGD 220 to within ±1 K of a specified temperature. As known in the art, spectral transmission characteristics of an AWGD, such asAWGD 220, are relatively sensitive to temperature, and good temperature control can ensure that the AWGD has relatively low optical-insertion losses at the ITU wavelengths λ i . - In one configuration, temperature-
control unit 270 delivers, using different resistive heaters, different respective rates of heat flow to AWGD 220 andmirror array 260, e.g., to avoid detrimental temperature gradients and/or to keep the AWG and mirror array at different respective temperatures. This feature can be used, e.g., to enable implementations in whichAWGD 220 andmirror array 260 are made of different materials, thereby enabling the use of low-cost materials, e.g., for the mirror array, without the detriment of increased optical losses. In addition, possible optical misalignments induced by non-uniform heating induced by external heat sources (such as electronic circuits located in relatively close proximity to optical subassembly 290) can be mitigated or avoided. -
FIG. 3 shows a cross-sectional side view of anoptical subassembly 390 that can be used asoptical subassembly 290 according to one embodiment of the invention.Optical subassembly 390 comprises anAWGD 320, aplanar structure 360 having an array ofmirrors 362 on a surface thereof, and a temperature-control unit 370. Eachmirror 362 has a relatively small vertical size, which is only slightly larger than the thickness ofoutput waveguides 316 inAWGD 320. The small vertical size may be advantageous for enabling the middle portion ofmirror 362 to be positioned (i) in relatively close proximity to the terminus ofoutput waveguide 316 and/or (ii) in relatively close proximity to photosensitive area 234 (seeFIG. 2 ).Planar structure 360 andAWGD 320 are implemented using different respective sets of materials. For example,AWGD 320 may have aplanar substrate 314 made of a first material (e.g., silicon), andplanar structure 360 may have aplanar substrate 364 made of a second material (e.g., glass) different from the first material. As a result,planar structure 360 and AWGD 320 have different thermal expansion coefficients. - In general, different instances of
AWGD 320 have different optimal operating temperatures due to process variations during fabrication. As a result, different instances ofoptical subassembly 390 may need to be configured to keep theirrespective AWGDs 320 at different respective operating temperatures. Whileplanar structure 360 is designed to have a thickness that places the middle portion ofmirrors 362 in optical alignment withoutput waveguides 316 at the nominal operating temperature, a difference in the thermal expansion coefficients and a deviation of the actual operating temperature from the nominal operating temperature may causemirrors 362 to go out of good optical alignment withoutput waveguides 316 in some instances ofoptical subassembly 390 ifplanar structure 360 has the same temperature asAWGD 320. - To address this problem, temperature-
control unit 370 has two independently controlledheaters Heater 372 provides temperature control forAWGD 320 and is configured to keep the AWGD at the appropriate operating temperature, T1, selected so that the optical insertion losses in the AWGD are kept close to a minimum. As already indicated above, temperature T1 may differ from the nominal operating temperature.Heater 374 provides independent temperature control forplanar structure 360 and is configured to keep the planar structure at temperature T2, which may differ from temperature T1. More specifically, temperature T2 is selected so that, if necessary, the difference in the thermal expansion coefficients forAWGD 320 andplanar structure 360 is properly compensated by the difference between temperatures T1 and T2. Due to this compensation, mirrors 362 andoutput waveguides 316 are placed in good optical alignment with each other, thereby enablingoptical subassembly 390 to have a relatively high optical throughput (or low optical losses) despite the deviation of temperature T1 from the nominal operating temperature. - In one embodiment,
different mirrors 362 ofplanar structure 360 are implemented as different (e.g., separate) optical devices integrated intoplanar structure 360, withplanar structure 360 having a corresponding plurality of optical ports along its edge to enable optical coupling between the output ports of AWGD 320 (e.g., the termini of output waveguides 316) and the corresponding mirrors 362. - As used herein, the term "offset distance" refers to a minimum distance between two elements. For example, in the view shown in
FIG. 2 , the offset distance betweensubstrate 204 andmirror array 260 is the distance between the upper surface of the substrate and the lower surface of the mirror array. Similarly, the offset distance betweensubstrate 204 andAWGD 220 is the distance between the upper surface of the substrate and the lower surface of the AWGD. Therefore, the offset distance betweenAWGD 220 andsubstrate 204 is greater than the offset distance betweenmirror array 260 andsubstrate 204. - While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. For example, although
TIA 240 i has been described as being directly attached tosubstrate 204, an alternative embodiment that uses a submount inserted between the TIA and the substrate is also possible.TIAs 240 connected todifferent APDs 230 may be arranged in a staggered rather than linear configuration. More specifically, in the view shown inFIG. 2 , the staggered configuration means thatTIA 240 i is located to the right of APD 230 i (as shown), whereasTIA 240 i+1 is located to the left ofAPD 230 i+1 , with this alternation being repeated across the TIA array.Planar substrate 314 may primarily be formed of a first semiconductor, andplanar substrate 364 may primarily be formed of a second semiconductor, e.g., having a different alloy composition than the first semiconductor. - Various modifications of the described embodiments, as well as other embodiments of the invention, which are apparent to persons skilled in the art to which the invention pertains are deemed to lie within the principle and scope of the invention as expressed in the following claims.
- For the purposes of this specification, a MEMS device is a device having two or more parts adapted to move relative to one another, where the motion is based on any suitable interaction or combination of interactions, such as mechanical, thermal, electrical, magnetic, optical, and/or chemical interactions. MEMS devices are fabricated using micro- or smaller fabrication techniques (including nano-fabrication techniques) that may include, but are not necessarily limited to: (1) self-assembly techniques employing, e.g., self-assembling monolayers, chemical coatings having high affinity to a desired chemical substance, and production and saturation of dangling chemical bonds and (2) wafer/material processing techniques employing, e.g., lithography, chemical vapor deposition, patterning and selective etching of materials, and treating, shaping, plating, and texturing of surfaces. Examples of MEMS devices include, without limitation, NEMS (nano-electromechanical systems) devices, MOEMS (micro-opto-electromechanical systems) devices, micromachines, microsystems, and devices produced using microsystems technology or microsystems integration.
- Unless explicitly stated otherwise, each numerical value and range should be interpreted as being approximate as if the word "about" or "approximately" preceded the value of the value or range.
- It will be further understood that various changes in the details, materials, and arrangements of the parts which have been described and illustrated in order to explain the nature of this invention may be made by those skilled in the art without departing from the scope of the invention as expressed in the following claims.
- Reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments necessarily mutually exclusive of other embodiments. The same applies to the term "implementation."
- The description and drawings merely illustrate the principles of the invention. It will thus be appreciated that those of ordinary skill in the art will be able to devise various arrangements that, although not explicitly described or shown herein, embody the principles of the invention and are included within its spirit and scope. Furthermore, all examples recited herein are principally intended expressly to be only for pedagogical purposes to aid the reader in understanding the principles of the invention and the concepts contributed by the inventor(s) to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass equivalents thereof.
- The use of terms such as height, length, width, top, bottom, is strictly to facilitate the description of the invention and is not intended to limit the invention to a specific orientation. For example, height does not imply only a vertical rise limitation, but is used to identify one of the three dimensions of a three-dimensional structure as shown in the figures. Such "height" would be vertical where the electrodes are horizontal but would be horizontal where the electrodes are vertical, and so on. Similarly, while all figures show the different layers as horizontal layers such orientation is for descriptive purposes only and not to be construed as a limitation.
- The functions of the various elements shown in the figures, including any functional blocks labeled as "processors," may be provided through the use of dedicated hardware as well as hardware capable of executing software in association with appropriate software. When provided by a processor, the functions may be provided by a single dedicated processor, by a single shared processor, or by a plurality of individual processors, some of which may be shared. Moreover, explicit use of the term "processor" or "controller" should not be construed to refer exclusively to hardware capable of executing software, and may implicitly include, without limitation, digital signal processor (DSP) hardware, network processor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), read only memory (ROM) for storing software, random access memory (RAM), and non volatile storage. Other hardware, conventional and/or custom, may also be included. Similarly, any switches shown in the figures are conceptual only. Their function may be carried out through the operation of program logic, through dedicated logic, through the interaction of program control and dedicated logic, or even manually, the particular technique being selectable by the implementer as more specifically understood from the context.
- Also for purposes of this description, the terms "couple," "coupling," "coupled," "connect," "connecting," or "connected" refer to any manner known in the art or later developed in which energy is allowed to be transferred between two or more elements, and the interposition of one or more additional elements is contemplated, although not required. Conversely, the terms "directly coupled," "directly connected," etc., imply the absence of such additional elements.
Claims (9)
- An apparatus, comprising:a support structure having a planar surface;a first planar substrate (314) located at an offset distance from the planar surface and having a first optical device, the first optical device having an array of first optical ports along an edge of the first planar substrate (314);a second planar substrate (364) located at an offset distance from the planar surface and having one or more second optical devices with second optical ports along a second edge of the second planar substrate (364), the second edge facing the first edge;a first heater thermally coupled to the first planar substrate (314); anda second heater thermally coupled to the second planar substrate (364), wherein:the first planar substrate (314) has a substantially different thermal expansivity than the second planar substrate (364); andthe first heater and the second heater are configured to be separately controllable.
- The apparatus of claim 1, wherein:the first planar substrate (314) includes a planar base, the optical device is located adjacent to the planar base, and the planar base has a different composition than a composition of the second planar substrate (364); andthe one or more second optical devices optically couple to devices located on the planar surface of the support structure.
- The apparatus of claim 1, further comprising:a plurality of photo-detectors (130) mounted on the planar surface;a plurality of amplifiers (140) mounted on the planar surface and electrically connected to receive electrical signals (132) generated by the photo-detectors (130) in response to received light, wherein the one or more second optical devices are configured to direct light from the array of first optical ports to the plurality of photo-detectors (130); anda submount (222) attached to the planar surface, wherein the photo-detectors (130) are mounted on the submount (222).
- The apparatus of claim 3, wherein the submount (222) comprises:a first layer (224) attached to the planar surface; anda second layer (226) formed over the first layer (224), wherein the photo-detectors (130) are directly attached to the second layer (226), wherein:the first layer (224) comprises silicon;the second layer (226) comprises silicon oxide or silicon nitride and has a thickness of at least 10 µm;the submount (222) further comprises a third layer (228) formed over the second layer (226) and made of an electrically conductive material; andthe third layer (228) is patterned to form electrical leads for transmitting the electrical signals (132) from the photo-detectors (130) to the amplifiers (140).
- The apparatus of claim 1, comprising:a plurality of photo-detectors (130) mounted on the support structure, wherein the support structure is a support plate;a plurality of amplifiers (140) mounted on the support structure and electrically connected to receive electrical signals (132) generated by the photo-detectors (130) in response to received light; andan optical subassembly mounted on the support structure, wherein:the photo-detectors (130) are positioned between the optical sub-assembly and the support structure; andthe optical subassembly is configured to direct light to the photo-detectors (130) , wherein the optical subassembly comprises:an optical demultiplexer (120) adapted to demultiplex an optical signal into a plurality of spectral components;one or more mirrors (262) configured to receive the spectral components from the optical demultiplexer (120) and direct said spectral components to the corresponding photo-detectors (130); anda temperature-control unit (270), wherein:the optical demultiplexer (120) and the one or more mirrors (262) are both attached to the temperature-control unit (270) in a side-by-side arrangement;the temperature-control unit (270) is positioned at a greater offset distance from the support plate than either of the optical demultiplexer (120) and the array of mirrors;the temperature-control unit (270) comprises two or more resistive heaters adapted to separately control the temperature of the optical demultiplexer (120) and the one or more mirrors (262); andthe optical demultiplexer (120) is positioned at a greater offset distance from the support structure than the one or more mirrors (262).
- An apparatus, comprising:a support plate;a plurality of photo-detectors (130) mounted on the support plate;a plurality of amplifiers (140) mounted on the support plate and electrically connected to receive electrical signals (132) generated by the photo-detectors (130) in response to received light; andthe apparatus of claim 1 as an optical subassembly mounted on the support plate, wherein:the photo-detectors (130) are positioned between the optical sub-assembly and the support plate; andthe optical subassembly is configured to direct light to the photo-detectors (130); and further comprising:a first spacer and a second spacer, both mounted on the support plate, wherein:a first end of the optical subassembly is attached to the first spacer;a second end of the optical subassembly is attached to the second spacer; anda middle portion of the optical subassembly is suspended between the first and second spacers; anda submount (222) attached to the support plate, wherein:the photo-detectors (130) are mounted on the submount (222); andthe first and second spacers are attached to the submount (222).
- The apparatus of claim 6, wherein:the photo-detectors (130) are mounted at a first offset distance from the support plate;the amplifiers (140) are mounted at a second offset distance from the support plate; andthe first offset distance is larger than the second offset distance.
- The apparatus of claim 6, wherein:
the submount (222) comprises:a first layer (224) directly attached to the support plate; anda second layer (226) formed over the first layer (224), wherein the photo-detectors (130) are directly attached to the second layer (226). - The apparatus of claim 8, wherein:the first layer (224) comprises silicon;the second layer (226) comprises silicon oxide or silicon nitride and has a thickness of at least 10 µm;the submount (222) further comprises a third layer (228) formed over the second layer (226) and made of an electrically conductive material;the third layer (228) is patterned to form electrical leads for transmitting the electrical signals (132) from the photo-detectors (130) to the amplifiers (140); anda surface of the submount (222) on which the photo-diodes are mounted is flat to within ±2 µm.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US39083710P | 2010-10-07 | 2010-10-07 | |
US12/944,875 US8787775B2 (en) | 2010-10-07 | 2010-11-12 | Opto-electronic assembly for a line card |
PCT/US2011/053812 WO2012047701A2 (en) | 2010-10-07 | 2011-09-29 | Opto-electronic assembly for a line card |
Publications (3)
Publication Number | Publication Date |
---|---|
EP2625558A2 EP2625558A2 (en) | 2013-08-14 |
EP2625558A4 EP2625558A4 (en) | 2017-11-22 |
EP2625558B1 true EP2625558B1 (en) | 2021-06-23 |
Family
ID=45928333
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP11831336.0A Active EP2625558B1 (en) | 2010-10-07 | 2011-09-29 | Opto-electronic assembly for a line card |
Country Status (6)
Country | Link |
---|---|
EP (1) | EP2625558B1 (en) |
JP (1) | JP5784130B2 (en) |
KR (1) | KR101515732B1 (en) |
CN (1) | CN103154798B (en) |
TW (1) | TW201229589A (en) |
WO (1) | WO2012047701A2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9893816B2 (en) * | 2016-03-25 | 2018-02-13 | Intel Corporation | Dynamic beam steering optoelectronic packages |
CN107843955B (en) * | 2017-09-20 | 2019-12-20 | 博创科技股份有限公司 | Heating type Array Waveguide Grating (AWG) module |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5212745A (en) * | 1991-12-02 | 1993-05-18 | Micron Optics, Inc. | Fixed and temperature tuned fiber fabry-perot filters |
DE69701175T2 (en) * | 1996-03-18 | 2000-09-14 | Koninkl Philips Electronics Nv | PLASMA-ADDRESSED COLOR DISPLAY DEVICE |
JP3448551B2 (en) * | 2000-06-14 | 2003-09-22 | 古河電気工業株式会社 | Array waveguide type diffraction grating |
US20020037025A1 (en) * | 2000-09-25 | 2002-03-28 | Bartman Randall K. | Hybrid narrow -linewidth semiconductor lasers |
JP3768099B2 (en) * | 2000-12-19 | 2006-04-19 | 三洋電機株式会社 | Light receiving element and optical semiconductor device including the same |
JP4665240B2 (en) * | 2001-06-25 | 2011-04-06 | 富士通株式会社 | Optical transmission equipment |
US7116851B2 (en) * | 2001-10-09 | 2006-10-03 | Infinera Corporation | Optical signal receiver, an associated photonic integrated circuit (RxPIC), and method improving performance |
KR100442609B1 (en) * | 2002-03-05 | 2004-08-02 | 삼성전자주식회사 | Structure of flip chip bonding and method for bonding |
US6842572B2 (en) * | 2002-05-15 | 2005-01-11 | Intel Corporation | Techniques to guide optical signals |
JP3947460B2 (en) * | 2002-12-03 | 2007-07-18 | ローム株式会社 | Optical module |
JP4336759B2 (en) * | 2002-12-17 | 2009-09-30 | 日本電気株式会社 | Light dispersion filter |
US7376310B2 (en) * | 2002-12-20 | 2008-05-20 | International Business Machines Corporation | Optical waveguide element with controlled birefringence |
US6945708B2 (en) * | 2003-02-18 | 2005-09-20 | Jds Uniphase Corporation | Planar lightwave circuit package |
JP2005064109A (en) * | 2003-08-08 | 2005-03-10 | Noritsu Koki Co Ltd | Laser beam source and laser exposure device |
JP2005167348A (en) | 2003-11-28 | 2005-06-23 | Matsushita Electric Ind Co Ltd | Optical receiver, optical transmitter/receiver and optical module |
WO2005106546A2 (en) * | 2004-04-15 | 2005-11-10 | Infinera Corporation | COOLERLESS AND FLOATING WAVELENGTH GRID PHOTONIC INTEGRATED CIRCUITS (PICs) FOR WDM TRANSMISSION NETWORKS |
CN101147088B (en) * | 2005-02-16 | 2011-08-17 | 应用材料股份有限公司 | Optical coupling to IC chip |
JP4830607B2 (en) * | 2006-02-09 | 2011-12-07 | パナソニック電工株式会社 | Photoelectric conversion device, manufacturing method thereof, and external waveguide |
US7532783B2 (en) * | 2006-10-11 | 2009-05-12 | Futurewei Technologies, Inc. | Method and system for integrated DWDM receivers |
JP2009092690A (en) * | 2007-10-03 | 2009-04-30 | Fuji Xerox Co Ltd | Optical module |
JP5052668B2 (en) * | 2008-03-18 | 2012-10-17 | 三菱電機株式会社 | Laser light source module |
KR101018278B1 (en) * | 2008-09-19 | 2011-03-04 | 전자부품연구원 | wavelength conversion device package |
-
2011
- 2011-09-29 EP EP11831336.0A patent/EP2625558B1/en active Active
- 2011-09-29 JP JP2013532839A patent/JP5784130B2/en not_active Expired - Fee Related
- 2011-09-29 WO PCT/US2011/053812 patent/WO2012047701A2/en active Application Filing
- 2011-09-29 CN CN201180048250.7A patent/CN103154798B/en active Active
- 2011-09-29 KR KR1020137008704A patent/KR101515732B1/en active IP Right Grant
- 2011-10-03 TW TW100135787A patent/TW201229589A/en unknown
Non-Patent Citations (1)
Title |
---|
None * |
Also Published As
Publication number | Publication date |
---|---|
TW201229589A (en) | 2012-07-16 |
KR20130052015A (en) | 2013-05-21 |
WO2012047701A3 (en) | 2012-08-16 |
KR101515732B1 (en) | 2015-04-27 |
JP5784130B2 (en) | 2015-09-24 |
CN103154798A (en) | 2013-06-12 |
EP2625558A2 (en) | 2013-08-14 |
EP2625558A4 (en) | 2017-11-22 |
WO2012047701A2 (en) | 2012-04-12 |
JP2013541047A (en) | 2013-11-07 |
CN103154798B (en) | 2015-12-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8787775B2 (en) | Opto-electronic assembly for a line card | |
EP1994653B1 (en) | Method and system for integrated dwdm transmitters | |
JP4790819B2 (en) | Method and system for a hybrid integrated 1xN DWDN transmitter | |
US8285150B2 (en) | Method and system for integrated DWDM transmitters | |
JP4060023B2 (en) | Optical waveguide transceiver module | |
JP2009522622A (en) | Method and system for integrated DWDM receiver | |
CN110888203B (en) | Photodiode array with integrated backside lens and multichannel transceiver module implementing the same | |
CN111221085B (en) | Optical isolator array for use in optical subassembly modules | |
EP2625558B1 (en) | Opto-electronic assembly for a line card | |
JP2009151041A (en) | Optical module and optical transmission/reception module | |
Gao et al. | Hybrid integration with efficient ball lens-based optical coupling for compact WDM transmitters | |
Tong | Multiwavelength receivers for WDM systems | |
CN111175911B (en) | Optical alignment of optical lenses, optical sub-assembly module for coupling lens clips, optical lenses, and optical sub-assembly module for implementing same | |
CN115016077A (en) | Optical module | |
EP3075082B1 (en) | Photodetectors aligning and coupling optical demultiplexer outputs | |
Bolle et al. | Compact Hybridly Integrated 10$\,\times\, $11.1-Gb/s DWDM Optical Receiver | |
Schumacher et al. | Monolithically integrated 20-channel optical add/drop multiplexer subsystem with hybrid-integrated 40-channel photo detector array | |
JP2022127580A (en) | optical module | |
KR101114573B1 (en) | Hybrid optical integration circuit assembly for optical receiving module and manufacturing method thereof | |
Mochizuki et al. | Four-channel integrated receiver with a built-in spatial demultiplexer optics for 100 Gb/s ethernet | |
Ohyama et al. | Hybrid integrated multiwavelength photoreceivers consisting of photo-diodes and an arrayed-waveguide grating | |
Lisicka et al. | Integration of arrayed wavelength division multiplex components into an optical add drop module transmitter and receiver |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 20130507 |
|
AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR |
|
111Z | Information provided on other rights and legal means of execution |
Free format text: AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR Effective date: 20130507 |
|
DAX | Request for extension of the european patent (deleted) | ||
RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: ALCATEL LUCENT |
|
D11X | Information provided on other rights and legal means of execution (deleted) | ||
A4 | Supplementary search report drawn up and despatched |
Effective date: 20171025 |
|
RIC1 | Information provided on ipc code assigned before grant |
Ipc: G02B 6/12 20060101ALI20171019BHEP Ipc: H04B 10/50 20130101ALI20171019BHEP Ipc: G02B 6/42 20060101AFI20171019BHEP |
|
RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: ALCATEL LUCENT |
|
GRAP | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOSNIGR1 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: GRANT OF PATENT IS INTENDED |
|
RIC1 | Information provided on ipc code assigned before grant |
Ipc: G02B 6/42 20060101AFI20200608BHEP Ipc: H04B 10/50 20130101ALI20200608BHEP Ipc: G02B 6/12 20060101ALI20200608BHEP Ipc: H01L 31/0203 20140101ALI20200608BHEP |
|
INTG | Intention to grant announced |
Effective date: 20200710 |
|
GRAJ | Information related to disapproval of communication of intention to grant by the applicant or resumption of examination proceedings by the epo deleted |
Free format text: ORIGINAL CODE: EPIDOSDIGR1 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE |
|
INTC | Intention to grant announced (deleted) | ||
GRAP | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOSNIGR1 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: GRANT OF PATENT IS INTENDED |
|
INTG | Intention to grant announced |
Effective date: 20210119 |
|
GRAS | Grant fee paid |
Free format text: ORIGINAL CODE: EPIDOSNIGR3 |
|
GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE PATENT HAS BEEN GRANTED |
|
AK | Designated contracting states |
Kind code of ref document: B1 Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: FG4D |
|
REG | Reference to a national code |
Ref country code: CH Ref legal event code: EP |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R096 Ref document number: 602011071237 Country of ref document: DE Ref country code: AT Ref legal event code: REF Ref document number: 1404789 Country of ref document: AT Kind code of ref document: T Effective date: 20210715 |
|
REG | Reference to a national code |
Ref country code: IE Ref legal event code: FG4D |
|
REG | Reference to a national code |
Ref country code: LT Ref legal event code: MG9D |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: HR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210623 Ref country code: BG Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210923 Ref country code: FI Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210623 Ref country code: LT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210623 |
|
REG | Reference to a national code |
Ref country code: AT Ref legal event code: MK05 Ref document number: 1404789 Country of ref document: AT Kind code of ref document: T Effective date: 20210623 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: NO Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210923 Ref country code: LV Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210623 Ref country code: GR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210924 Ref country code: RS Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210623 Ref country code: SE Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210623 |
|
REG | Reference to a national code |
Ref country code: NL Ref legal event code: MP Effective date: 20210623 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: SM Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210623 Ref country code: SK Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210623 Ref country code: EE Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210623 Ref country code: CZ Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210623 Ref country code: RO Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210623 Ref country code: NL Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210623 Ref country code: PT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20211025 Ref country code: ES Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210623 Ref country code: AT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210623 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: PL Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210623 |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R097 Ref document number: 602011071237 Country of ref document: DE |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: DK Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210623 |
|
PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
REG | Reference to a national code |
Ref country code: CH Ref legal event code: PL |
|
REG | Reference to a national code |
Ref country code: BE Ref legal event code: MM Effective date: 20210930 |
|
26N | No opposition filed |
Effective date: 20220324 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: MC Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210623 Ref country code: AL Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210623 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: LU Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20210929 Ref country code: IT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210623 Ref country code: IE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20210929 Ref country code: FR Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20210930 Ref country code: BE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20210930 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: LI Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20210930 Ref country code: CH Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20210930 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: HU Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT; INVALID AB INITIO Effective date: 20110929 Ref country code: CY Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210623 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: GB Payment date: 20230810 Year of fee payment: 13 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: DE Payment date: 20230802 Year of fee payment: 13 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: MK Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210623 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: TR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210623 |