EP2528100A1 - Circuit board, display device, and process for production of circuit board - Google Patents

Circuit board, display device, and process for production of circuit board Download PDF

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Publication number
EP2528100A1
EP2528100A1 EP10843931A EP10843931A EP2528100A1 EP 2528100 A1 EP2528100 A1 EP 2528100A1 EP 10843931 A EP10843931 A EP 10843931A EP 10843931 A EP10843931 A EP 10843931A EP 2528100 A1 EP2528100 A1 EP 2528100A1
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EP
European Patent Office
Prior art keywords
circuit board
layer
wirings
semiconductor layer
aluminum
Prior art date
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Application number
EP10843931A
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German (de)
French (fr)
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EP2528100A4 (en
EP2528100B1 (en
Inventor
Yoshihito Hara
Yukinobu Nakata
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Sharp Corp
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Sharp Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02551—Group 12/16 materials
    • H01L21/02554—Oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the present invention relates to a circuit board, a display device, and a process for producing a circuit board. More specifically, the present invention relates to a circuit board used as a component of an electronic device such as a display device; a display device; and a process for producing a circuit board.
  • a circuit board has an electronic circuit as its component, and a circuit board including elements such as thin-film transistors (TFTs), for example, is widely used as a component of an electronic device such as a liquid crystal display device, an organic electroluminescent display device, and a solar battery.
  • TFTs thin-film transistors
  • a TFT array substrate has a pixel circuit that has a structure in which TFTs (switching elements) are disposed at intersections of m x n matrix wirings with m rows of scanning lines and n columns of signal lines.
  • the drain wirings of the TFTs are connected to picture element electrodes.
  • peripheral circuits such as a scanning driver IC and a data driver IC are respectively connected to the gate wirings and source wirings of the TFTs.
  • low-resistance aluminum wirings are often used.
  • a circuit is affected by the performance of TFTs formed on a TFT substrate. That is, the performance of TFTs formed on a TFT substrate varies according to the material of the TFTs, and thus the circuit formed on the TFT substrate affects whether the circuit can be driven by the TFTs formed on the circuit board, whether the circuit size is not large, whether the yield does not decrease, and the like.
  • a-Si amorphous silicon
  • a-Si has low electron mobility. For this reason, a material better in electronic properties has been desired.
  • Patent Document 1 discloses a thin-film transistor that has an oxide semiconductor containing one element selected from In, Ga, and Zn as its channel layer.
  • Patent Literature 1 JP 2008-277326 A
  • a semiconductor layer is not resistant to wet etching whereas a-Si is resistant to wet etching, in the case of employing an oxide semiconductor as a semiconductor layer for an increase in the electron mobility.
  • the oxide semiconductor is removed by the etching solution for aluminum which is used in a mask process (e.g., a five-sheet mask process with a channel etching process) in production of a circuit board including low-resistance aluminum wirings. Accordingly, such a circuit board can be further improved in terms of increasing reliability.
  • the five-sheet mask process includes the steps of, for example, (1) performing etching using a first mask to form gate wirings; (2) performing etching using a second mask to form a semiconductor layer; (3) performing etching using a third mask to form a conductor layer, and then separating the layer into source electrodes and drain electrodes (this step is also referred to as a "channel etching process” or a “channel separation process” herein); (4) performing etching using a fourth mask to form an insulating film layer and an organic insulating film, and then forming contact holes; and (5) performing etching using a fifth mask to form picture element electrodes.
  • the present invention has been made in view of the above state of the art, and aims to provide a reliable circuit board that includes TFTs a semiconductor layer of which is formed from an oxide semiconductor; and low-resistance aluminum wirings.
  • the present inventors have made various studies on highly reliable circuit boards, and have focused on the phenomenon that, in a circuit board in which a semiconductor layer is formed from an oxide semiconductor, the oxide semiconductor in the TFT portions, terminal portions and so on of the circuit board is lost because of the etching solution for aluminum wirings.
  • the loss of the oxide semiconductor has been found to lead to insufficient reliability of the circuit board.
  • the present inventors have found that the loss of the oxide semiconductor because of the etching solution in production of a circuit board can be prevented and the reliability can be increased, in the case that the wirings are formed by stacking a layer formed from a metal other than aluminum and a layer containing aluminum in the TFT portions of the circuit board, and that each of the source wirings and the drain wirings includes a portion in contact with the semiconductor layer, portions of the source wirings in contact with the semiconductor layer and respective portions of the drain wirings in contact with the semiconductor layer spacedly facing each other.
  • the findings have solved the above problem admirably, and thereby the present invention has been completed.
  • the present invention is a circuit board including: an oxide semiconductor layer; source wirings; and drain wirings, wherein each of the source wirings and the drain wirings includes a portion in contact with the semiconductor layer, portions of the source wirings in contact with the semiconductor layer and respective portions of the drain wirings in contact with the semiconductor layer spacedly facing each other, and the source wirings and the drain wirings are formed by stacking a layer formed from a metal other than aluminum and a layer containing aluminum.
  • the circuit board of the present invention having the above structure is produced through a channel etching process of etching the layer containing aluminum and then etching the layer formed from a metal other than aluminum.
  • dry etching can be employed in place of the wet etching for aluminum.
  • Use of dry etching enables to minimize the loss of the oxide semiconductor. Therefore, the reliability can be sufficiently increased regarding a circuit board that includes TFTs the semiconductor layer of which is formed from an oxide semiconductor; and low-resistance aluminum wirings.
  • the layer containing aluminum is preferably formed from aluminum, an aluminum alloy, Mo/Al, or a Mo/Al alloy, for example.
  • the Al alloy is an alloy the main component of which is Al-Ni, Al-Nd, Al-Co, or Al-Si, for example.
  • the thickness of the layer is, for example, 50 nm to 400 nm.
  • the layer formed from a metal other than aluminum is preferably one that is resistant to an etchant for the layer containing aluminum and can go through dry etching.
  • metals such as Ti, Ta, and W are preferred.
  • the thickness of the layer is preferably 10 nm to 100 nm so that the dry etching time is shortened to reduce damage to the base.
  • oxide semiconductor layer examples include crystalline oxide semiconductor layers such as ZnO layers, and amorphous oxide semiconductor layers such as IGZO (indium gallium zinc oxide) layers. Among these, amorphous oxide semiconductor layers are preferred. These amorphous oxide semiconductor layers are lost by a mixed solution (used in general etching for Al) of phosphoric acid + nitric acid + acetic acid.
  • crystalline oxide semiconductor layers such as ZnO layers
  • amorphous oxide semiconductor layers such as IGZO (indium gallium zinc oxide) layers.
  • IGZO indium gallium zinc oxide
  • circuit board of the present invention essentially includes these components, the structure of the circuit board of the present invention is not particularly limited by other components. Preferred structures of the circuit board of the present invention are described in detail below.
  • a preferred structure of the circuit board of the present invention is a structure in which the layer formed from a metal other than aluminum includes at least one selected from the group consisting of titanium, tantalum, and tungsten. This structure enables easy dry etching, which enables to achieve the effects of the present invention sufficiently.
  • a more preferred structure is a structure in which the layer formed from a metal other than aluminum consists of at least one selected from the group consisting of titanium, tantalum, and tungsten.
  • circuit board of the present invention is a structure in which the circuit board is a thin-film transistor array substrate.
  • the thin-film transistor array substrate has thin-film transistors (TFTs) on the circuit board.
  • Another aspect of the present invention is a display device including the circuit board of the present invention.
  • the display device include liquid crystal display devices and EL display devices such as organic EL display devices and inorganic EL display devices.
  • Yet another aspect of the present invention is a process for producing a circuit board that includes an oxide semiconductor layer, source wirings, and drain wirings, the process including: an oxide semiconductor formation step of forming an oxide semiconductor layer; a conductor layer formation step of forming a conductor layer by stacking a layer formed from a metal other than aluminum and a layer containing aluminum; and a treatment step of treating the layer containing aluminum by wet etching, and then treating the layer formed from a metal other than aluminum by dry etching, wherein the treatment step includes separating the conductor layer into source wirings and drain wirings such that portions of the source wirings in contact with the semiconductor layer and respective portions of the drain wirings in contact with the semiconductor layer spacedly face each other.
  • the process for producing the circuit board of the present invention employs dry etching in place of wet etching in the later part of the etching in the channel etching process, and the use of dry etching minimizes the loss of the exposed oxide semiconductor. Therefore, the reliability can be sufficiently increased regarding a circuit board that includes TFTs the semiconductor layer of which is formed from an oxide semiconductor; and low-resistance aluminum wirings.
  • the conductor layer formation step is enough if the step includes formation of a conductor layer as a pre-step of the treatment step of separating the conductor layer into source wirings and drain wirings through etching.
  • a preferred structure of the process for producing the circuit board of the present invention is the same as the above preferred structure of the circuit board of the present invention.
  • the present invention enables to sufficiently increase the reliability regarding a circuit board that includes TFTs the semiconductor layer of which is produced from an oxide semiconductor; and low-resistance aluminum wirings.
  • portions of the source wirings in contact with the semiconductor layer and respective portions of the drain wirings in contact with the semiconductor layer spacedly facing each other is satisfied as long as a surface of each source wiring in a portion in contact with the semiconductor layer and a surface of a drain wiring in a portion in contact with the semiconductor layer are disposed in parallel with each other without direct contact as shown in Fig. 2 , for example.
  • the circuit board is a substrate on which TFTs are formed in the embodiment, the circuit board is also referred to as a TFT-side substrate.
  • a substrate facing the circuit board is a substrate on which color filters (CFs) are formed in the embodiment, the substrate facing the circuit board is also referred to as a CF-side substrate.
  • FIG. 1 is a schematic plan view illustrating the circuit board of the first embodiment.
  • a circuit board 100 is a TFT-side substrate provided with thin-film transistors (TFTs) 41, and has a picture element electrode area (display area) and an area outside the picture element electrode area (non-display area).
  • TFTs thin-film transistors
  • non-display area connecting portions 51 and terminal portions 61 are arranged.
  • a source driver can be mounted on the circuit board 100 by, for example, a chip-on-glass (COG) method.
  • COG chip-on-glass
  • a flexible printed circuit board (FPC) can be mounted on the circuit board 100.
  • signals for driving the source driver can be input from the FPC via the terminal portions 61 and the connecting portions 51.
  • Fig. 2 is a schematic cross-sectional view illustrating a TFT portion in the circuit board of the first embodiment.
  • the circuit board of the first embodiment has, in each TFT portion, a gate wiring 13, an oxide semiconductor layer 17 such as an IGZO (indium gallium zinc oxide) layer, and a source wiring 19s and a drain wiring 19d formed by stacking a layer formed from a metal other than aluminum and a layer containing aluminum.
  • Each of the source wirings 19s and the drain wirings 19d has a portion in contact with the oxide semiconductor layer 17, and portions of the source wirings 19s in contact with the oxide semiconductor layer 17 and respective portions of the drain wirings 19d in contact with the oxide semiconductor layer 17 spacedly face each other.
  • a channel etching process is performed in which etching of the layer containing aluminum is performed first and then etching of the layer formed from a metal other than aluminum is performed.
  • dry etching can be employed in place of the wet etching, and dry etching enables to minimize the loss of the oxide semiconductor. Therefore, the reliability can be sufficiently increased regarding a circuit board that includes TFTs the semiconductor layer of which is formed from an oxide semiconductor; and low-resistance aluminum wirings.
  • Any solution can be used for wet etching as long as it enables etching of aluminum.
  • a solution enabling etching of aluminum usually results in a loss of the oxide semiconductor, and thus application of the present invention to a circuit board produced using such a solution is expected to achieve advantageous effects of the present invention.
  • the solution include strong acid, weak acid, and strong alkali. Since the oxide semiconductor layer 17 is etched even with weak alkali in the case that the oxide semiconductor layer 17 is of ZnO or the like metal other than IGZO, the present invention can also be applied to a circuit board obtained using a weak alkali in this case.
  • a mixed solution used in general etching of aluminum
  • phosphoric acid + nitric acid + acetic acid is preferred.
  • Suitable examples of the oxide semiconductor layer 17 other than an IGZO layer include ISZO (In-Si-Zn-O), IAZO (In-Al-Zn-O), INiZO (In-Ni-Zn-O), ICuZO (In-Cu-Zn-O), IHfZO (In-Hf-Zn-O), and IZO (In-Zn-O) layers.
  • Fig. 3 is a schematic cross-sectional view illustrating a substrate on which gate wirings are formed in the process for producing the circuit board of the first embodiment. From the left side of the drawing, the respective portions indicate a TFT portion, a storage capacitance (Cs) portion, the connecting portion 51, and the terminal portion 61 in the circuit board. The same applies in Figs. 4 to 9 and Figs. 12 to 16 . In each of the TFT portion, the connecting portion, and the terminal portion, a gate wiring 13 is formed.
  • Fig. 4 is a schematic cross-sectional view illustrating the substrate on which a semiconductor layer is further formed in the process for producing the circuit board of the first embodiment.
  • An insulating layer 15 has been further formed on the substrate illustrated in Fig. 3 , and an oxide semiconductor layer 17 has been formed in each of the TFT portion and the terminal portion.
  • Fig. 5 is a schematic cross-sectional view illustrating the substrate after wet etching of a layer containing aluminum in the process for producing the circuit board of the first embodiment. That is, a conductor layer is further formed on the substrate illustrated in Fig. 4 by stacking a layer 19a formed from a metal other than aluminum and a layer 19b containing aluminum. On the conductor layer, a resist 20 has been formed through a mask process, so that wet etching can be performed on the layer 19b containing aluminum.
  • Fig. 6 is a schematic cross-sectional view illustrating the substrate after dry etching of the layer formed from a metal other than aluminum in the process for producing the circuit board of the first embodiment.
  • the layer 19a formed from a metal other than aluminum has been further subjected to dry etching.
  • the oxide semiconductor layer 17 has only received the minimum damage by dry etching, and is not lost substantially.
  • the conductor layer (source wirings and drain wirings) illustrated in the present embodiment may include two layers or three or more layers, but preferably includes two layers or three layers.
  • the layer preferably has a multi-layer structure of Al (aluminum)/Ti (titanium), Mo (molybdenum)/Al (aluminum)/Ti (titanium), Al alloy/Mo (molybdenum)/Ti, Al alloy/Ti, Al alloy/Ta (tantalum), or Al alloy/W (tungsten).
  • the thickness of the layer containing aluminum can be 50 nm to 400 nm.
  • the thickness of the layer formed from a metal other than aluminum can be 10 nm to 100 nm.
  • the upper layer aluminum is processed through a wet etching process, and then Ti, Ta, W, or the like is processed through a dry process.
  • Fig. 7 is a schematic cross-sectional view illustrating the substrate after removal of a resist in the process for producing the circuit board of the first embodiment. The resist has been removed from the substrate illustrated in Fig. 6 .
  • Fig. 8 is a schematic cross-sectional view illustrating the substrate on which an organic insulating film is further formed in the process for producing the circuit board of the first embodiment.
  • An insulating layer 21 has been further formed on the substrate illustrated in Fig. 7 , and then an organic insulating film 23 has been formed on the insulating layer 21. After that, contact holes have been formed by dry etching in the storage capacitance (Cs) portion, the connecting portion, and the terminal portion.
  • Cs storage capacitance
  • Fig. 9 is a schematic cross-sectional view illustrating the substrate on which picture element electrodes are further formed in the process for producing the circuit board of the first embodiment.
  • Picture electrodes 31 have been further formed on the circuit board illustrated in Fig. 8 .
  • wirings including a low-resistance aluminum (alloy) layer can be suitably produced through the five-sheet mask process.
  • Fig. 10 is an exploded perspective view schematically illustrating the structure of a liquid crystal panel that includes the circuit board of the first embodiment. As illustrated in Fig.
  • liquid crystals 73 are sandwiched by a CF-side substrate 72 and the circuit board 100 in a liquid crystal panel 200.
  • the liquid crystal panel 200 also has a backlight 75 on the backside of the circuit board 100.
  • the light of the backlight 75 passes through a polarizer 74, the circuit board 100, the liquid crystals 73, the CF-side substrate 72, and a polarizer 71 in the stated order, and transmission and non-transmission of light is controlled by alignment control of the liquid crystals.
  • Fig. 11 is an exploded perspective view schematically illustrating the structure of a liquid crystal display device that includes the liquid crystal panel illustrated in Fig. 10 . As illustrated in Fig.
  • the liquid crystal panel 200 fixed on a fixation panel 400 is sealed by a front cabinet 300 and a back cabinet 500.
  • the back cabinet 500 and an upper stand 700 are fixed to each other via a metal fitting 600.
  • the upper stand 700 and a lower stand 800 are fitted with each other.

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  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
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  • Chemical & Material Sciences (AREA)
  • Thin Film Transistor (AREA)
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Abstract

The present invention provides a highly reliable circuit board that includes TFTs a semiconductor layer of which is formed from an oxide semiconductor; and low-resistance aluminum wirings. The circuit board of the present invention includes an oxide semiconductor layer; source wirings; and drain wirings, wherein each of the source wirings and the drain wirings includes a portion in contact with the semiconductor layer, portions of the source wirings in contact with the semiconductor layer and respective portions of the drain wirings in contact with the semiconductor layer spacedly facing each other, and the source wirings and the drain wirings are formed by stacking a layer formed from a metal other than aluminum and a layer containing aluminum.

Description

    TECHNICAL FIELD
  • The present invention relates to a circuit board, a display device, and a process for producing a circuit board. More specifically, the present invention relates to a circuit board used as a component of an electronic device such as a display device; a display device; and a process for producing a circuit board.
    • BACKGROUND ART
  • A circuit board has an electronic circuit as its component, and a circuit board including elements such as thin-film transistors (TFTs), for example, is widely used as a component of an electronic device such as a liquid crystal display device, an organic electroluminescent display device, and a solar battery.
  • Hereinafter, a circuit board is illustrated based on an example of a circuit configuration of a TFT array substrate constituting a TFT-driven liquid crystal display panel. A TFT array substrate has a pixel circuit that has a structure in which TFTs (switching elements) are disposed at intersections of m x n matrix wirings with m rows of scanning lines and n columns of signal lines. The drain wirings of the TFTs are connected to picture element electrodes. Also, peripheral circuits such as a scanning driver IC and a data driver IC are respectively connected to the gate wirings and source wirings of the TFTs. For the wirings, low-resistance aluminum wirings are often used.
  • A circuit is affected by the performance of TFTs formed on a TFT substrate. That is, the performance of TFTs formed on a TFT substrate varies according to the material of the TFTs, and thus the circuit formed on the TFT substrate affects whether the circuit can be driven by the TFTs formed on the circuit board, whether the circuit size is not large, whether the yield does not decrease, and the like. Although a-Si (amorphous silicon) is used in many cases for conventional circuit boards in that TFTs can be easily formed at low cost, a-Si has low electron mobility. For this reason, a material better in electronic properties has been desired.
  • Regarding other semiconductor compounds usable for a channel layer of a TFT, Patent Document 1, for example, discloses a thin-film transistor that has an oxide semiconductor containing one element selected from In, Ga, and Zn as its channel layer.
    • CITATION LIST Patent Literature
  • Patent Literature 1: JP 2008-277326 A
    • SUMMARY OF INVENTION Technical Problem
  • However, a semiconductor layer is not resistant to wet etching whereas a-Si is resistant to wet etching, in the case of employing an oxide semiconductor as a semiconductor layer for an increase in the electron mobility. Hence, at least a part of the oxide semiconductor is removed by the etching solution for aluminum which is used in a mask process (e.g., a five-sheet mask process with a channel etching process) in production of a circuit board including low-resistance aluminum wirings. Accordingly, such a circuit board can be further improved in terms of increasing reliability. Here, the five-sheet mask process includes the steps of, for example, (1) performing etching using a first mask to form gate wirings; (2) performing etching using a second mask to form a semiconductor layer; (3) performing etching using a third mask to form a conductor layer, and then separating the layer into source electrodes and drain electrodes (this step is also referred to as a "channel etching process" or a "channel separation process" herein); (4) performing etching using a fourth mask to form an insulating film layer and an organic insulating film, and then forming contact holes; and (5) performing etching using a fifth mask to form picture element electrodes.
    • Fig. 12 is a schematic cross-sectional view illustrating a substrate on which gate wirings are formed in a process for producing a conventional circuit board. From the left side of the drawing, the respective portions indicate a TFT portion, a storage capacitance (Cs) portion, a connecting portion, and a terminal portion in the circuit board. In each portion, a gate wiring 113 is formed.
    • Fig. 13 is a schematic cross-sectional view illustrating the substrate on which a semiconductor layer is further formed in the process for producing a conventional circuit board. An insulating layer 115 has been further formed on the substrate illustrated in Fig. 12, and an oxide semiconductor layer 117 has been formed in each of the TFT portion and the terminal portion.
    • Fig. 14 is a schematic cross-sectional view illustrating the substrate after wet etching of a layer containing aluminum in the process for producing a conventional circuit board. A layer 119 containing aluminum has been further formed on the substrate illustrated in Fig. 13, and the layer 119 containing aluminum has been then wet-etched by the mask process. In the portions from which the layer 119 containing aluminum has been removed by wet etching, parts of the oxide semiconductor layer 117 have been lost and the layer has become thinner.
    • Fig. 15 is a schematic cross-sectional view illustrating the substrate on which an organic insulating film is further formed in the process for producing a conventional circuit board. An insulating layer 121 has been further formed on the substrate illustrated in Fig. 14, and then an organic insulating film 123 has been formed on the insulating layer 121. After that, contact holes have been formed by dry etching in the storage capacitance (Cs) portion, the connecting portion, and the terminal portion.
    • Fig. 16 is a schematic cross-sectional view illustrating a substrate on which picture element electrodes are further formed in the process for producing a conventional circuit board. Picture electrodes 131 have been further formed on the circuit board illustrated in Fig. 15.
    As described above, at least a part or all of the oxide semiconductor layer 117 is lost because of the wet etching of the layer 119 containing aluminum in the conventional circuit board. For this reason, conventional circuit boards can be further improved in terms of sufficiently increasing the reliability.
  • The present invention has been made in view of the above state of the art, and aims to provide a reliable circuit board that includes TFTs a semiconductor layer of which is formed from an oxide semiconductor; and low-resistance aluminum wirings.
    • Solution to Problem
  • The present inventors have made various studies on highly reliable circuit boards, and have focused on the phenomenon that, in a circuit board in which a semiconductor layer is formed from an oxide semiconductor, the oxide semiconductor in the TFT portions, terminal portions and so on of the circuit board is lost because of the etching solution for aluminum wirings. The loss of the oxide semiconductor has been found to lead to insufficient reliability of the circuit board. Also, the present inventors have found that the loss of the oxide semiconductor because of the etching solution in production of a circuit board can be prevented and the reliability can be increased, in the case that the wirings are formed by stacking a layer formed from a metal other than aluminum and a layer containing aluminum in the TFT portions of the circuit board, and that each of the source wirings and the drain wirings includes a portion in contact with the semiconductor layer, portions of the source wirings in contact with the semiconductor layer and respective portions of the drain wirings in contact with the semiconductor layer spacedly facing each other. The findings have solved the above problem admirably, and thereby the present invention has been completed.
  • That is, the present invention is a circuit board including: an oxide semiconductor layer; source wirings; and drain wirings, wherein each of the source wirings and the drain wirings includes a portion in contact with the semiconductor layer, portions of the source wirings in contact with the semiconductor layer and respective portions of the drain wirings in contact with the semiconductor layer spacedly facing each other, and the source wirings and the drain wirings are formed by stacking a layer formed from a metal other than aluminum and a layer containing aluminum.
  • The circuit board of the present invention having the above structure is produced through a channel etching process of etching the layer containing aluminum and then etching the layer formed from a metal other than aluminum. In the later part of the etching, dry etching can be employed in place of the wet etching for aluminum. Use of dry etching enables to minimize the loss of the oxide semiconductor. Therefore, the reliability can be sufficiently increased regarding a circuit board that includes TFTs the semiconductor layer of which is formed from an oxide semiconductor; and low-resistance aluminum wirings.
  • The layer containing aluminum is preferably formed from aluminum, an aluminum alloy, Mo/Al, or a Mo/Al alloy, for example. The Al alloy is an alloy the main component of which is Al-Ni, Al-Nd, Al-Co, or Al-Si, for example. The thickness of the layer is, for example, 50 nm to 400 nm.
  • The layer formed from a metal other than aluminum is preferably one that is resistant to an etchant for the layer containing aluminum and can go through dry etching. For example, metals such as Ti, Ta, and W are preferred. The thickness of the layer is preferably 10 nm to 100 nm so that the dry etching time is shortened to reduce damage to the base.
  • Examples of the oxide semiconductor layer include crystalline oxide semiconductor layers such as ZnO layers, and amorphous oxide semiconductor layers such as IGZO (indium gallium zinc oxide) layers. Among these, amorphous oxide semiconductor layers are preferred. These amorphous oxide semiconductor layers are lost by a mixed solution (used in general etching for Al) of phosphoric acid + nitric acid + acetic acid.
  • As long as the circuit board of the present invention essentially includes these components, the structure of the circuit board of the present invention is not particularly limited by other components.
    Preferred structures of the circuit board of the present invention are described in detail below.
  • A preferred structure of the circuit board of the present invention is a structure in which the layer formed from a metal other than aluminum includes at least one selected from the group consisting of titanium, tantalum, and tungsten. This structure enables easy dry etching, which enables to achieve the effects of the present invention sufficiently. A more preferred structure is a structure in which the layer formed from a metal other than aluminum consists of at least one selected from the group consisting of titanium, tantalum, and tungsten.
  • Another preferred structure of the circuit board of the present invention is a structure in which the circuit board is a thin-film transistor array substrate. The thin-film transistor array substrate has thin-film transistors (TFTs) on the circuit board.
  • Another aspect of the present invention is a display device including the circuit board of the present invention. Examples of the display device include liquid crystal display devices and EL display devices such as organic EL display devices and inorganic EL display devices.
  • Yet another aspect of the present invention is a process for producing a circuit board that includes an oxide semiconductor layer, source wirings, and drain wirings, the process including: an oxide semiconductor formation step of forming an oxide semiconductor layer; a conductor layer formation step of forming a conductor layer by stacking a layer formed from a metal other than aluminum and a layer containing aluminum; and a treatment step of treating the layer containing aluminum by wet etching, and then treating the layer formed from a metal other than aluminum by dry etching, wherein the treatment step includes separating the conductor layer into source wirings and drain wirings such that portions of the source wirings in contact with the semiconductor layer and respective portions of the drain wirings in contact with the semiconductor layer spacedly face each other.
  • The process for producing the circuit board of the present invention employs dry etching in place of wet etching in the later part of the etching in the channel etching process, and the use of dry etching minimizes the loss of the exposed oxide semiconductor. Therefore, the reliability can be sufficiently increased regarding a circuit board that includes TFTs the semiconductor layer of which is formed from an oxide semiconductor; and low-resistance aluminum wirings.
  • The conductor layer formation step is enough if the step includes formation of a conductor layer as a pre-step of the treatment step of separating the conductor layer into source wirings and drain wirings through etching.
  • A preferred structure of the process for producing the circuit board of the present invention is the same as the above preferred structure of the circuit board of the present invention.
  • The above structures may be appropriately combined as long as the combination does not go beyond the scope of the present invention.
    • Advantageous Effects of Invention
  • The present invention enables to sufficiently increase the reliability regarding a circuit board that includes TFTs the semiconductor layer of which is produced from an oxide semiconductor; and low-resistance aluminum wirings.
    • BRIEF DESCRIPTION OF DRAWINGS
    • Fig. 1 is a schematic plan view illustrating a circuit board of a first embodiment.
    • Fig. 2 is a schematic cross-sectional view illustrating a TFT portion in the circuit board of the first embodiment.
    • Fig. 3 is a schematic cross-sectional view illustrating a substrate on which gate wirings have been formed in a process for producing the circuit board of the first embodiment.
    • Fig. 4 is a schematic cross-sectional view illustrating the substrate on which a semiconductor layer is further formed in the process for producing the circuit board of the first embodiment.
    • Fig. 5 is a schematic cross-sectional view illustrating the substrate after wet etching of a layer containing aluminum in the process for producing the circuit board of the first embodiment.
    • Fig. 6 is a schematic cross-sectional view illustrating the substrate after dry etching of a layer formed from a metal other than aluminum in the process for producing the circuit board of the first embodiment.
    • Fig. 7 is a schematic cross-sectional view illustrating the substrate after removal of a resist in the process for producing the circuit board of the first embodiment.
    • Fig. 8 is a schematic cross-sectional view illustrating the substrate on which an organic insulating film is further formed in the process for producing the circuit board of the first embodiment.
    • Fig. 9 is a schematic cross-sectional view illustrating the substrate on which picture elements are formed in the process for producing the circuit board of the first embodiment.
    • Fig. 10 is an exploded perspective view schematically illustrating the structure of a liquid crystal panel that includes the circuit board of the first embodiment.
    • Fig. 11 is an exploded perspective view schematically illustrating the structure of a liquid crystal display device that includes the liquid crystal panel illustrated in Fig. 10.
    • Fig. 12 is a schematic cross-sectional view illustrating a substrate on which gate wirings are formed in a process for producing a conventional circuit board.
    • Fig. 13 is a schematic cross-sectional view illustrating the substrate on which a semiconductor layer is further formed in the process for forming a conventional circuit board.
    • Fig. 14 is a schematic cross-sectional view illustrating the substrate after wet etching of a layer containing aluminum in the process for forming a conventional circuit board.
    • Fig. 15 is a schematic cross-sectional view illustrating the substrate on which an organic insulating film is further formed in the process for producing a conventional circuit board.
    • Fig. 16 is a schematic cross-sectional view illustrating the substrate on which picture elements are further formed in the process for producing a conventional circuit board.
    DESCRIPTION OF EMBODIMENTS
  • The condition of "portions of the source wirings in contact with the semiconductor layer and respective portions of the drain wirings in contact with the semiconductor layer spacedly facing each other" mentioned herein is satisfied as long as a surface of each source wiring in a portion in contact with the semiconductor layer and a surface of a drain wiring in a portion in contact with the semiconductor layer are disposed in parallel with each other without direct contact as shown in Fig. 2, for example.
    Since the circuit board is a substrate on which TFTs are formed in the embodiment, the circuit board is also referred to as a TFT-side substrate. Since a substrate facing the circuit board is a substrate on which color filters (CFs) are formed in the embodiment, the substrate facing the circuit board is also referred to as a CF-side substrate.
  • The present invention will be described in more detail below with reference to the drawings based on an embodiment which, however, is not intended to limit the scope of the present invention.
    • First embodiment
  • Fig. 1 is a schematic plan view illustrating the circuit board of the first embodiment. A circuit board 100 is a TFT-side substrate provided with thin-film transistors (TFTs) 41, and has a picture element electrode area (display area) and an area outside the picture element electrode area (non-display area).
    In the non-display area, connecting portions 51 and terminal portions 61 are arranged. Via the connecting portions 51, a source driver can be mounted on the circuit board 100 by, for example, a chip-on-glass (COG) method. Via the terminal portions 61, a flexible printed circuit board (FPC) can be mounted on the circuit board 100. For example, signals for driving the source driver can be input from the FPC via the terminal portions 61 and the connecting portions 51.
    In the display area of the circuit board 100, gate wirings 13 and source wirings 19s substantially perpendicular to each other are provided on a glass substrate (not illustrated in Fig. 1), and a picture element electrode 31 and a TFT 41 are provided in each area surrounded by the gate wirings 13 and the source wirings 19s. Also, storage capacitance (Cs) wirings 25 are provided so as to overlap with picture element electrode 31 in such a manner that they are substantially parallel with the gate wirings 13.
    Fig. 2 is a schematic cross-sectional view illustrating a TFT portion in the circuit board of the first embodiment. The circuit board of the first embodiment has, in each TFT portion, a gate wiring 13, an oxide semiconductor layer 17 such as an IGZO (indium gallium zinc oxide) layer, and a source wiring 19s and a drain wiring 19d formed by stacking a layer formed from a metal other than aluminum and a layer containing aluminum. Each of the source wirings 19s and the drain wirings 19d has a portion in contact with the oxide semiconductor layer 17, and portions of the source wirings 19s in contact with the oxide semiconductor layer 17 and respective portions of the drain wirings 19d in contact with the oxide semiconductor layer 17 spacedly face each other. In the circuit board of the present embodiment having the above structure, a channel etching process is performed in which etching of the layer containing aluminum is performed first and then etching of the layer formed from a metal other than aluminum is performed. In the later part of the etching, dry etching can be employed in place of the wet etching, and dry etching enables to minimize the loss of the oxide semiconductor. Therefore, the reliability can be sufficiently increased regarding a circuit board that includes TFTs the semiconductor layer of which is formed from an oxide semiconductor; and low-resistance aluminum wirings.
  • Any solution can be used for wet etching as long as it enables etching of aluminum. A solution enabling etching of aluminum usually results in a loss of the oxide semiconductor, and thus application of the present invention to a circuit board produced using such a solution is expected to achieve advantageous effects of the present invention. Examples of the solution include strong acid, weak acid, and strong alkali. Since the oxide semiconductor layer 17 is etched even with weak alkali in the case that the oxide semiconductor layer 17 is of ZnO or the like metal other than IGZO, the present invention can also be applied to a circuit board obtained using a weak alkali in this case. Among these solutions, a mixed solution (used in general etching of aluminum) of phosphoric acid + nitric acid + acetic acid is preferred.
  • Suitable examples of the oxide semiconductor layer 17 other than an IGZO layer include ISZO (In-Si-Zn-O), IAZO (In-Al-Zn-O), INiZO (In-Ni-Zn-O), ICuZO (In-Cu-Zn-O), IHfZO (In-Hf-Zn-O), and IZO (In-Zn-O) layers.
  • The steps of producing the circuit board of the first embodiment are described below with reference to Figs. 3 to 9.
    Fig. 3 is a schematic cross-sectional view illustrating a substrate on which gate wirings are formed in the process for producing the circuit board of the first embodiment. From the left side of the drawing, the respective portions indicate a TFT portion, a storage capacitance (Cs) portion, the connecting portion 51, and the terminal portion 61 in the circuit board. The same applies in Figs. 4 to 9 and Figs. 12 to 16. In each of the TFT portion, the connecting portion, and the terminal portion, a gate wiring 13 is formed.
  • Fig. 4 is a schematic cross-sectional view illustrating the substrate on which a semiconductor layer is further formed in the process for producing the circuit board of the first embodiment. An insulating layer 15 has been further formed on the substrate illustrated in Fig. 3, and an oxide semiconductor layer 17 has been formed in each of the TFT portion and the terminal portion.
  • Fig. 5 is a schematic cross-sectional view illustrating the substrate after wet etching of a layer containing aluminum in the process for producing the circuit board of the first embodiment. That is, a conductor layer is further formed on the substrate illustrated in Fig. 4 by stacking a layer 19a formed from a metal other than aluminum and a layer 19b containing aluminum. On the conductor layer, a resist 20 has been formed through a mask process, so that wet etching can be performed on the layer 19b containing aluminum.
  • Fig. 6 is a schematic cross-sectional view illustrating the substrate after dry etching of the layer formed from a metal other than aluminum in the process for producing the circuit board of the first embodiment. In a portion from which the layer 19b containing aluminum has been removed (in other words, a portion with no resist 20 formed), the layer 19a formed from a metal other than aluminum has been further subjected to dry etching. The oxide semiconductor layer 17 has only received the minimum damage by dry etching, and is not lost substantially.
    The conductor layer (source wirings and drain wirings) illustrated in the present embodiment may include two layers or three or more layers, but preferably includes two layers or three layers. For example, the layer preferably has a multi-layer structure of Al (aluminum)/Ti (titanium), Mo (molybdenum)/Al (aluminum)/Ti (titanium), Al alloy/Mo (molybdenum)/Ti, Al alloy/Ti, Al alloy/Ta (tantalum), or Al alloy/W (tungsten). The thickness of the layer containing aluminum can be 50 nm to 400 nm. Also, the thickness of the layer formed from a metal other than aluminum can be 10 nm to 100 nm. As mentioned above, the upper layer aluminum is processed through a wet etching process, and then Ti, Ta, W, or the like is processed through a dry process.
  • Fig. 7 is a schematic cross-sectional view illustrating the substrate after removal of a resist in the process for producing the circuit board of the first embodiment. The resist has been removed from the substrate illustrated in Fig. 6.
  • Fig. 8 is a schematic cross-sectional view illustrating the substrate on which an organic insulating film is further formed in the process for producing the circuit board of the first embodiment. An insulating layer 21 has been further formed on the substrate illustrated in Fig. 7, and then an organic insulating film 23 has been formed on the insulating layer 21. After that, contact holes have been formed by dry etching in the storage capacitance (Cs) portion, the connecting portion, and the terminal portion.
  • Fig. 9 is a schematic cross-sectional view illustrating the substrate on which picture element electrodes are further formed in the process for producing the circuit board of the first embodiment. Picture electrodes 31 have been further formed on the circuit board illustrated in Fig. 8.
    Thereby, wirings including a low-resistance aluminum (alloy) layer can be suitably produced through the five-sheet mask process. That is, a loss of the oxide semiconductor in a TFT portion of a circuit board because of the etching solution in production of a circuit board can be prevented to increase the reliability, in the case that the wirings are formed by stacking a layer formed from a metal other than aluminum and a layer containing aluminum, and that each of the source wirings and the drain wirings includes a portion in contact with the semiconductor layer, and portions of the source wirings in contact with the semiconductor layer and respective portions of the drain wirings in contact with the semiconductor layer spacedly face each other.
    Fig. 10 is an exploded perspective view schematically illustrating the structure of a liquid crystal panel that includes the circuit board of the first embodiment.
    As illustrated in Fig. 10, liquid crystals 73 are sandwiched by a CF-side substrate 72 and the circuit board 100 in a liquid crystal panel 200. The liquid crystal panel 200 also has a backlight 75 on the backside of the circuit board 100. The light of the backlight 75 passes through a polarizer 74, the circuit board 100, the liquid crystals 73, the CF-side substrate 72, and a polarizer 71 in the stated order, and transmission and non-transmission of light is controlled by alignment control of the liquid crystals.
    Fig. 11 is an exploded perspective view schematically illustrating the structure of a liquid crystal display device that includes the liquid crystal panel illustrated in Fig. 10. As illustrated in Fig. 11, the liquid crystal panel 200 fixed on a fixation panel 400 is sealed by a front cabinet 300 and a back cabinet 500. The back cabinet 500 and an upper stand 700 are fixed to each other via a metal fitting 600. The upper stand 700 and a lower stand 800 are fitted with each other.
  • The structures in the above embodiment may be appropriately combined as long as the combination does not go beyond the scope of the present invention.
  • The present application claims priority to Patent Application No. 2010-011368 filed in Japan on January 21, 2010 under the Paris Convention and provisions of national law in a designated State, the entire contents of which are hereby incorporated by reference.
    • EXPLANATION OF SYMBOLS
    • 11: Glass Substrate
    • 13, 113: Gate wiring
    • 15, 21, 115, 121: Insulating layer
    • 17, 117: Oxide semiconductor layer
    • 19s: Source wiring
    • 19d: Drain wiring
    • 19a: Layer formed from metal other than aluminum
    • 19b, 119: Layer containing aluminum
    • 20: Resist
    • 23, 123: Organic insulating film
    • 25: Cs (storage capacitance) wiring
    • 31,131: Picture element electrode
    • 41: TFT
    • 51: Connecting portion
    • 61: Terminal portion
    • 71, 74: Polarizer
    • 72: CF-side substrate
    • 73: Liquid crystal
    • 75: Backlight
    • 100: Circuit board
    • 200: Liquid crystal panel
    • 300: Front cabinet
    • 400: Fixation panel
    • 500: Back cabinet
    • 600: Metal fitting
    • 700: Upper stand
    • 800: Lower stand
    • 900: Liquid crystal display device

Claims (5)

  1. A circuit board comprising:
    an oxide semiconductor layer;
    source wirings; and
    drain wirings,
    wherein each of the source wirings and the drain wirings includes a portion in contact with the semiconductor layer, portions of the source wirings in contact with the semiconductor layer and respective portions of the drain wirings in contact with the semiconductor layer spacedly facing each other, and
    the source wirings and the drain wirings are formed by stacking a layer formed from a metal other than aluminum and a layer containing aluminum.
  2. The circuit board according to claim 1,
    wherein the layer formed from a metal other than aluminum contains at least one selected from the group consisting of titanium, tantalum, and tungsten.
  3. The circuit board according to claim 1 or 2,
    wherein the circuit board is a thin-film transistor array substrate.
  4. A display device comprising the circuit board according to any one of claims 1 to 3.
  5. A process for producing a circuit board that includes an oxide semiconductor layer, source wirings, and drain wirings,
    the process comprising:
    an oxide semiconductor formation step of forming an oxide semiconductor layer;
    a conductor layer formation step of forming a conductor layer by stacking a layer formed from a metal other than aluminum and a layer containing aluminum; and
    a treatment step of treating the layer containing aluminum by wet etching, and then treating the layer formed from a metal other than aluminum by dry etching,
    wherein the treatment step includes separating the conductor layer into source wirings and drain wirings such that portions of the source wirings in contact with the semiconductor layer and respective portions of the drain wirings in contact with the semiconductor layer spacedly face each other.
EP10843931.6A 2010-01-21 2010-10-25 Process for production of circuit board Not-in-force EP2528100B1 (en)

Applications Claiming Priority (2)

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PCT/JP2010/068803 WO2011089767A1 (en) 2010-01-21 2010-10-25 Circuit board, display device, and process for production of circuit board

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Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20120099475A (en) 2009-12-04 2012-09-10 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor device and manufacturing method thereof
US8664097B2 (en) * 2010-09-13 2014-03-04 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor device
JP6076038B2 (en) * 2011-11-11 2017-02-08 株式会社半導体エネルギー研究所 Method for manufacturing display device
KR20240105514A (en) 2012-12-25 2024-07-05 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor device
US9905585B2 (en) 2012-12-25 2018-02-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device comprising capacitor
KR102241249B1 (en) 2012-12-25 2021-04-15 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Resistor, display device, and electronic device
US9915848B2 (en) 2013-04-19 2018-03-13 Semiconductor Energy Laboratory Co., Ltd. Display device and electronic device
US9704894B2 (en) 2013-05-10 2017-07-11 Semiconductor Energy Laboratory Co., Ltd. Display device including pixel electrode including oxide
TWI649606B (en) 2013-06-05 2019-02-01 日商半導體能源研究所股份有限公司 Display device and electronic device
CN105339999B (en) * 2013-06-27 2017-12-01 夏普株式会社 Liquid crystal display device
US9293480B2 (en) 2013-07-10 2016-03-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and display device including the semiconductor device
WO2016063169A1 (en) 2014-10-23 2016-04-28 Semiconductor Energy Laboratory Co., Ltd. Light-emitting element
US10680017B2 (en) 2014-11-07 2020-06-09 Semiconductor Energy Laboratory Co., Ltd. Light-emitting element including EL layer, electrode which has high reflectance and a high work function, display device, electronic device, and lighting device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070241327A1 (en) * 2006-04-18 2007-10-18 Samsung Electronics Co. Ltd. Fabrication methods of a ZnO thin film structure and a ZnO thin film transistor, and a ZnO thin film structure and a ZnO thin film transistor
US20090239335A1 (en) * 2005-09-29 2009-09-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor Device and Manufacturing Method Thereof

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3365954B2 (en) * 1997-04-14 2003-01-14 株式会社神戸製鋼所 Al-Ni-Y alloy thin film for semiconductor electrode and sputtering target for forming Al-Ni-Y alloy thin film for semiconductor electrode
JP5064747B2 (en) 2005-09-29 2012-10-31 株式会社半導体エネルギー研究所 Semiconductor device, electrophoretic display device, display module, electronic device, and method for manufacturing semiconductor device
JP5305630B2 (en) * 2006-12-05 2013-10-02 キヤノン株式会社 Manufacturing method of bottom gate type thin film transistor and manufacturing method of display device
JP2008277326A (en) 2007-04-25 2008-11-13 Canon Inc Amorphous oxide semiconductor, semiconductor device and thin-film transistor
US8300167B2 (en) * 2007-06-14 2012-10-30 Sharp Kabushiki Kaisha Display panel, display device, and method for manufacturing display panel
WO2010061778A1 (en) * 2008-11-28 2010-06-03 シャープ株式会社 Substrate for display device, and display device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090239335A1 (en) * 2005-09-29 2009-09-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor Device and Manufacturing Method Thereof
US20070241327A1 (en) * 2006-04-18 2007-10-18 Samsung Electronics Co. Ltd. Fabrication methods of a ZnO thin film structure and a ZnO thin film transistor, and a ZnO thin film structure and a ZnO thin film transistor

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2011089767A1 *

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JP5559210B2 (en) 2014-07-23
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CN102714221A (en) 2012-10-03
JPWO2011089767A1 (en) 2013-05-20

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