Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/38—Information transfer, e.g. on bus
  • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
  • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F2213/38—Universal adapter
  • G06F2213/3814—Wireless link with a computer system port

Definitions

• the present invention relates to near-field data communication techniques, or Near Field Communication (NFC) techniques.
• NFC Near Field Communication
• NFC communication techniques formerly known as "RFID” or “Radio Frequency Identification” use inductive coupling between two closely spaced antenna coils to transfer data between two components.
• An NFC communication generally involves an active component and a passive component.
• the active component emits a magnetic field by means of its antenna coil and modulates the magnetic field.
• the passive component generally modulates the impedance of its antenna circuit.
• Such an impedance modulation called “charge modulation” or
• “retromodulation” affects the antenna circuit of the active component by inductive coupling, which can extract the data sent to it by appropriate filtering and decoding operations.
• Passive NFC components are generally so-called “non-contact” integrated circuits because they can exchange data by inductive coupling.
• Contactless integrated circuits are usually mounted in or on portable objects to form, for example, contactless cards (application to payment), contactless badges.
• card emulation where they emulate the operation of an integrated circuit without passive contact. This passive mode of operation allows them to communicate with an NFC reader in the active mode, by sending data by charge modulation in the presence of the magnetic field emitted by the reader operating in the active mode.
• NFC new generations of mobile phones
• An NFC reader embedded in a mobile phone makes it possible, when in the active mode, to use the telephone to read contactless integrated circuits (contactless business cards, electronic tags, etc.), and when is in the passive mode (card emulation mode) to use the phone as a means of payment or identification without contact.
• NFC technology in various devices or devices for everyday use is envisaged in the medium term, as a means of data transmission in its own right as today's Bluetooth ® technology, and not only to conduct identification procedures.
• the advantage of NFC technology over Bluetooth technology is that the passive NFC component can operate without any power source because its supply voltage can be extracted from the magnetic field emitted by the active NFC component.
• an NFC phone with the empty battery remains usable as a means of payment or identification.
• NFC function integrated in a device having electronic and / or computer resources
• a mobile phone can be used to exchange data with the device equipped with the NFC function, for example to program it, configure it, set it to day or save data.
• the NFC readers generally include a Universal Asynchronous Receiver Transmitter (UART) type universal port, which makes it possible to connect them to a host device or terminal device.
• FIGS. 1 and 2 illustrate a conventional application configuration in which a terminal device DV1 is equipped with an NFC reader RDI and is connected thereto via its UART port, which allows the device DV1 to benefit from NFC technology.
• the device DV1 uses the reader RDI to read or write data in a contactless integrated circuit ICC1, the reader RDI emitting a magnetic field FLD.
• the device DV1 uses the reader RDI to exchange data with a terminal device DV2 which is itself equipped with a reader RD2.
• the reader RD2 is for example in the active mode and emits the magnetic field FLD necessary for the communication, while the reader RDI is in the passive mode.
• NFC readers with UART communication ports are complex circuits with a microprocessor strong enough to handle contactless communication, UART communication port management, data buffer management to store data received via the channel contactless communication and return them to the communication port, management of various communication protocols etc.
• such readers are equipped with oscillators and AC voltage generation circuits to be applied to their antenna circuit to produce a magnetic field.
• the non-contact integrated circuit comprises an antenna circuit Lc-Ca, a transmission / reception circuit CLER connected to the antenna circuit Lc-Ca, a processing unit ML1 with wired logic (logical sequencer ) coupled to the transmit / receive circuit, a clock circuit CKCT for providing a clock signal and a memory array MEM.
• the antenna circuit comprises an antenna coil Lc and at least one tuning capacitor Ca.
• the transmission / reception circuit CLER performs the extraction, the demodulation and the decoding of incoming data DTr as well as the coding of data. outgoing DTx and providing a corresponding charge modulation signal. It is generally found that the cost price of an NFC reader is approximately 10 to 20 times greater than that of a non-contact non-microprocessor integrated circuit of the type shown in FIG.
• Embodiments of the invention are based on the idea that an integrated circuit without passive contact, that is to say without magnetic field emission means, may be sufficient to implement a NFC communication between two terminal devices, since one of the two devices, for example an NFC mobile phone, has an NFC reader function.
• one of the two devices for example an NFC mobile phone
• has an NFC reader function for example, in the application shown in Fig. 2, only one of the RDI drives RD2 is in the active mode. It is therefore not necessary that the DV1, DV2 devices are both equipped with an NFC reader having the active mode.
• the RDI reader could be replaced by a passive contactless integrated circuit provided that it is able to transfer to the device DV1 the data it receives from the reader RD2, or to send to the reader RD2, by load modulation, data that the device DVl provides.
• embodiments of the invention are based on the idea of incorporating into a non-contact passive low cost integrated circuit (so-called "low end”) a contact communication port and hard-wired logic means. for real-time transmission back to the contact communication port of the data received by the integrated circuit via its contactless communication interface.
• a non-contact passive low cost integrated circuit so-called "low end”
• embodiments of the invention relate to an integrated circuit data exchange device on a semiconductor chip comprising a passive NFC contactless communication interface for establishing a contactless communication channel with an NFC component. active, and a processing unit for processing commands received via the contactless communication interface, the device further comprising a contact communication port, and a wired logic routing circuit configured to copy in real time on the port communication device to the data that the device receives via the contactless communication interface.
• the routing circuit is also configured to copy in real time on the communication port to R2009 / 000933
• the device is configurable in a first mode of operation in which data received via the contactless communication interface are not recopied on the contact communication port and in a second mode of operation in which data are copied to the contact communication port.
• the routing circuit is also configured to provide the processing unit with data received via the contact communication port and to provide the contact communication port with data provided by the processing unit, way that the processing unit can communicate with an external device via the contact communication port.
• the routing circuit processing is configured to detect whether first incoming data is received via the contactless communication interface or via the contact communication port, and temporarily disable or inhibit a data reception circuit of the contact communication port if incoming data is received via the contactless communication interface, or disable or temporarily disable a data receiving circuit of the contactless communication interface if the incoming data is received via the communication port to contact.
• the device comprises a non-volatile memory and the processing unit is configured to execute a write command of the memory comprising a write address and data to be written, and a read command of the memory comprising a read address.
• the device is configurable in a Transparent operating mode in which the routing circuit copies in real time to the contact communication port data that the device exchanges via the contactless communication interface, and, in response to a command to write data to the non-volatile memory, the processing unit does not write the data to the nonvolatile memory but writes it to a volatile buffer.
• the device is the Transparent operating mode
• the processing unit is configured to, in response to a data write command in the non-volatile memory, write the data data into the volatile buffer and setting a flag to a determined value indicating that data has been written to the volatile buffer, and executing flag write and read commands received after positioning the flag.
• the device comprises at least one write-accessible configuration bit configured to place the device in the Transparent operating mode or in a standard operating mode in which data exchanged by the device via the communication interface contactless are not recopied by the routing circuit on the contact communication port.
• the device comprises at least one write-accessible configuration bit configured to place the device in the Transparent operating mode or in a buffer operating mode in which data exchanged by the device via the communication interface contactless are copied to the contact communication port by the routing circuit and wherein the processing unit executes commands for writing data from the memory by writing the data into the memory.
• the contact communication port comprises a bidirectional data input / output terminal, a data transmitter circuit and a data receiver circuit both connected to the input / output terminal.
• the device comprises a circuit for extracting a first power supply voltage from an antenna signal present in an antenna circuit of the contactless communication interface, and a power supply contact for receiving an external power supply voltage in the absence of an antenna signal.
• the device comprises a circuit for extracting a clock signal from an antenna signal 00933
• an antenna circuit of the contactless communication interface and a circuit for generating the clock signal in the absence of an antenna signal.
• Embodiments of the invention also relate to a data exchange system comprising a first terminal device comprising a contactless integrated circuit reader, a data exchange device as described above, a second connected terminal device. the contact communication port of the data exchange device, and wherein the first and second terminal devices are configured to exchange data via the data exchange device and the contactless integrated circuit reader.
• the second terminal device is configured to communicate data to the first terminal device by sending commands to the data exchange device for writing these data into a memory of the data exchange device used as a box. exchange of data.
• the first terminal device is configured to communicate data to the second terminal device by sending commands to the data exchange device for writing this data into a memory of the data exchange device.
• Embodiments of the invention also relate to a method for exchanging data without contact with a terminal device without an NFC reader function, comprising the steps of providing a data exchange device comprising a communication interface without passive NFC contact, a processing unit for processing commands received via the contactless communication interface, providing a contact communication port in the data exchange device, connecting the terminal device to the contact communication port of the device for data exchange, establish a communication channel without contact with the data exchange device, transfer data to the data exchange device via the contactless communication channel, copy in real time, on the communication port in contact with the data exchange device, the incoming data received by the exchange device d e data, and receive the data in the second 00933
• the method comprises the steps of sending the data exchange device, in the contactless communication channel, an acknowledgment of receipt of the data, and copy the acknowledgment of receipt in real time on the contact communication port of the data exchange device.
• the step of transferring the data to the data exchange device comprises a step of sending to the data exchange device a write command of the data in a non-volatile memory of the exchange device of data.
• the method comprises the steps of copying in real time, on the contact communication port of the data data exchange device, the writing command of the data, and receiving the write command. data in the second terminal device via the contact communication port of the data exchange device.
• the method comprises a step of configuring the data exchange device to execute the write command by writing the data to an area of the memory designated by an address included in the command writing.
• the method comprises a step of configuring the data exchange device to execute the write command by writing the data into a volatile buffer.
• the method comprises a step of configuring the data exchange device to execute the write command by writing the data into a volatile buffer and to set a flag to a value determined that data was written to the volatile buffer.
• the method comprises a step consisting of, after having received a copy of the command, sending to the data exchange device, by the terminal device, for acknowledgment of receipt, a write command in the flag of a data whose value is different from said determined value.
• the method comprises a step of receiving data sent by the terminal device comprising the steps of transferring the data from the terminal device to the data exchange device by sending to the data exchange device, by the terminal device, a write command of the data in a non-volatile memory of the data exchange device used as a data exchange box, and address to the data exchange device, via the contactless communication channel, a command for reading the data in the memory of the exchange device.
• FIGS. 1 and 2 previously described illustrate two examples of conventional integration of NFC technology in terminal devices, by using active components,
• FIG. 3 represents the architecture of a passive integrated circuit according to a first embodiment of the invention and also illustrates an example of integration of the NFC technology into a terminal device by means of such an integrated circuit
• FIG. 4A represents the architecture of a contactless integrated circuit according to a second embodiment of the invention
• FIG. 4B a detail of embodiment of the integrated circuit of FIG. 4A
• FIG. 5 is a table describing modes of operation of the integrated circuit of FIG. 4A.
• FIGS. 6A to 6E illustrate steps of a data transmission between an NFC terminal device and a terminal device equipped with the integrated circuit of FIG. 4A;
• FIGS. 7A to 7D illustrate steps of a data transmission between the terminal device equipped with the integrated circuit of FIG. 4A and the NFC terminal device
• FIG. 8A represents the architecture of a contactless integrated circuit according to a third embodiment of the invention
• FIG. 8B a detail of embodiment of the integrated circuit of FIG. 8A
• FIG. 9 is a table describing modes of operation of the integrated circuit of FIG. 8A
• FIGS. 10A to 10D illustrate steps of a data transmission between an NFC terminal device and a terminal device equipped with the integrated circuit of FIG. 8A
• FIGS. 11A to HD illustrate steps of a data transmission between the terminal device equipped with the integrated circuit of FIG. 8A and the NFC terminal device
• FIG. 12 represents an embodiment of the integrated circuit of FIG. 8A
• FIG. 13 represents an antenna signal appearing in an antenna circuit of the integrated circuit of FIG. 12,
• FIG. 14 represents an embodiment of a wired logic routing circuit represented in the form of a block in FIG. 12;
• FIG. 15 describes groups of signals involved in the operation of the routing circuit;
• FIGS. 16A and 16B are tables describing the operation of an element of the routing circuit
• FIG. 17 is a table describing the operation of another element of the routing circuit
• FIGS. 18A, 18B are timing diagrams describing the operation of yet another element of the routing circuit
• FIG. 19 shows an embodiment of a contact communication port according to one embodiment of the invention
• FIG. 20 represents an example of encoding signals passing through the contact communication port
• FIG. 21 shows yet another embodiment of an integrated circuit according to the invention.
• FIG. 3 schematically represents a contactless integrated circuit architecture ICC2 according to an embodiment of the invention as well as an example of integration of the NFC technology into a terminal device DV2 thanks to the integrated circuit ICC2.
• NFC reader RDI which emits a magnetic field FLD
• the reader RDI being connected to a terminal device DV1 or integrated therein.
• non-contact does not mean that the integrated circuit ICC2 is devoid of any electrical contact and only means that the integrated circuit comprises NFC-type contactless communication means.
• the term “passive” does not necessarily mean that the integrated circuit is devoid of any power source, and only means that it does not include means for emitting a magnetic field.
• a passive integrated circuit often uses the ambient magnetic field to generate electrical voltages necessary for its operation, some applications may require the addition of a self-contained voltage source such as an electric battery.
• the contactless integrated circuit ICC2 is formed on a semiconductor chip and comprises a CLER data transmission / reception circuit, a cabled logic processing unit ML2 ("Main Logic"), a clock circuit CKCT, a memory plane MEM, a power supply circuit PS1 and an antenna circuit Lc-Ca.
• the antenna circuit and the CLER circuit form what is commonly referred to as a contactless communication interface.
• This contactless communication interface is here entirely passive in that the integrated circuit ICC2 has no means for applying to the antenna circuit an excitation signal that would emit a magnetic field.
• the antenna circuit comprises an antenna coil Lc and at least one tuning capacitance Ca for tuning the antenna circuit to a natural frequency in the vicinity of the oscillation frequency of the magnetic field FLD, for example 13.56 MHz.
• the antenna coil Lc may be a component external to the semiconductor chip or arranged on one side thereof (technique called “coil on chip”).
• the clock circuit CKCT extracts a clock signal CK1 from an antenna signal Sac appearing in the antenna circuit in the presence of the magnetic field FLD.
• the memory array MEM comprises a non-volatile memory zone of programmable and electrically erasable type (Flash, EEPRCM ...) and may include a RAM area.
• Flash programmable and electrically erasable type
• Other conventional means known to those skilled in the art can be provided and will not be described here, such as a charge pump providing a high erase or memory programming voltage, cryptographic (optional) means, etc.
• the reader RDI sends DTr data to the integrated circuit ICC2 ("incoming data") and the integrated circuit sends DTx data to the reader RDI ("outgoing data”), these two operations intervening the one after the other ("half duplex").
• the reader RDI modulates the magnetic field FLD, for example the amplitude of the magnetic field.
• a data carrier modulation signal DTr appears in the antenna signal Bag of the integrated circuit ICC2.
• the CLER circuit filters the antenna signal to extract the data carrier signal DTr, then decodes the DTr data and supplies it to the processing unit ML2.
• the data to be transmitted DTx are provided by the processing unit ML2 to the circuit CLER. This codes them according to an appropriate protocol, transforms them into a load modulation signal that it applies to the antenna circuit Lc-Ca.
• the CLER circuit is for example configured to encode / decode these data according to one or more known standards such as ISO 14 443, ISO 15 693, Felica®.
• the ML2 processing unit is configured ⁇ here to perform standard commands as commands identification, settlement control of a contactless communication channel, commands for reading or writing blocks in the memory MEM etc.
• the processing unit may be configured to process authentication commands (requiring the provision of a cryptography circuit).
• the integrated circuit ICC2 comprises a CTP contact communication port and a routing circuit MX which is arranged (interposed) between the CLER circuit, the ML2 processing unit and the CTP port.
• the routing circuit MX is configured to route the processing unit ML2 the incoming data DTr while copying them in real time to the communication port CTP contact, and to route to the circuit CLER outgoing data DTx while copying them in real time on the CTP communication port.
• the circuit ICC2 is associated with a device DV2 which is connected to the communication port CTP.
• the DV2 device includes a microprocessor MP that receives and processes the data DTr, DTx copied in real time on the CTP port of the circuit MX.
• the routing circuit MX and the communication port CTP of the integrated circuit ICC2 data DTr transmitted by the reader RDI are received by the processing unit ML2 and transmitted in real time to the device DV2.
• the DTx data transmitted by the processing unit ML2 to the attention of the reader RDI are both provided to the circuit CLER (to be transmitted as a load modulation signal) and transmitted to the device DV2 in real time .
• the integrated circuit ICC2 thus enables the DV1 and DV2 devices to exchange data and to drive an application (transaction, payment, simple data transmission, etc.).
• any collision avoidance or authentication commands may only concern the ML2 processing unit while other data, called application data, concern the DV2 device.
• the contactless communication channel thus forms a kind of "pipe" through which application data can be exchanged.
• the MX circuit copies all the data here incoming DTrs on the CTP port, including if these are commands that only the ML2 processing unit is able to execute.
• the DTr data intended specifically for the integrated circuit ICC2 are therefore received but are not processed by the device DV2.
• the integrated circuit thus behaves, seen from the outside, as a kind of multiplexer having a "contactless input” and a “contact output” which copies all the data received by the contactless input, except possibly and optionally, certain protocol data such as start of field (SOF) or end of frame (EOF) fields.
• SOF start of field
• EEF end of frame
• the device DV2 receives data exchanged which do not concern it directly and which concern for example the management of the communication channel without contact between the reader RDI and the circuit ICC2 (for example, communication channel creation commands, authentication commands, collision avoidance commands, etc.), as well as data to be processed or executed by the ML2 processing unit, such as MEM memory access commands and other commands described later .
• This integral copy mechanism also enables the device DV2 to receive data concerning it, that is to say concerning the "application” layer (application data) and making it possible to drive an application between the DV1 and DV2 devices, these application data which may themselves comprise commands if the application layer is based on a communication protocol using a set of commands.
• the routing circuit MX also provides routing to the CTP contact communication port DTx data 1 transmitted by the processing unit ML2 to the attention of the device DV2 , as well as the routing to the processing unit ML2 of DTr 'data which are transmitted by the device DV2 specifically to his attention.
• the device DV2 can dialogue with the integrated circuit ICC2 and access its resources, including MEM memory.
• the device DV2 To simplify the structure of the processing unit ML2, provision is preferably made for the device DV2 to address the integrated circuit ICC2 with commands for writing or reading the memory that conform to the format of the commands used by the communication channel. without contact, which avoids having to provide in the processing unit specific circuitry to manage commands that would be specific to the CTP contact communication port.
• the device DV2 may also want to address data DTr "to the device DV1 through the integrated circuit ICC2.
• a solution implemented in the present embodiment is to record the data DTr" in the memory MEM.
• a location of the memory MEM is provided for this purpose and is used as a kind of "data exchange box". This location may be a fixed location agreed between the two interlocutors DV1, DV2 or a location dynamically determined at each new communication session between the interlocutors.
• the device DV1 can send to the integrated circuit ICC2 a write command of a particular code (an agreed binary value) at an address of the memory MEM intended to form the address of the data exchange box.
• the device DV2 Since the device DV2 receives a copy of the order, it deduces, after identifying the particular code, that the write address of the code is the address of the exchange box (or the first address of the box). exchange if it covers several addresses). In this case, the device DV2 sends the data DTr "to the integrated circuit by using a command to write data to the identified memory address.
• the address of the data exchange box is clearly indicated in the data accompanying a write command sent by the device DV1 and is different from the data recording address.
• Various other methods may be provided by those skilled in the art for using MEM as a means for exchanging data between DV1, DV2 devices.
• Table 1 summarizes the manner in which the DV1, DV2 devices exchange data.
• FIG. 4A represents an integrated circuit ICC3 comprising the same elements as the integrated circuit ICC2, in particular the circuit MX routing and the CTP contact communication port, and additional features that will be described.
• MEM memory access commands are, for example, commands for writing and reading blocks.
• the memory MEM comprises for example 32 blocks of 64 bits each.
• the write commands are for example of the type [WR] [AD] [DT] and comprise a write command code "WR", an "AD” block address and the data to be written "DT".
• the read commands are of the type [RD] [AD] and include a read command code "RD” and an "AD” block address. These commands are for example compatible ISO 14 443, ISO 15 693 or Felica®.
• the integrated circuit ICC3 differs from the circuit ICC2 in that it comprises a processing unit ML3 equipped with a volatile buffer BUF intended to serve as a data exchange box for the transmission of data DTr ". SBl configuration allows placing the integrated circuit ICC3 in a "Standard" operating mode or in a "Transparent” operating mode.In one embodiment of the ML3 processing unit illustrated in more detail in FIG.
• configuration bit SB1 is stored in the memory MEM, for example in block BL1, at power-up and for example at the time of execution of a reset procedure POR ("Power On Reset") of the circuit integrated, the processing unit ML3 is configured to copy the bit SB1 in a volatile latch LT1 ("latch") and also copy it into a volatile latch LT2
• the configuration bit copied into the latch LT1 is designated SB1 and the configuration bit copied into the lock LT2 is designated SB1 '.
• the bit SB1 1 is writable to the devices DV1, DV2 by means of a write command [WR] [ADSB1] [DT1] in which ADSB1 is the address of the bit SB1 in the non-volatile block BL1 and DT1.
• the processing unit ML3 is configured not to execute the write instruction in the non-volatile memory but to execute it in the lock LT2 to modify the bit SB1 '.
• a "factory configuration" mode is, however, provided for factory setting of the non-volatile bit SB1 at the time of commissioning of the integrated circuit, but this mode of operation is not accessible to the DV1, DV2 devices.
• a comparison logic circuit may be provided to give priority to the non-volatile configuration bit SB1 as configured at the factory, with respect to the value of the volatile bit SB1 'that can be modified by means of the write command.
• the non-volatile configuration bit SB1 and the volatile configuration bit SB1 ' are combined in an AND logic gate whose output provides a resulting configuration bit SB1 "which determines the operating mode of the For example, if the SBl bit is forced to 0 at the factory, the Transparency mode will be selected by default.This optional control is of course inhibited if the SBl bit is set to 1 at the factory.
• bit SB1 'could be used to configure the integrated circuit in the absence of the comparison logic gate.
• bit SB1 as copied in the lock LT1 could be used in the absence of the lock LT2, the lock LT1 could then be made accessible in writing.
• the bit SB1 as stored in the block BL1 of the nonvolatile memory MEM determines the operating mode of the integrated circuit when it is powered up, but the bit SB1 'can be configured by the one of the devices DV1, DV2 by means of a write command, which modifies the value of the resulting bit SB1 "if the bit SB1 is at 1.
• the processing unit ML3 executes a command to write or read a block of the memory MEM in a conventional manner, by accessing the memory MEM in writing or reading at the address of the block indicated in the command.
• Standard mode may or may not include disabling the DTr incoming data routing function and DTx outgoing data to the CTP port and disabling the CTP port.
• the MX circuit behaves as a simple wire between the ML3 processing unit and the CLER circuit and the integrated circuit ICC3 operates as a conventional contactless integrated circuit.
• the circuit MX In the Transparent mode of operation, the circuit MX is active and performs all the previously described functions, in particular the routing of a copy of the incoming data DTr and outgoing data DTx to the port CTP.
• a characteristic of this mode of operation is that the processing unit ML3 does not execute a write command of a memory block in a conventional manner: instead of writing the data supplied to the block address " AD "specified in the command, it writes them to the BUF volatile buffer regardless of the block address specified in the command. Also, the processing unit ML3 does not conventionally execute a command to read a block: instead of reading data at the block address indicated in the command, it reads the data in the buffer BuF.
• An additional feature of the Transparent operating mode is optionally provided for implementing an acknowledgment mechanism for the data sent by the DV1 device.
• This characteristic consists, for example, in configuring the processing unit ML3 to manage a volatile flag F by setting it to a determined logical value, for example 1, when data is written in the buffer BUF.
• the flag F is for example a bit included in the BUF buffer (see FIG. 4A).
• FIGS. 6A to 6E a data sending sequence of the device DV1 to the device DV2 when the integrated circuit is in the transparent mode, illustrated in FIGS. 6A to 6E;
• FIGS. 7A to 7D a data sending sequence from the DV2 device to the DV1 device when the integrated circuit is in the Transparent mode, illustrated in FIGS. 7A to 7D.
• the routing circuit MX and the communication port CTP contact are not represented.
• the intervention of these elements for the real-time transmission of a copy of the data DTx, DTr to the device DV2 is considered as implicit, as well as their intervention during a data exchange between the device DV2 and the integrated circuit ICC3.
• the integrated circuit ICC3 does not have an independent power source and is powered by a voltage Vl that the PSl power circuit extracted from the antenna signal Bag. The steps shown in FIGS. 6A to 7D are thus conducted while the magnetic field FLD is emitted by the RDI reader.
• the device DV1 sends to the integrated circuit ICC3 a command [WR] [AD] [DT] containing the data DT intended for the device DV2.
• the processing unit ML3 does not write these data in memory and writes them in the buffer BUF without taking into account the address AD.
• the address AD can therefore be any and for example 0.
• a copy of the [WR] [AD] [DT] command is transmitted in real time to the DV2 device.
• the processing unit ML3 sets the flag F to 1 to indicate that the buffer has just been written.
• the processing unit ML3 sends a write acknowledgment [ACK] to the device DV1, signifying that the write command has been executed.
• the device DV2 receives a real-time copy of this acknowledgment, transmitted by the circuit MX.
• the device DV2 sends the integrated circuit an erase command of the flag F. This command is for example the control of write a null value [WR] [ADF] [0] using the ADF virtual address.
• the device DV1 then sends a command for reading the flag [RD] [ADF] to the integrated circuit ICC3 (whose copy is sent to the device DV2 in real time).
• the processing unit responds to the command by sending the null value of the flag F to the device DV1, which can thus know that the device DV2 has read the data written in the buffer BUF .
• the device DV2 could send to the integrated circuit a reading command of the buffer BUF if the data DT were not read correctly during the step of FIG. 6A, and delete the flag F after reading the stamp ..
• the DV2 device sends the integrated circuit ICC3 a [WR] [AD] [DT] command containing the data for the DV1 device .
• the processing unit ML3 writes the data DT in the buffer BUF without taking into account the address AD.
• the ML3 processing unit also sets the flag F to 1, as before.
• the processing unit ML3 sends to the device DV2 the write acknowledgment [ACK] signifying that the command has been executed.
• the device DV1 sends to the integrated circuit a read command [RD] [AD].
• AD address can be any because the processing unit does not take into account. Copy of the playback command is sent in real time to the DV2 device.
• the processing unit ML3 reads the data DT in the buffer BUF and supplies it to the device DV1 while sending a copy of the response to the device DV2.
• the device DV1 erases the flag F to ensure the device DV2 that the buffer has been read because the device DV2 receives in real time a copy of everything that receives the device DVl.
• FIG. 8A represents an integrated circuit ICC4 equipped with the routing circuit MX and the communication port with CTP contact.
• the circuit ICC4 implements the characteristics of the circuit ICC3 previously described and offers additional features that will be described.
• This embodiment is based on the fact that some applications may require data exchange in "non real time" ("non real time”) between the DV1 and DV2 devices.
• the device DV2 must be able to receive data transmitted to it by the device DV1 at times when the device DV1 is no longer present near the integrated circuit ICC4.
• the volatile buffer BUF can not be used because the device DV1 may wish to send a string of bits that can not be contained in the single BUF buffer.
• the voltage Vl would disappear and the data in the volatile buffer would be lost.
• the non-volatile memory MEM is thus used here as a data exchange box, all or some of the blocks available in the memory that can be used for this data exchange. Modes of operation of the ICC4 integrated circuit
• the configuration bits SBO, SB1 are stored in the memory MEM, for example in the block BL1.
• the processing unit ML4 is configured to copy the bits SBO, SB1 in two volatile locks LT10, LTIl ("latches") and copy them also in two other volatile locks LT20, LT21.
• the configuration bits copied in the locks LT10, LTI1 are designated SBO, SB1 and the configuration bits copied in the locks LT20, LT21 are designated SBO ', SB1'.
• the bits SBO ', SB1' are writable to the devices DV1, DV2 by means of a write command [WR] [ADSB01] [DT01] in which ADSBO1 is the address of the bits SBO, SB1 in the non-block volatile BLl, and DTOl the value to give the bits SBO ', SBl'.
• the processing unit ML4 is configured not to execute this write instruction in the non-volatile memory but to execute it in the locks LT20, LT21 to modify the bits SBO ', SBl'.
• a "factory configuration" operating mode is also provided for configuring the non-volatile bits SBO, SB1 at the time of commissioning of the integrated circuit, the bits SBO, SB1 remaining inaccessible outside this operating mode.
• a comparison logic circuit may be provided to give priority to the non-volatile configuration bits SBO, SB1 as configured at the factory, with respect to the values of the volatile bits SBO ', SB1' being modifiable by means of a control of writing.
• the non-volatile configuration bit SBO and the volatile configuration bit SBO ' are combined in a first AND logic gate whose output provides a resultant configuration bit SBO ".
• non-volatile configuration SB1 and the volatile configuration bit SB1 ' are combined in a first AND logic gate whose output provides a resultant configuration bit SB1 ", the resulting configuration bits SBO", SB1 "determining the operating mode of the integrated circuit .
• the buffer mode can not be selected by the device DV1 or DV2 because the resulting bit SB1 "can not be equal to 1
• This mechanism for prohibiting certain modes is inhibited if the bits SBO, SB1 are set to 1 at the factory.
• the bits SBO ', SB1' can be used to configure the integrated circuit, the comparison logic gates being in this case deleted.
• the SBO, SB1 bits as copies in the LT10, LTI1 latches could be used directly to determine the mode of operation.
• the LT20, LT21 locks would then be deleted and the LT10, LTI1 locks could be made writable.
• the bits SBO, SB1 as stored in the block BL1 of the nonvolatile memory MEM determine the operating mode of the integrated circuit when it is powered up, as long as one of the devices DV1, DV2 does not intervene to modify the bits SBO ', SBl' (or the bits SBO, SB1 such as copy in the locks LT10, LTI1, if the locks LT20, LT21 are not provided).
• General characteristics of the operating modes The Standard mode is in line with the one described above.
• the MX routing circuit only provides the signal transition between the ML4 processing unit and the CLER circuit, the CTP port is deactivated, and the ICC4 integrated circuit operates as an integrated circuit without conventional contact.
• the Transparent mode is also in accordance with what has been described above: the MX circuit and the CTP port are active and the write and read commands of the memory are not executed conventionally, the ML4 processing unit writing the received data to the BUF buffer instead of writing them to the memory, and reading the BUF buffer instead of reading the memory.
• the circuit incorporates ICC4 operates thus as the circuit integrates ICC3 in the Transparent mode.
• the circuit integrates ICC4 operates as the integrated circuit ICC2 described above.
• the MX circuit and the CTP port are active and the ML4 processing unit executes write or read commands from the memory in a conventional manner.
• Energy and clock management A constraint of a non-real time data exchange between the DV1 and DV2 devices is that the circuit integrates ICC4 must be able to be electrically powered in the absence of the device DV1 and consequently in the absence of the FLD magnetic field provided by the RDI reader. Also, the integrated circuit needs a clock signal to operate, which the clock extraction circuit CKCT can not provide in the absence of the antenna signal Bag.
• the integrated circuit ICC4 comprises a power supply terminal PWP ("Power Pad") to which the device DV2 is connected and by means of which the latter can supply the integrated circuit ICC4 with a complementary electrical voltage Vl 1 in the absence of the antenna signal Bag.
• PWP Power Pad
• a Ground Pad (GP) terminal is also provided so that both components can have a common potential reference (this ground terminal can also be included in the connections between the DV2 device and the CTP port).
• the integrated circuit ICC4 also comprises a clock generator circuit CKGEN equipped with an oscillator OSC, to supply the clock signal CK1 in place of the extractor circuit CKCT in the absence of the antenna signal.
• the generator CKGEN includes a detector circuit VBS ("VB Sense") which detects the presence of the antenna signal Bag, for example by detecting the presence of an alternating voltage VB on a terminal of the antenna coil Lc, forming here the antenna signal Bag.
• VBS detector circuit
• the CKGEN generator is automatically activated when the integrated circuit is powered up by the VBS circuit if the antenna signal is not present.
• the VBS circuit is of a type known per se, used in the prior art in integrated circuits RFID type "combi" (contact / contactless) to select an external supply voltage in the absence of voltage of internal power extracted from the magnetic field.
• Table 3 illustrates an embodiment of a method for managing the energy and the clock within the integrated circuit ICC4.
• the supply voltage V1 and the clock signal CK1 are extracted from the antenna signal Sac when the integrated circuit is in the Standard and Transparent modes.
• the supply voltage V1 is supplied by the circuit PS1 if the antenna signal is present or is supplied by the device DV2 if the antenna signal is absent.
• the Transparent mode could be used when the voltage Vl 'is supplied by the device DV2, while ensuring the extraction of the clock signal from the antenna signal.
• the voltage Vl 'could also be provided by an autonomous voltage source (eg an electric battery) in applications where the integrated circuit is mounted on or in a support for embedding such an independent voltage source. Selecting the operating mode
• the selection of the operating mode is made first of all to power up the integrated circuit:
• the processing unit places the integrated circuit in the Standard mode at power up if the antenna signal Sac is present.
• the detection of the antenna signal is for example made by the VBS circuit which sends to the processing unit ML4 a detection signal DET.
• the device DV1 can then place the integrated circuit in the buffer mode or in the transparent mode by means of a writing command of the bits SBO 1 , SB1 ';
• the processing unit places the integrated circuit in the buffer mode at power up if the antenna signal Sac is not present. Indeed, the fact that the processing unit is active means that the voltage Vl 'is provided by the device DV2. The device DV2 must therefore be able to access the integrated circuit. Auto-configuration in Buffer mode ensures that the MX circuit and the CTP port are active and the ML4 processing unit can receive write or read commands sent by the DV2 device.
• an asynchronous operating mode or the clock signal is provided by the internal generator CKGEN.
• Figs. 10A to 10D illustrate a data sending sequence from the DV1 device to the DV2 device when the integrated circuit is in the buffer mode
• Figs. 11A to HD illustrate a sending sequence from the device DV2 to the device DV1 when the integrated circuit is in the buffer mode.
• the device DV1 sends the integrated circuit ICC4 a command [WR] [AD] [DT] containing the data intended for the device DV2. Simultaneously a copy of the command [WR] [AD] [DT] is transmitted in real time to the device DV2 by the circuit MX (not shown).
• the processing unit ML4 then writes the data DT in the memory MEM to the address indicated in the command.
• the processing unit ML4 sends a write acknowledgment [ACK] to the device DV1, signifying that the write command has been executed.
• the circuit MX transmits in real time a copy of this acknowledgment to the device DV2.
• FIGS. 10A and 10B may optionally be repeated as many times as necessary if the DV1 device is to communicate a long bit string to the DV2 device. Since the latter knows that the integrated circuit has been placed in the buffer mode, it does not intervene and does not try to read the data as long as the reader RDI emits the magnetic field FLD. The interruption of the supply of the magnetic field, which results in the disappearance of the voltage Vl that the device DV2 monitors, can therefore be used by the device DV2 as an indicator that the data can be read in the manner shown in the figures 10C and 10D.
• the processing unit places the integrated circuit in the buffer mode II is here asynchronous buffer mode
• the device DV2 addresses to the integrated circuit a read command [RD] [AD ] pointing to an address used by the DVl device to write the data.
• the processing unit ML4 reads the data DT in the memory at the address specified by the command and supplies them to the device DV2. These steps can be repeated as much as necessary. Since the device DV2 has received a copy of the write command sent by the device DV1, it knows where the data to be read is. Assuming, in a variant, that the device DV2 has not analyzed these commands and has not memorized the addresses or the data has been written, it can perform a read scan of the contents of the memory MEM to find them.
• a variant of these steps can be implemented in the synchronous buffer mode.
• the device DV2 reads the data while the field FLD is still present, even before the device DV1 has finished writing all the data that it wants to place in the memory MEM.
• An embodiment of the MX routing circuit in which potential conflicts of incoming data are handled is described below.
• Such conflict management includes locking of the contactless communication channel if the DV2 device is the first to send data to the ICC4 circuit or the CTP contact communication port lock if the DV1 device is the first to send data to the ICC4 circuit.
• Such handling of incoming data conflicts also applies to Transparent mode.
• the circuit integrates ICC4 is electrically powered by the voltage Vl 'provided by the device DV2 and the clock signal is provided by the generator CKGEN.
• the integrated circuit is thus placed in the asynchronous buffer mode During the step shown in FIG. 11A, the device
• the processing unit ML4 writes the data DT in the memory MEM to the address indicated in the command.
• the processing unit ML4 sends the write acknowledgment [ACK] to the device DV2.
• ACK write acknowledgment
• the device DV1 is present and emits the magnetic field FLD. It is assumed here that the integrated circuit has just been energized by the appearance of the magnetic field and is automatically placed in the synchronous buffer mode because the antenna signal is present.
• the device DV1 seeks to know if the device DV2 has deposited data in the memory MEM. It thus sends to the integrated circuit a read command [RD] [AD].
• the device DV2 receives a copy of the read command and can thus verify that the data it has deposited in the memory to the attention of the device DV1 are in tram to be read.
• the processing unit ML4 reads the data DT at the indicated address and supplies them to the device DV1 as well as a copy to the device DV2 (the latter thus knows what the DVl device). This reading step can be repeated as much as necessary by the DV1 device, until complete reading of the memory or at the very least of the part of the memory used as a data exchange box.
• the integrated circuit is initially in the asynchronous buffer mode, for example because the device DV2 has maintained the voltage Vl 'after the steps HC, HD.
• the integrated circuit continues to receive the voltage Vl' but the appearance of the Antenna signal is detected by the VBS circuit which deactivates the clock generator CKGEN.
• the clock signal is then provided by the extractor circuit CKCT and the integrated circuit is then in synchronous buffer mode to establish a contactless communication channel and perform the steps of figures HC, HD.
• FIG. 12 represents an embodiment of certain elements of the integrated circuit ICC4, notably the CTP contact communication port, the CLER transmission / reception circuit and the PS1 supply circuit.
• the CTP port comprises a single input / output terminal of the IOP data ("I / O Pad"), an IOBR receiver circuit ("I / O Bit Receiver") and an IOBE transmitter circuit ("I / O Bit Emitter”). ).
• the IOBR circuit has an input connected to the IOP terminal and an output connected to the routing circuit MX.
• the IOBE circuit has an input connected to the routing circuit and an output connected to the IOP terminal.
• the CLER circuit comprises a demodulator circuit DEMOD, a modulator circuit MOD, a receiver circuit BR ("Bit Receiver") and a transmitter circuit BE ("Bit Emitter").
• the modulator circuit MOD has an output connected to two terminals TA, TB of the antenna circuit for effecting a modulation of the impedance thereof (and therefore a charge modulation which is detected by the RDI reader) when DTx data must be sent in the contactless communication channel.
• the DMOD demodulator circuit has an input connected to the terminal TB of the antenna circuit for extracting from the antenna signal Sac a data modulation amplitude signal DTr transmitted by the reader RDI.
• the detector circuit VBS and the clock extractor circuit CKGEN are also connected to the terminal TB of the antenna circuit.
• the circuit BR has an input connected to an output of the demodulator circuit DEMOD, to receive demodulated but coded DTr data, and an output connected to the routing circuit MX to provide decoded DTr data.
• the circuit BE has an input connected to the routing circuit MX for receiving uncoded DTx data, and an output connected to an input of the modulator circuit MOD, to supply the latter with unmodulated encoded DTx data.
• an alternating voltage VA appears on the terminal TA of the antenna circuit and is rectified by the supply circuit PS1 to obtain the DC supply voltage V.
• the circuit PS1 here comprises a diode Dr (or a diode-mounted transistor) reverse climb between the terminal TB of the antenna circuit and the integrated circuit ground, and a smoothing capacitor Cs connected between the terminal TA and the ground.
• the diode Dr imposes on the terminal TB, relative to the ground, a half-wave rectified voltage VB, forming the antenna signal Sac, oscillating between a voltage -Vd representing the threshold voltage of the diode in reverse and a voltage Vmax whose amplitude depends on the distance between the antenna circuit and the antenna coil of the RDI reader (ie the magnetic field strength FLD) and the inductive coupling rate.
• the smoothing capacitance Cs imposes the continuous supply voltage Vl on the terminal TA of the antenna circuit.
• Fig. 14 shows an embodiment of the routing circuit MX.
• the circuit MX comprises a multiplexer circuit RMUX, a demultiplexer circuit EMJX and a control circuit CCT which configures the circuits RMUX and EMUX according to the operating mode of the integrated circuit ICC4 and incoming or outgoing signals.
• the RMUX circuit comprises:
• the EMUX circuit comprises: inputs receiving the signal group FROM_BR,
• the control circuit CCT comprises:
• the EMUXSEL signal determines the demultiplexing function that the EMUX circuit carries out between its inputs and outputs and the RMUXSEL signal determines the multiplexing function that the RMUX circuit carries out between its inputs and its outputs.
• the signals SBO, SB1 are identical in value to the resulting configuration bits SBO ", SB1" and are generated automatically after reading of the latter by the processing unit ML4 as soon as the integrated circuit is powered up, or after writing of the block BLl for configuring the integrated circuit in a different operating mode than the Standard mode.
• Table 4 describes the various signals exchanged between the elements of the circuit MX and the elements ML4, BE, BR, IOBE, IOBR.
• Table 5 describes the composition of the signal groups, and Table 6 describes the function of the signals described by Table 4.
• Table 5 is also shown in Fig. 15 which completes Fig. 14.
• Table 7 in the Appendix, also shown in FIG. 17, describes the multiplexing function performed by the RMUX circuit, the left-hand column indicating the outputs of the RMUX circuit and the two other columns indicating which input signal is being fed. on the corresponding output (output on the same line) depending on the value of the RMUXSEL signal.
• Table 8 in the Appendix also shown in FIG. 16A, describes the demultiplexing function performed by the EMUX circuit, the left column indicating the outputs of the EMUX circuit and the four other columns indicating which input signal is being fed. sure the corresponding output (output on the same line) according to the value of the EMUXSEL signal.
• FIG. 16B represents an equivalent developed version of Table 8, which more clearly shows the multiplexing function performed by the EMUX circuit as a function of the EMUXSEL signal.
• the outputs of the EMUX circuit are identified in the left column for each EMUXSEL value and the inputs of the EMUX circuit are identified in the top line. Crosses indicate which entry is copied to which output.
• the EMUX circuit has two modes of operation, namely a "Standard" operating mode that is selected when the integrated circuit ICC4 is in the Standard mode, and a "Contact” mode that is selected when the integrated circuit is in the "mode". Transparent "or” Stamp ". In these last two operating modes, the CTP contact communication port is in the active state and the MX circuit carries out the routing described above.
• EMUXSEL 00
• the CTP communication port is disabled ("disabled").
• the signals received by the EMUX circuit are exclusively sent to the BE circuit.
• the EMUXSEL signal can have three values corresponding to three different demultiplexings:
• the IOBE circuit comprises a "slave" mode of operation which is activated by setting the IOBE_BitRateEn control signal to 1. When this signal is at 1, the IOBE BitRate signal is used to control the sending of data by the IOBE circuit
• the control signal IOBE_BitRate copies the signal BE_RFNewBit (see Figure 16B) which is emitted by the circuit BE when it is ready to send data in the contactless communication channel.
• the sending of data on the IOP terminal is done in synchronization with the transmission of data in the contactless communication channel by the circuit BE (the IOBE circuit is thus slaved to the circuit BE).
• the control signal IOBE_BitRate copies the signal BR_BitReady (see Figure 16B) which is sent by the circuit BR when the latter has received data via the contactless communication channel.
• the sending of data on the terminal IOP is carried out in real time in synchronization with the reception of data via the contactless communication channel by the circuit BR (the IOBE circuit is here enslaved to the circuit BR).
• FIG. 18A is a flowchart that describes a decision process implemented by the CCT control circuit during data reception, to set the value of the EMUXSEL signal which configures the operating mode of the EMUX demultiplexing circuit.
• the circuit CCT After having been reset by the Reset signal, the circuit CCT sets the signal BR_DISABLE to 0 to activate the circuit BR ensuring the reception of the bits in the communication channel without contact. It also sets the IOBR_DISABLE signal to 1 to disable for all intents and purposes the IOBR circuit receiving bits on the IOP terminal.
• the CCT circuit determines whether the contact mode is allowed or not. The answer is negative if the signals SBO, SB1 are both equal to 1. In this case the control circuit sets the EMUXSEL signal to the value 00 (Standard mode) and waits for the next reset (decided by the control unit). ML4 treatment).
• the contact mode is, on the contrary, allowed if one of the signals SB1 or SBO is equal to 0 (transparent mode or buffer mode).
• the circuit CCT sets the signal IOBR_DISABLE to 0 to activate the reception circuit IOBR and then waits to receive the signal BR_SOF indicating the reception of a frame start via the communication channel or to receive the signal IOBR_SOF indicating the reception of a frame start on the IOP terminal. If the IOBR_SOF signal is received first, the CCT circuit sets the BR_DISABLE signal to disable the BR circuit and prevent a collision between the data being received on the IOP terminal and data that could be received from time to time. the other via the contactless communication channel.
• the CCT circuit sets the EMUXSEL signal to the value 11 (see FIG. 16B, exclusive communication between the integrated circuit and the DV2 device) and then wait for the next reset. If, on the contrary, the BR_SOF signal is received first, the CCT circuit sets the IOBR_DISABLE signal to deactivate the IOBR circuit and prevent a collision between the data being received via the contactless communication channel and data which could be received. from one moment to another on the IOP terminal. Also, the circuit CCT sets the EMUXSEL signal to the value 10 (see FIG. 16B) in order to transfer to the IOBE circuit a copy of all the data received by the circuit BR via the contactless communication channel.
• the circuit CCT then waits to receive the signal BR_EOF indicating that the circuit BR has received a frame end via the contactless communication channel. When this signal is received, it sets the BR_DISABLE signal to 1 to disable the BR circuit and sets the EMUXSEL signal to 01 to ensure transfer to the IOBE circuit of all the data sent by the processing unit to the circuit BE, then wait for the next reset.
• Fig. 18B is a flow chart that describes the decision process implemented by the CCT control circuit during a data transmission, to determine the value of the RMUXSEL signal that configures the operating mode of the RMUX multiplexing circuit.
• the circuit CCT determines whether the contact mode is authorized or not. The answer is negative if the signals SBO, SB1 are both equal to 1. In this case the circuit CCT sets the signal RMUXSEL to the value 00 (Standard mode) and waits for the next reset (decided by the processing unit ML4). The contact mode is as previously authorized if one of the signals SB1 or SBO is equal to 0. In this case, the circuit CCT waits to receive the signal BR_SOF indicating the reception of a frame start via the communication channel or to receive the IOBR_SOF signal indicating the reception of a frame start on the IOP terminal.
• the circuit CCT sets the signal RMUXSEL to 0 so that the incoming data and the signals supplied by the circuit BR are sent to the processing unit ML4 (see Table 7 or FIG. 17), and wait for the next reset. If the signal IOBR_SOF is received first, the circuit CCT sets the signal RMUXSEL so that the incoming data and the signals supplied by the circuit IOBR are sent to the processing unit ML4, and waits for the next reset.
• FIG. 19 represents a contact communication channel comprising a conductive line L1 connecting the IOP terminal to the device DV2 and a line L2 carrying the voltage V1 '.
• the integrated circuit ICC4 and the device DV2 can each pull the line at 0 by means of an NMOS transistor having its source at ground, or at 1 by means of a PMOS transistor having its source receiving the voltage Vl or Vl '(not shown).
• the data encoding and the format of the SOF frame start and EOF frame end fields in the contact communication channel may be of any appropriate known type.
• the data encoding and the format of the SOF frame start fields and end of frame EOF in the contact communication channel is. the same as that used by the contactless communication channel. It can be advantageously provided that the contactless communication channel operates according to several known contactless protocols, for example ISO 14443 and ISO 15693.
• FIG. 20 represents a coding of the PWM type data in the contact communication channel according to a known protocol such as ISO 14443.
• the "0" is coded by a pulse at 1 of duration TO within a period of the clock signal and the "1" is encoded by a pulse at 1 of a duration Tl greater than TO within the period of the clock signal.
• a SOF frame start field is encoded by a pulse at 1 occurring at a time Tsof1 calculated from the first zero crossing of the data signal on the line L1 and having a duration Tsof2, and an end field of EOF frame is encoded by a pulse at 1 of duration Teof greater than TO and T1.
• Embodiments of the invention can provide low cost integrated circuits to promote the development of NFC technology in various application domains. Such integrated circuits can be implantable in known devices and serve as an NFC data exchange device without requiring structural modifications to the host devices and requiring only inexpensive software modifications.
• a data exchange device is capable of various variants.
• the modes of operation Buffer or Transparent allowing the device DV2 to communicate data to the device DV1 by using a memory zone of the integrated circuit as a data exchange box (volatile buffer for the Transparent mode and non-volatile memory for Buffer mode). Transmission in time
• the embodiment of the DV1 device of the data provided by the device DV2 could also be provided.
• the circuit incorporates ICC5 differs from the integrated circuit ICC4 in that it comprises a clock terminal CKP receiving the clock signal CK1 to which the device DV2 is connected.
• the clock signal CK is extracted from the magnetic field and is used by the integrated circuit ICC5 to manage the contactless communication channel.
• the signal CK thus enables the device DV2 to synchronize with the communication channel without contact.
• the data supplied to the IOBR circuit by the device DV2 can be sent directly into the contactless communication channel without passing through the buffer BUF or the memory MEM.
• circuit MX as represented in FIG. 14 is only an example of what the person skilled in the art could realize in the light of the teaching disclosed in the present application.
• the copying and routing function urged by the circuit MX can be carried out in another way, for example with number state machines. finite states, with shift circuits, etc.
• the MX circuit has been described as a circuit independent of the ML2, ML3, ML4 processing unit to facilitate the understanding of the invention, it will be apparent to those skilled in the art that the function of routing carried out by the circuit MX can be incorporated in the processing unit ML2, ML3 or ML4, which must then be equipped with inputs / outputs connected to the communication port CTP. Similarly, the functions performed by the IOBR and IOBR circuits can be integrated into the processing unit, which can then be directly connected to the IOP terminal.
• the contact communication channel could use two lines of data transmission "half-duplex" , or even understand a parallel bus by transforming in real time the data received in series via the contactless communication channel into parallel data by means of shift registers.

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