EP2224469A3 - Verfahren zum Ätzen von 3-D-Strukturen in ein Halbleitersubstrat, einschließlich der Oberflächenbehandlung - Google Patents

Verfahren zum Ätzen von 3-D-Strukturen in ein Halbleitersubstrat, einschließlich der Oberflächenbehandlung Download PDF

Info

Publication number: EP2224469A3
Authority: EP; European Patent Office
Prior art keywords: substrate; etching; structures; semiconductor substrate; order
Prior art date: 2009-02-25
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Withdrawn

Application number

EP10154439.3A

Other languages

English (en)

French (fr)

Other versions

EP2224469A2 (de

Inventor

Patrick Verdonck

Marc Van Cauwenberghe

Alain Phommahaxay

Ricardo Cotrin Teixeira

Nina Tutunjyan

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Interuniversitair Microelektronica Centrum vzw IMEC

Original Assignee

Interuniversitair Microelektronica Centrum vzw IMEC

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

2009-02-25

Filing date

2010-02-23

Publication date

2015-03-25

2010-02-23 Application filed by Interuniversitair Microelektronica Centrum vzw IMEC filed Critical Interuniversitair Microelektronica Centrum vzw IMEC

2010-09-01 Publication of EP2224469A2 publication Critical patent/EP2224469A2/de

2015-03-25 Publication of EP2224469A3 publication Critical patent/EP2224469A3/de

Status Withdrawn legal-status Critical Current

Links

239000000758 substrate Substances 0.000 title abstract 6
238000005530 etching Methods 0.000 title abstract 2
239000004065 semiconductor Substances 0.000 title abstract 2
238000000034 method Methods 0.000 title 1
238000002360 preparation method Methods 0.000 title 1
238000000708 deep reactive-ion etching Methods 0.000 abstract 3
238000001125 extrusion Methods 0.000 abstract 2
238000000227 grinding Methods 0.000 abstract 2
244000025254 Cannabis sativa Species 0.000 abstract 1
230000015572 biosynthetic process Effects 0.000 abstract 1
238000001312 dry etching Methods 0.000 abstract 1
238000004519 manufacturing process Methods 0.000 abstract 1
238000004381 surface treatment Methods 0.000 abstract 1
238000001039 wet etching Methods 0.000 abstract 1

Classifications

- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching

Landscapes

Engineering & Computer Science (AREA)
Physics & Mathematics (AREA)
Condensed Matter Physics & Semiconductors (AREA)
General Physics & Mathematics (AREA)
Manufacturing & Machinery (AREA)
Computer Hardware Design (AREA)
Microelectronics & Electronic Packaging (AREA)
Power Engineering (AREA)
Plasma & Fusion (AREA)
Mechanical Treatment Of Semiconductor (AREA)
Drying Of Semiconductors (AREA)
Weting (AREA)

EP10154439.3A 2009-02-25 2010-02-23 Verfahren zum Ätzen von 3-D-Strukturen in ein Halbleitersubstrat, einschließlich der Oberflächenbehandlung Withdrawn EP2224469A3 (de)

Applications Claiming Priority (1)

Application Number	Priority Date	Filing Date	Title
US15542609P	2009-02-25	2009-02-25

Publications (2)

Publication Number	Publication Date
EP2224469A2 EP2224469A2 (de)	2010-09-01
EP2224469A3 true EP2224469A3 (de)	2015-03-25

Family

ID=42211922

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
EP10154439.3A Withdrawn EP2224469A3 (de)	2009-02-25	2010-02-23	Verfahren zum Ätzen von 3-D-Strukturen in ein Halbleitersubstrat, einschließlich der Oberflächenbehandlung

Country Status (2)

Country	Link
US (1)	US20100216308A1 (de)
EP (1)	EP2224469A3 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
MD360Z (ro) *	2010-09-23	2011-11-30	Институт Прикладной Физики Академии Наук Молдовы	Procedeu de formare a suprafeţelor microstructurate ale substraturilor de siliciu
JP2013084695A (ja) *	2011-10-06	2013-05-09	Tokyo Electron Ltd	半導体装置の製造方法
US9006703B2 (en)	2013-07-31	2015-04-14	International Business Machines Corporation	Method for reducing lateral extrusion formed in semiconductor structures and semiconductor structures formed thereof
KR20240069818A (ko) *	2017-02-10	2024-05-20	어플라이드 머티어리얼스, 인코포레이티드	딥 트렌치에서의 저온 선택적 에피택시를 위한 방법 및 장치

Citations (4)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
WO2000072366A1 (en) *	1999-05-21	2000-11-30	Plasmasil, L.L.C.	Method for improving thickness uniformity of semiconductor wafers
US20080121808A1 (en) *	2006-11-24	2008-05-29	Tower Semiconductor Ltd.	High Resolution Integrated X-Ray CMOS Image Sensor
US20080164573A1 (en) *	2007-01-05	2008-07-10	Basker Veeraraghaven S	Methods for fabricating silicon carriers with conductive through-vias with low stress and low defect density
US20080258267A1 (en) *	2005-02-17	2008-10-23	Hiroaki Nakashima	Method of Producing Semiconductor Device and Semiconductor Device

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US2619414A (en) *	1950-05-25	1952-11-25	Bell Telephone Labor Inc	Surface treatment of germanium circuit elements
US5204288A (en) *	1988-11-10	1993-04-20	Applied Materials, Inc.	Method for planarizing an integrated circuit structure using low melting inorganic material
DE4241045C1 (de)	1992-12-05	1994-05-26	Bosch Gmbh Robert	Verfahren zum anisotropen Ätzen von Silicium
JP3612158B2 (ja) *	1996-11-18	2005-01-19	スピードファム株式会社	プラズマエッチング方法及びその装置
US6794272B2 (en) *	2001-10-26	2004-09-21	Ifire Technologies, Inc.	Wafer thinning using magnetic mirror plasma
US6846747B2 (en) *	2002-04-09	2005-01-25	Unaxis Usa Inc.	Method for etching vias
US6818532B2 (en) *	2002-04-09	2004-11-16	Oriol, Inc.	Method of etching substrates
JP4817291B2 (ja) *	2005-10-25	2011-11-16	Ｏｋｉセミコンダクタ株式会社	半導体ウェハの製造方法
JP4799542B2 (ja) *	2007-12-27	2011-10-26	株式会社東芝	半導体パッケージ

2010
- 2010-02-23 EP EP10154439.3A patent/EP2224469A3/de not_active Withdrawn
- 2010-02-24 US US12/711,544 patent/US20100216308A1/en not_active Abandoned

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
WO2000072366A1 (en) *	1999-05-21	2000-11-30	Plasmasil, L.L.C.	Method for improving thickness uniformity of semiconductor wafers
US20080258267A1 (en) *	2005-02-17	2008-10-23	Hiroaki Nakashima	Method of Producing Semiconductor Device and Semiconductor Device
US20080121808A1 (en) *	2006-11-24	2008-05-29	Tower Semiconductor Ltd.	High Resolution Integrated X-Ray CMOS Image Sensor
US20080164573A1 (en) *	2007-01-05	2008-07-10	Basker Veeraraghaven S	Methods for fabricating silicon carriers with conductive through-vias with low stress and low defect density

Also Published As

Publication number	Publication date
EP2224469A2 (de)	2010-09-01
US20100216308A1 (en)	2010-08-26

Legal Events

Date	Code	Title	Description
2010-07-30	PUAI	Public reference made under article 153(3) epc to a published international application that has entered the european phase	Free format text: ORIGINAL CODE: 0009012
2010-09-01	AK	Designated contracting states	Kind code of ref document: A2 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO SE SI SK SM TR
2010-09-01	AX	Request for extension of the european patent	Extension state: AL BA RS
2015-02-20	PUAL	Search report despatched	Free format text: ORIGINAL CODE: 0009013
2015-03-25	AK	Designated contracting states	Kind code of ref document: A3 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO SE SI SK SM TR
2015-03-25	AX	Request for extension of the european patent	Extension state: AL BA RS
2015-03-25	RIC1	Information provided on ipc code assigned before grant	Ipc: H01L 21/3065 20060101ALI20150218BHEP Ipc: H01L 21/304 20060101AFI20150218BHEP
2016-02-19	STAA	Information on the status of an ep patent application or granted ep patent	Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN
2016-03-23	18D	Application deemed to be withdrawn	Effective date: 20150926

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EP2398044A3 (de)	2014-07-02	Verfahren zur Passivierung einer Siliciumoberfläche
EP2224469A3 (de)	2015-03-25	Verfahren zum Ätzen von 3-D-Strukturen in ein Halbleitersubstrat, einschließlich der Oberflächenbehandlung
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