EP2211381A1 - Insulated casing with low stray capacitance for electronic components - Google Patents

Insulated casing with low stray capacitance for electronic components Download PDF

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Publication number
EP2211381A1
EP2211381A1 EP10150992A EP10150992A EP2211381A1 EP 2211381 A1 EP2211381 A1 EP 2211381A1 EP 10150992 A EP10150992 A EP 10150992A EP 10150992 A EP10150992 A EP 10150992A EP 2211381 A1 EP2211381 A1 EP 2211381A1
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EP
European Patent Office
Prior art keywords
layer
silicon
type
trench
substrate
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EP10150992A
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German (de)
French (fr)
Inventor
Patrick Poveda
Benjamin Morillon
Erwan Bruno
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STMicroelectronics Tours SAS
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STMicroelectronics Tours SAS
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Publication of EP2211381A1 publication Critical patent/EP2211381A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0814—Diodes only

Definitions

  • the present invention relates to electronic components formed in and on a semiconductor structure and isolated from each other. More particularly, the present invention relates to a structure in which parasitic capacitances between components and between component and substrate are reduced. The present invention also relates to a method of manufacturing such a structure.
  • the figure 1 illustrates one of these structures proposed by the applicant in the patent application published under the number FR 2 914 497 .
  • Two diodes D1 and D2 are formed side by side in an SOI type structure which comprises an N-type doped semiconductor layer formed on a semiconductor substrate 1 with the interposition of an insulating layer 3.
  • the diodes D1 and D2 are isolated laterally by insulating regions 5, for example silicon oxide, which pass through the semiconductor layer and join the insulating layer 3.
  • Each diode is thus formed in an N-type doped semiconductor casing 7 on the surface of which is formed a P-type doped region 9.
  • Each box 7 is surrounded (bottom, side walls and a portion of its upper surface) of a heavily doped N-type region (N + ).
  • Anode contact 13 and a cathode contact 15 are formed, respectively, on the regions 9 and 11 of the diode D1 and an anode contact 17 and a cathode contact 19 are formed, respectively, on the regions 9 and 9. 11 of the diode D2.
  • the layer 3 and the insulating regions 5 have, for example, thicknesses greater than 2 ⁇ m and allow the parasitic capacitances between the components and between the component and the substrate to be very small.
  • the figure 2 is an electrical diagram illustrating an example of a device for protecting a data transmission line 21 (I / O) against overvoltages.
  • the device of the figure 2 comprises two low capacitance diodes D1 and D2 and a protection diode DP.
  • Diode D2 has its cathode 19 connected to line 21 and its anode 17 connected to ground. When a negative overvoltage appears on the line 21, the diode D2 is forward biased and becomes conducting.
  • the diode D1 and the protection diode DP are placed in series in parallel with the diode D2.
  • the diode D1 has its anode 13 connected to line 21 and its cathode 15 connected to the cathode of the protective diode DP.
  • the anode of the DP protection diode is connected to ground.
  • this protection diode DP goes into avalanche and passes the current, the diode D1 is also forward biased.
  • protection diodes D1 and D2 may correspond to the diodes of the figure 1 and the protective diode DP can also be formed in a similar box.
  • SOI-type box structures have several disadvantages. SOI-type tranches are relatively expensive compared to massive tranches if one imposes particular characteristics on each element of the unit. In addition, to allow good vertical isolation, generally used slices comprising a thick buried oxide layer, which can cause significant deformation making the treatment of slices delicate during manufacturing operations.
  • An object of an embodiment of the present invention is to provide a low cost and space saving structure comprising electronic components isolated from each other.
  • Another object of an embodiment of the present invention is to provide a structure in which the capabilities parasites between components and between component and substrate are very low.
  • Another object of an embodiment of the present invention is to provide a method of manufacturing such a structure.
  • an embodiment of the present invention provides a structure comprising at least one electronic component formed in a semiconductor stack comprising a buried layer of highly doped silicon of a first type of conductivity extending over a silicon substrate with a low doping. a second type of conductivity and a vertical insulating trench surrounding the component, the penetrating trench, in the silicon substrate, below the silicon layer, to a depth greater than the thickness of the space charge area in the silicon substrate.
  • the silicon substrate is doped with a dopant concentration of less than 8.5 ⁇ 10 13 atoms / cm 3 and the buried silicon layer is doped with a dopant concentration greater than 10 19 atoms / cm 3 .
  • the space charge area has a thickness of between 1 ⁇ m and 3.3 ⁇ m.
  • the structure further comprises highly doped regions of the first conductivity type formed along the trench, above the heavily doped layer of the first conductivity type.
  • the insulating trench has insulated walls and is filled with polycrystalline silicon.
  • the electronic component is a diode formed in an upper silicon layer of the first conductivity type extending over the highly doped silicon layer of the first conductivity type.
  • the first type of conductivity is the type N.
  • the method further comprises a step of filling the trench with polycrystalline silicon.
  • the buried layer of highly doped silicon of the first conductivity type is formed by implantation / dopant diffusion at the surface of the silicon substrate and the upper silicon layer is formed by epitaxy on the layer of silicon. buried silicon.
  • the figure 3 illustrates a structure comprising electronic components insulated from each other according to an embodiment of the present invention.
  • FIG. 3 On a substrate 31 of P-type lightly doped silicon (P - ) are formed two caissons 33 of N type doped silicon. figure 3 , the electronic components shown are diodes, D1 and D2, but it will be understood that any electronic component can be formed in the wells 33.
  • a layer 35 of strongly doped silicon N (N + ) type is formed at the interface between the Boxes 33 and the substrate 31.
  • Highly doped N-type regions 37 extend on the side walls of boxes 33 and a portion of their upper surfaces.
  • Anode regions 39 of diodes D1 and D2, doped with type P, are formed on the surface of boxes 33. Boxes 33 are isolated laterally by insulating trenches 41 which penetrate into substrate 31.
  • the boxes 33 may have a thickness of about 10 microns and the heavily doped N-type layer 35 a thickness of about 5 microns.
  • the combination of the P-type lightly doped substrate 31 and the N-type heavily doped layer 35 forms a space charge region which extends deep into the substrate 31 due to the doping difference between these regions.
  • the limit of this space charge area is shown in dotted lines in figure 3 .
  • the doping of the layer 35 and the substrate 31 are provided so that the space charge area in the substrate 31 has a thickness greater than about 3 ⁇ m.
  • these dopings are relatively greater than 10 19 atoms / cm 3 for the layer 35 and less than 8.5 ⁇ 10 13 atoms / cm 3 for the substrate 31, for example between 8.10 12 atoms / cm 3 and 8.5 ⁇ 10 13 atoms / cm 3 .
  • a space charge area having a thickness of 8 ⁇ m equals, in terms of parasitic capacitance, a silicon oxide layer having a thickness of about 2.5 ⁇ m.
  • the permittivity of the intrinsic silicon is approximately equal to 3 times the permittivity of the silicon oxide.
  • the vertical isolation between component and substrate, formed by the structure of the figure 3 is equivalent to that of known structures on SOI substrate, without the use of such substrates.
  • Those skilled in the art will easily determine the doping of the layer 35 and the substrate 31 to obtain a space charge zone whose thickness is between 3 ⁇ m and 10 ⁇ m, such thickness being equivalent to a thickness of buried oxide of between 1 ⁇ m and 3.3 ⁇ m.
  • the trenches 41 penetrate the substrate 31 to a depth greater than the thickness of the space charge area in the substrate 31. This limits parasitic capacitances between two neighboring components formed in neighboring boxes 33. Indeed, if the insulating trenches 41 stop at the interface between the layer 35 and the substrate 31, high parasitic capacitances can be formed between two adjacent components, below the insulating trenches 41. The isolation between the caissons is then ineffective. The structure of the figure 3 avoids this, the trenches insulators 41 forming an obstacle to the creation of these parasitic capacitances.
  • This isolation has, in a known manner, the advantage of ensuring low parasitic capacitances between the components and of having a reduced bulk (less than the isolations per junction).
  • the boxes 33 are isolated from the substrate 31 by a junction which, unlike prejudices, produces effects identical to those produced by a buried oxide layer having a thickness of a few micrometers. The parasitic capacitances between component and substrate are thus reduced, without requiring the use of an expensive SOI structure that is susceptible to deformation.
  • FIGS. 4A to 4G illustrate results of steps of a method according to an embodiment of the present invention making it possible to obtain the structure of the figure 3 .
  • the Figure 4A is a P-type (P - ) lightly doped silicon substrate 31 on which a N-type (N + ) strongly doped silicon layer is formed.
  • the layer 35 may be formed, for example, by performing an implantation of arsenic or antimony, and have a thickness, after diffusion, of about 5 microns.
  • a thick layer 33 of N-type doped silicon On the layer 35 is formed, by epitaxy, a thick layer 33 of N-type doped silicon.
  • the substrate 31 can be doped with a dopant concentration of less than 1.5 ⁇ 10 13 atoms / cm 3 and the layer 35 at a dopant concentration of the order of 10 19 atoms / cm 3 .
  • the layer 33 may be doped with a dopant concentration of the order of 2.10 13 atoms / cm 3 and have a thickness of about 10 ⁇ m.
  • a mask 51 having openings through which trenches 53 are formed in the upper silicon layer is formed on the surface of the silicon layer 33, to form silicon boxes 33.
  • the mask 51 may be, for example , in silicon oxide or silicon nitride.
  • the trenches 53 resulting for example from a plasma etching, stop in the layer of In fact, the silicon layer 35 having a thickness of a few microns, it allows a stop of the etching so that the dispersion in depth of the etching is not critical.
  • the trenches 53 may have a width of between 1 and 2 ⁇ m.
  • a predeposit 37 of POCl 3 has been formed on the walls of the trenches 53, which makes it possible, during a subsequent annealing step, to form regions heavily doped with phosphorus (type N) on the walls of the caissons 33. optionally subsequently deoxidizing to remove the oxide formed on the surface of the walls of the trenches 53.
  • a new plasma etching is performed to increase the depth of the trenches 53 so that they pass through the strongly-doped N-type silicon layer 35 and penetrate into the P-type lightly doped substrate 31.
  • This step is carried out at Using the mask 51, an annealing is then carried out whereby the POCl 3 can be diffused in the silicon boxes 33 to form strongly doped N-type regions 37 on the top of the walls of the trenches 53, in the wells 33. It will be noted that the annealing can be done before the step of the figure 4D deep trench formation.
  • the trenches 53 can penetrate into the silicon substrate 31 to a depth of between about 10 ⁇ m and about 15 ⁇ m, as described above.
  • a thin insulating layer 43 has been formed on the walls and the bottom of the trenches 53, for example by thermal oxidation, to form a silicon oxide layer 43.
  • the trenches 53 were filled with polycrystalline silicon or any other material 45 having good trenching properties 53, for example an oxide.
  • the mask 51 is then removed.
  • diodes D1 and D2 identical to that of the figure 3 , which comprise P-doped regions 39 formed on the surface of each of the caissons 33.
  • the regions 39 form the anodes of the diodes D1 and D2.
  • contacts 57 and 59 are respectively taken on the cathode 37 and anode regions 39 of the diodes D1 and D2.
  • Highly doped N-type regions can be formed at the surface of wells 33, at regions 37, to aid in the formation of cathode contacts 59.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The structure has an electronic component i.e. diode, formed in a semiconductor stack. The stack has an N-type heavily doped silicon layer (35) extending on a P-type lightly doped silicon substrate (31). Insulating trenches (41) surround the component, and are filled with polycrystalline silicon. The trenches are penetrated in the substrate to a depth greater than a thickness of a space charge zone in the substrate below the layer, where the thickness ranges between 1 and 3.3 micrometers. N-type doped silicon boxes (33) are formed on and insulated from the substrate by a junction. An independent claim is also included for a method for manufacturing a semiconductor structure containing an electronic component.

Description

Domaine de l'inventionField of the invention

La présente invention concerne des composants électroniques formés dans et sur une structure semiconductrice et isolés entre eux. Plus particulièrement, la présente invention concerne une structure dans laquelle les capacités parasites entre composants et entre composant et substrat sont réduites. La présente invention concerne également un procédé de fabrication d'une telle structure.The present invention relates to electronic components formed in and on a semiconductor structure and isolated from each other. More particularly, the present invention relates to a structure in which parasitic capacitances between components and between component and substrate are reduced. The present invention also relates to a method of manufacturing such a structure.

Exposé de l'art antérieurPresentation of the prior art

De façon classique, des composants électroniques formés dans et sur un substrat semiconducteur, par exemple des composants de puissance, sont isolés, en surface de l'empilement, par des jonctions PN. Si le substrat est de type N, des régions P isolent latéralement les composants électroniques les uns des autres. Ce type d'isolement présente l'inconvénient de consommer une surface importante pour être efficace. En effet, la largeur de la région P est au moins égale à deux fois sa profondeur. De plus, on considère généralement qu'un isolement par jonction PN n'est pas optimal du point de vue des capacités parasites entre composant et substrat.Conventionally, electronic components formed in and on a semiconductor substrate, for example power components, are isolated at the surface of the stack by PN junctions. If the substrate is N-type, P regions laterally isolate the electronic components from each other. This type of isolation has the disadvantage of consuming a large area to be effective. Indeed, the width of the region P is at least twice its depth. In addition, it is generally considered that isolation by PN junction is not optimal from the point of view of parasitic capacitances between component and substrate.

Ainsi, pour limiter la surface occupée et réduire les capacités parasites, il a été proposé de former des composants électroniques dans et sur des substrats de type silicium sur isolant (SOI) et d'isoler les composants entre eux à l'aide de matériaux diélectriques.Thus, in order to limit the area occupied and to reduce parasitic capacitances, it has been proposed to form electronic components in and on silicon-on-insulator (SOI) substrates and to isolate the components between them using dielectric materials. .

La figure 1 illustre une de ces structures proposée par la demanderesse dans la demande de brevet publiée sous le numéro FR 2 914 497 . Deux diodes D1 et D2 sont formées côte à côte dans une structure de type SOI qui comprend une couche semiconductrice dopée de type N formée sur un substrat semiconducteur 1 avec interposition d'une couche isolante 3. Les diodes D1 et D2 sont isolées latéralement par des régions isolantes 5, par exemple en oxyde de silicium, qui traversent la couche semiconductrice et rejoignent la couche isolante 3. Chaque diode est ainsi réalisée dans un caisson semiconducteur 7 dopé de type N en surface duquel est formée une région 9 dopée de type P. Chaque caisson 7 est entouré (fond, parois latérales et une partie de sa surface supérieure) d'une région 11 fortement dopée de type N (N+). Un contact d'anode 13 et un contact de cathode 15 sont formés, respectivement, sur les régions 9 et 11 de la diode D1 et un contact d'anode 17 et un contact de cathode 19 sont formés, respectivement, sur les régions 9 et 11 de la diode D2. La couche 3 et les régions isolantes 5 ont par exemple des épaisseurs supérieures à 2 µm et permettent que les capacités parasites entre composants et entre composant et substrat soient très faibles.The figure 1 illustrates one of these structures proposed by the applicant in the patent application published under the number FR 2 914 497 . Two diodes D1 and D2 are formed side by side in an SOI type structure which comprises an N-type doped semiconductor layer formed on a semiconductor substrate 1 with the interposition of an insulating layer 3. The diodes D1 and D2 are isolated laterally by insulating regions 5, for example silicon oxide, which pass through the semiconductor layer and join the insulating layer 3. Each diode is thus formed in an N-type doped semiconductor casing 7 on the surface of which is formed a P-type doped region 9. Each box 7 is surrounded (bottom, side walls and a portion of its upper surface) of a heavily doped N-type region (N + ). Anode contact 13 and a cathode contact 15 are formed, respectively, on the regions 9 and 11 of the diode D1 and an anode contact 17 and a cathode contact 19 are formed, respectively, on the regions 9 and 9. 11 of the diode D2. The layer 3 and the insulating regions 5 have, for example, thicknesses greater than 2 μm and allow the parasitic capacitances between the components and between the component and the substrate to be very small.

La figure 2 est un schéma électrique illustrant un exemple d'un dispositif de protection d'une ligne de transmission de données 21 (I/O) contre des surtensions. Le dispositif de la figure 2 comprend deux diodes faible capacité D1 et D2 et une diode de protection DP. La diode D2 a sa cathode 19 connectée à la ligne 21 et son anode 17 connectée à la masse. Lorsqu'une surtension négative apparaît sur la ligne 21, la diode D2 est polarisée en direct et devient passante. La diode D1 et la diode de protection DP sont placées, en série, en parallèle de la diode D2. La diode D1 a son anode 13 connectée à la ligne 21 et sa cathode 15 connectée à la cathode de la diode de protection DP. L'anode de la diode de protection DP est connectée à la masse. Lorsqu'une surtension positive supérieure à la tension d'avalanche de la diode de protection DP apparaît sur la ligne 21, cette diode de protection DP entre en avalanche et laisse passer le courant, la diode D1 étant également polarisée en direct.The figure 2 is an electrical diagram illustrating an example of a device for protecting a data transmission line 21 (I / O) against overvoltages. The device of the figure 2 comprises two low capacitance diodes D1 and D2 and a protection diode DP. Diode D2 has its cathode 19 connected to line 21 and its anode 17 connected to ground. When a negative overvoltage appears on the line 21, the diode D2 is forward biased and becomes conducting. The diode D1 and the protection diode DP are placed in series in parallel with the diode D2. The diode D1 has its anode 13 connected to line 21 and its cathode 15 connected to the cathode of the protective diode DP. The anode of the DP protection diode is connected to ground. When a positive overvoltage greater than the avalanche voltage of the protective diode DP appears on the line 21, this protection diode DP goes into avalanche and passes the current, the diode D1 is also forward biased.

On souhaite généralement que les circuits de protection contre les surtensions tels que celui de la figure 2 affectent le moins possible les signaux circulant dans la ligne. Pour cela, il est nécessaire que les capacités parasites liées au circuit de protection soient les plus faibles possibles. Ainsi, les diodes de protection D1 et D2 peuvent correspondre aux diodes de la figure 1 et la diode de protection DP peut également être formée dans un caisson similaire.It is generally desired that overvoltage protection circuits such as that of the figure 2 affect the signals flowing in the line as little as possible. For this, it is necessary that the parasitic capacitances related to the protection circuit are the lowest possible. Thus, the protection diodes D1 and D2 may correspond to the diodes of the figure 1 and the protective diode DP can also be formed in a similar box.

Cependant, des structures à caissons de type SOI ont plusieurs inconvénients. Les tranches de type SOI coûtent relativement cher par rapport aux tranches massives si on impose des caractéristiques particulières à chacun des éléments de la tranche. De plus, pour permettre un bon isolement vertical, on utilise généralement des tranches comprenant une couche d'oxyde enterrée épaisse, ce qui peut provoquer une déformation importante rendant le traitement des tranches délicat lors des opérations de fabrication.However, SOI-type box structures have several disadvantages. SOI-type tranches are relatively expensive compared to massive tranches if one imposes particular characteristics on each element of the unit. In addition, to allow good vertical isolation, generally used slices comprising a thick buried oxide layer, which can cause significant deformation making the treatment of slices delicate during manufacturing operations.

Ainsi, un besoin existe d'une structure permettant l'isolement entre des composants électroniques, qui soit relativement peu coûteuse, à faible encombrement, et qui limite les capacités parasites entre composants et entre composant et substrat.Thus, there is a need for a structure for isolation between electronic components, which is relatively inexpensive, compact, and which limits parasitic capacitances between components and between component and substrate.

Résumésummary

Un objet d'un mode de réalisation de la présente invention est de prévoir une structure à faible coût et peu encombrante comprenant des composants électroniques isolés entre eux.An object of an embodiment of the present invention is to provide a low cost and space saving structure comprising electronic components isolated from each other.

Un autre objet d'un mode de réalisation de la présente invention est de prévoir une structure dans laquelle les capacités parasites entre composants et entre composant et substrat sont très faibles.Another object of an embodiment of the present invention is to provide a structure in which the capabilities parasites between components and between component and substrate are very low.

Un autre objet d'un mode de réalisation de la présente invention est de prévoir un procédé de fabrication d'une telle structure.Another object of an embodiment of the present invention is to provide a method of manufacturing such a structure.

Ainsi, un mode de réalisation de la présente invention prévoit une structure comprenant au moins un composant électronique formé dans un empilement semiconducteur comprenant une couche enterrée de silicium fortement dopé d'un premier type de conductivité s'étendant sur un substrat de silicium faiblement dopé d'un second type de conductivité et une tranchée isolante verticale entourant le composant, la tranchée pénétrant, dans le substrat de silicium, en dessous de la couche de silicium, sur une profondeur supérieure à l'épaisseur de la zone de charge d'espace dans le substrat de silicium.Thus, an embodiment of the present invention provides a structure comprising at least one electronic component formed in a semiconductor stack comprising a buried layer of highly doped silicon of a first type of conductivity extending over a silicon substrate with a low doping. a second type of conductivity and a vertical insulating trench surrounding the component, the penetrating trench, in the silicon substrate, below the silicon layer, to a depth greater than the thickness of the space charge area in the silicon substrate.

Selon un mode de réalisation de la présente invention, le substrat de silicium est dopé à une concentration de dopants inférieure à 8,5.1013 atomes/cm3 et la couche de silicium enterrée est dopée à une concentration de dopants supérieure à 1019 atomes/cm3.According to one embodiment of the present invention, the silicon substrate is doped with a dopant concentration of less than 8.5 × 10 13 atoms / cm 3 and the buried silicon layer is doped with a dopant concentration greater than 10 19 atoms / cm 3 .

Selon un mode de réalisation de la présente invention, la zone de charge d'espace a une épaisseur comprise entre 1 µm et 3,3 µm.According to one embodiment of the present invention, the space charge area has a thickness of between 1 μm and 3.3 μm.

Selon un mode de réalisation de la présente invention, la structure comprend en outre des régions fortement dopées du premier type de conductivité formées le long de la tranchée, au-dessus de la couche fortement dopée du premier type de conductivité.According to one embodiment of the present invention, the structure further comprises highly doped regions of the first conductivity type formed along the trench, above the heavily doped layer of the first conductivity type.

Selon un mode de réalisation de la présente invention, la tranchée isolante a des parois isolées et est remplie de silicium polycristallin.According to one embodiment of the present invention, the insulating trench has insulated walls and is filled with polycrystalline silicon.

Selon un mode de réalisation de la présente invention, le composant électronique est une diode formée dans une couche de silicium supérieure du premier type de conductivité s'étendant sur la couche de silicium fortement dopé du premier type de conductivité.According to an embodiment of the present invention, the electronic component is a diode formed in an upper silicon layer of the first conductivity type extending over the highly doped silicon layer of the first conductivity type.

Selon un mode de réalisation de la présente invention, le premier type de conductivité est le type N.According to one embodiment of the present invention, the first type of conductivity is the type N.

Un mode de réalisation de la présente invention prévoit en outre un procédé de fabrication d'une structure semiconductrice destinée à contenir un composant électronique, comprenant les étapes successives suivante :

  • former une couche de silicium supérieure s'étendant sur un substrat de silicium faiblement dopé d'un second type de conductivité avec interposition d'une couche enterrée de silicium fortement dopé du premier type de conductivité ;
  • réaliser une tranchée, selon le contour du composant, dans la couche de silicium supérieure ;
  • doper, du premier type de conductivité, les parois de la couche de silicium supérieure à partir de la tranchée ;
  • prolonger la tranchée dans le substrat de silicium, sur une profondeur supérieure à l'épaisseur de la zone de charge d'espace dans le substrat de silicium ; et
  • former, sur les parois et le fond de la tranchée, une couche isolante.
An embodiment of the present invention further provides a method of manufacturing a semiconductor structure for containing an electronic component, comprising the following steps:
  • forming an upper silicon layer extending over a lightly doped silicon substrate of a second conductivity type with the interposition of a buried layer of highly doped silicon of the first conductivity type;
  • make a trench, according to the contour of the component, in the upper silicon layer;
  • doping, of the first type of conductivity, the walls of the upper silicon layer from the trench;
  • extending the trench in the silicon substrate to a depth greater than the thickness of the space charge region in the silicon substrate; and
  • form, on the walls and the bottom of the trench, an insulating layer.

Selon un mode de réalisation de la présente invention, le procédé comprend en outre une étape de comblement de la tranchée par du silicium polycristallin.According to one embodiment of the present invention, the method further comprises a step of filling the trench with polycrystalline silicon.

Selon un mode de réalisation de la présente invention, la couche enterrée de silicium fortement dopé du premier type de conductivité est formée par implantation/diffusion de dopants en surface du substrat de silicium et la couche de silicium supérieure est formée par épitaxie sur la couche de silicium enterrée.According to one embodiment of the present invention, the buried layer of highly doped silicon of the first conductivity type is formed by implantation / dopant diffusion at the surface of the silicon substrate and the upper silicon layer is formed by epitaxy on the layer of silicon. buried silicon.

Brève description des dessinsBrief description of the drawings

Ces objets, caractéristiques et avantages, ainsi que d'autres seront exposés en détail dans la description suivante de modes de réalisation particuliers faite à titre non-limitatif en relation avec les figures jointes parmi desquelles :

  • la figure 1, précédemment décrite, illustre une structure connue comprenant des composants électroniques isolés entre eux ;
  • la figure 2, précédemment décrite, illustre un exemple de circuit connu de protection d'une ligne de transmission de données contre des surtensions ;
  • la figure 3 illustre une structure comprenant des composants électroniques isolés entre eux selon un mode de réalisation de la présente invention ; et
  • les figures 4A à 4G illustrent des résultats d'étapes d'un procédé de fabrication de la structure de la figure 3 selon un mode de réalisation de la présente invention.
These and other objects, features, and advantages will be set forth in detail in the following description of particular embodiments made in a non-limiting manner in connection with the accompanying figures among which:
  • the figure 1 , previously described, illustrates a known structure comprising electronic components isolated from each other;
  • the figure 2 , previously described, illustrates an example of a known circuit for protecting a data transmission line against overvoltages;
  • the figure 3 illustrates a structure comprising electronic components insulated from each other according to an embodiment of the present invention; and
  • the Figures 4A to 4G illustrate results of steps in a manufacturing process of the structure of the figure 3 according to an embodiment of the present invention.

Par souci de clarté, de mêmes éléments ont été désignés par de mêmes références aux différentes figures et, de plus, comme cela est habituel dans la représentation des circuits intégrés, les diverses figures ne sont pas tracées à l'échelle.For the sake of clarity, the same elements have been designated by the same references in the various figures and, moreover, as is customary in the representation of the integrated circuits, the various figures are not drawn to scale.

Description détailléedetailed description

La figure 3 illustre une structure comprenant des composants électroniques isolés entre eux selon un mode de réalisation de la présente invention.The figure 3 illustrates a structure comprising electronic components insulated from each other according to an embodiment of the present invention.

Sur un substrat 31 de silicium faiblement dopé de type P (P-) sont formés deux caissons 33 de silicium dopé de type N. En figure 3, les composants électroniques représentés sont des diodes, D1 et D2, mais on comprendra que tout composant électronique pourra être formé dans les caissons 33. Une couche 35 de silicium fortement dopé de type N (N+) est formée à l'interface entre les caissons 33 et le substrat 31. Des régions 37 fortement dopées de type N s'étendent sur les parois latérales des caissons 33 et sur une partie de leurs surfaces supérieures. Des régions d'anode 39 des diodes D1 et D2, dopées de type P, sont formées en surface des caissons 33. Les caissons 33 sont isolés latéralement par des tranchées isolantes 41 qui pénètrent dans le substrat 31. Dans l'exemple représenté, les parois et le fond des tranchées 41 sont recouverts d'une couche isolante 43, par exemple en oxyde de silicium, et l'espace restant dans les tranchées 41 est rempli de silicium polycristallin 45 ou de tout autre matériau permettant le comblement de cet espace. A titre d'exemple de valeurs numériques, les caissons 33 peuvent avoir une épaisseur d'environ 10 µm et la couche 35 fortement dopée de type N une épaisseur d'environ 5 µm.On a substrate 31 of P-type lightly doped silicon (P - ) are formed two caissons 33 of N type doped silicon. figure 3 , the electronic components shown are diodes, D1 and D2, but it will be understood that any electronic component can be formed in the wells 33. A layer 35 of strongly doped silicon N (N + ) type is formed at the interface between the Boxes 33 and the substrate 31. Highly doped N-type regions 37 extend on the side walls of boxes 33 and a portion of their upper surfaces. Anode regions 39 of diodes D1 and D2, doped with type P, are formed on the surface of boxes 33. Boxes 33 are isolated laterally by insulating trenches 41 which penetrate into substrate 31. In the example shown, the The walls and the bottom of the trenches 41 are covered with an insulating layer 43, for example made of silicon oxide, and the space remaining in the trenches 41 is filled with polycrystalline silicon 45 or with any other material making it possible to fill this space. As an example of numerical values, the boxes 33 may have a thickness of about 10 microns and the heavily doped N-type layer 35 a thickness of about 5 microns.

L'association du substrat 31 faiblement dopé de type P et de la couche 35 fortement dopée de type N forme une zone de charge d'espace qui s'étend profondément dans le substrat 31, du fait de la différence de dopage entre ces régions. La limite de cette zone de charge d'espace est représentée en pointillés en figure 3. Les dopages de la couche 35 et du substrat 31 sont prévus de façon que la zone de charge d'espace dans le substrat 31 ait une épaisseur supérieure à environ 3 µm. Par exemple, ces dopages sont relativement supérieur à 1019 atomes/cm3 pour la couche 35 et inférieur à 8,5.1013 atomes/cm3 pour le substrat 31, par exemple compris entre 8.1012 atomes/cm3 et 8,5.1013 atomes/cm3. Une zone de charge d'espace ayant une épaisseur de 8 µm équivaut, en terme de capacité parasite, à une couche d'oxyde de silicium ayant une épaisseur d'environ 2,5 µm. En effet, la permittivité du silicium intrinsèque est environ égale à 3 fois la permittivité de l'oxyde de silicium. Ainsi, l'isolement vertical entre composant et substrat, formé par la structure de la figure 3, est équivalent à celui des structures connues sur substrat SOI, sans utilisation de tels substrats. L'homme de l'art déterminera aisément les dopages de la couche 35 et du substrat 31 pour obtenir une zone de charge d'espace dont l'épaisseur est comprise entre 3 µm et 10 µm, une telle épaisseur étant équivalente à une épaisseur d'oxyde enterré comprise entre 1 µm et 3,3 µm.The combination of the P-type lightly doped substrate 31 and the N-type heavily doped layer 35 forms a space charge region which extends deep into the substrate 31 due to the doping difference between these regions. The limit of this space charge area is shown in dotted lines in figure 3 . The doping of the layer 35 and the substrate 31 are provided so that the space charge area in the substrate 31 has a thickness greater than about 3 μm. For example, these dopings are relatively greater than 10 19 atoms / cm 3 for the layer 35 and less than 8.5 × 10 13 atoms / cm 3 for the substrate 31, for example between 8.10 12 atoms / cm 3 and 8.5 × 10 13 atoms / cm 3 . A space charge area having a thickness of 8 μm equals, in terms of parasitic capacitance, a silicon oxide layer having a thickness of about 2.5 μm. Indeed, the permittivity of the intrinsic silicon is approximately equal to 3 times the permittivity of the silicon oxide. Thus, the vertical isolation between component and substrate, formed by the structure of the figure 3 , is equivalent to that of known structures on SOI substrate, without the use of such substrates. Those skilled in the art will easily determine the doping of the layer 35 and the substrate 31 to obtain a space charge zone whose thickness is between 3 μm and 10 μm, such thickness being equivalent to a thickness of buried oxide of between 1 μm and 3.3 μm.

Les tranchées 41 pénètrent dans le substrat 31 sur une profondeur supérieure à l'épaisseur de la zone de charge d'espace dans le substrat 31. Ceci permet de limiter les capacités parasites entre deux composants voisins formés dans des caissons 33 voisins. En effet, si les tranchées isolantes 41 s'arrêtent à l'interface entre la couche 35 et le substrat 31, des capacités parasites élevées peuvent se former entre deux composants voisins, en dessous des tranchées isolantes 41. L'isolement entre les caissons est alors inefficace. La structure de la figure 3 permet d'éviter cela, les tranchées isolantes 41 formant un obstacle à la création de ces capacités parasites.The trenches 41 penetrate the substrate 31 to a depth greater than the thickness of the space charge area in the substrate 31. This limits parasitic capacitances between two neighboring components formed in neighboring boxes 33. Indeed, if the insulating trenches 41 stop at the interface between the layer 35 and the substrate 31, high parasitic capacitances can be formed between two adjacent components, below the insulating trenches 41. The isolation between the caissons is then ineffective. The structure of the figure 3 avoids this, the trenches insulators 41 forming an obstacle to the creation of these parasitic capacitances.

Ainsi, on obtient une structure isolée latéralement par une tranchée isolante 41. Cet isolement a, de façon connue, l'avantage d'assurer des capacités parasites faibles entre les composants et d'avoir un encombrement réduit (inférieur aux isolements par jonction). De plus, les caissons 33 sont isolés du substrat 31 par une jonction qui, contrairement aux préjugés, produit des effets identiques à ceux produits par une couche d'oxyde enterrée ayant une épaisseur de quelques micromètres. On réduit ainsi les capacités parasites entre composant et substrat, sans nécessiter l'utilisation d'une structure SOI coûteuse et susceptible de subir des déformations.Thus, a structure isolated laterally by an insulating trench 41 is obtained. This isolation has, in a known manner, the advantage of ensuring low parasitic capacitances between the components and of having a reduced bulk (less than the isolations per junction). In addition, the boxes 33 are isolated from the substrate 31 by a junction which, unlike prejudices, produces effects identical to those produced by a buried oxide layer having a thickness of a few micrometers. The parasitic capacitances between component and substrate are thus reduced, without requiring the use of an expensive SOI structure that is susceptible to deformation.

Les figures 4A à 4G illustrent des résultats d'étapes d'un procédé selon un mode de réalisation de la présente invention permettant d'obtenir la structure de la figure 3.The Figures 4A to 4G illustrate results of steps of a method according to an embodiment of the present invention making it possible to obtain the structure of the figure 3 .

La figure 4A représente un substrat de silicium 31 faiblement dopé de type P (P-) sur lequel est formée une couche de silicium 35 fortement dopé de type N (N+). La couche 35 peut être formée, par exemple, en réalisant une implantation d'arsenic ou d'antimoine, et avoir une épaisseur, après diffusion, d'environ 5 µm. Sur la couche 35 est formée, par épitaxie, une couche épaisse 33 de silicium dopé de type N. A titre d'exemple, le substrat 31 peut être dopé à une concentration de dopants inférieure à 1,5.1013 atomes/cm3 et la couche 35 à une concentration de dopants de l'ordre de 1019 atomes/cm3. La couche 33 peut être dopée à une concentration de dopants de l'ordre de 2.1013 atomes/cm3 et avoir une épaisseur d'environ 10 µm.The Figure 4A is a P-type (P - ) lightly doped silicon substrate 31 on which a N-type (N + ) strongly doped silicon layer is formed. The layer 35 may be formed, for example, by performing an implantation of arsenic or antimony, and have a thickness, after diffusion, of about 5 microns. On the layer 35 is formed, by epitaxy, a thick layer 33 of N-type doped silicon. By way of example, the substrate 31 can be doped with a dopant concentration of less than 1.5 × 10 13 atoms / cm 3 and the layer 35 at a dopant concentration of the order of 10 19 atoms / cm 3 . The layer 33 may be doped with a dopant concentration of the order of 2.10 13 atoms / cm 3 and have a thickness of about 10 μm.

A l'étape illustrée en figure 4B, on a formé, en surface de la couche de silicium 33, un masque 51 comprenant des ouvertures au travers desquelles on forme des tranchées 53 dans la couche de silicium supérieure pour former des caissons de silicium 33. Le masque 51 peut être, par exemple, en oxyde de silicium ou en nitrure de silicium. Les tranchées 53, résultant par exemple d'une gravure plasma, s'arrêtent dans la couche de silicium fortement dopé 35. En effet, la couche de silicium 35 ayant une épaisseur de quelques micromètres, elle permet un arrêt de la gravure de telle façon que la dispersion en profondeur de la gravure ne soit pas critique. A titre d'exemple de valeurs numériques, les tranchées 53 peuvent avoir une largeur comprise entre 1 et 2 µm.At the step illustrated in Figure 4B a mask 51 having openings through which trenches 53 are formed in the upper silicon layer is formed on the surface of the silicon layer 33, to form silicon boxes 33. The mask 51 may be, for example , in silicon oxide or silicon nitride. The trenches 53, resulting for example from a plasma etching, stop in the layer of In fact, the silicon layer 35 having a thickness of a few microns, it allows a stop of the etching so that the dispersion in depth of the etching is not critical. As an example of numerical values, the trenches 53 may have a width of between 1 and 2 μm.

A l'étape illustrée en figure 4C, on a formé, sur les parois des tranchées 53, un prédépôt 37 de POCl3 permettant, lors d'une étape ultérieure de recuit, la formation de régions fortement dopées au phosphore (type N) sur les parois des caissons 33. On peut éventuellement ensuite réaliser une désoxydation pour éliminer l'oxyde formé en surface des parois des tranchées 53.At the step illustrated in figure 4C a predeposit 37 of POCl 3 has been formed on the walls of the trenches 53, which makes it possible, during a subsequent annealing step, to form regions heavily doped with phosphorus (type N) on the walls of the caissons 33. optionally subsequently deoxidizing to remove the oxide formed on the surface of the walls of the trenches 53.

A l'étape illustrée en figure 4D, on procède à une nouvelle gravure plasma pour augmenter la profondeur des tranchées 53 pour que celles-ci traversent la couche de silicium 35 fortement dopé de type N et pénètrent dans le substrat 31 faiblement dopé de type P. Cette étape est réalisée à l'aide du masque 51. On réalise ensuite un recuit permettant au POCl3 de diffuser dans les caissons de silicium 33 pour former des régions 37 fortement dopées de type N sur le haut des parois des tranchées 53, dans les caissons 33. On notera que le recuit pourra être réalisé avant l'étape de la figure 4D de formation de tranchées 53 profondes. A titre d'exemple, les tranchées 53 peuvent pénétrer dans le substrat 31 de silicium sur une profondeur comprise entre environ 10 µm et environ 15 µm, comme cela a été décrit ci-dessus.At the step illustrated in figure 4D , a new plasma etching is performed to increase the depth of the trenches 53 so that they pass through the strongly-doped N-type silicon layer 35 and penetrate into the P-type lightly doped substrate 31. This step is carried out at Using the mask 51, an annealing is then carried out whereby the POCl 3 can be diffused in the silicon boxes 33 to form strongly doped N-type regions 37 on the top of the walls of the trenches 53, in the wells 33. It will be noted that the annealing can be done before the step of the figure 4D deep trench formation. By way of example, the trenches 53 can penetrate into the silicon substrate 31 to a depth of between about 10 μm and about 15 μm, as described above.

A l'étape illustrée en figure 4E, on a formé une fine couche isolante 43 sur les parois et le fond des tranchées 53, par exemple par oxydation thermique, pour former une couche d'oxyde de silicium 43.At the step illustrated in figure 4E a thin insulating layer 43 has been formed on the walls and the bottom of the trenches 53, for example by thermal oxidation, to form a silicon oxide layer 43.

A l'étape illustrée en figure 4F, on a rempli les tranchées 53 de silicium polycristallin ou de tout autre matériau 45 ayant de bonnes propriétés de comblement des tranchées 53, par exemple un oxyde. Le masque 51 est ensuite retiré.At the step illustrated in figure 4F the trenches 53 were filled with polycrystalline silicon or any other material 45 having good trenching properties 53, for example an oxide. The mask 51 is then removed.

A l'étape illustrée en figure 4G, on a formé des composants électroniques dans les caissons 33, dans l'exemple représenté des diodes D1 et D2 identiques à celle de la figure 3, qui comprennent des régions 39 dopées de type P formées en surface de chacun des caissons 33. Les régions 39 forment les anodes des diodes D1 et D2. Dans l'exemple représenté, des contacts 57 et 59 sont pris, respectivement, sur les régions de cathode 37 et d'anode 39 des diodes D1 et D2. Des régions fortement dopées de type N peuvent être formées en surface des caissons 33, au niveau des régions 37, pour aider à la formation des contacts de cathode 59.At the step illustrated in figure 4G , electronic components were formed in the boxes 33, in the example represented diodes D1 and D2 identical to that of the figure 3 , which comprise P-doped regions 39 formed on the surface of each of the caissons 33. The regions 39 form the anodes of the diodes D1 and D2. In the example shown, contacts 57 and 59 are respectively taken on the cathode 37 and anode regions 39 of the diodes D1 and D2. Highly doped N-type regions can be formed at the surface of wells 33, at regions 37, to aid in the formation of cathode contacts 59.

Des modes de réalisation particuliers de la présente invention ont été décrits. Diverses variantes et modifications apparaîtront à l'homme de l'art. En particulier, on notera que les composants décrits ici ne sont que des exemples et que l'on pourra former d'autres composants dans les caissons isolés 33, par exemple des diodes de protection ou d'autres composants électroniques, par exemple des composants de puissance haute fréquence.Particular embodiments of the present invention have been described. Various variations and modifications will be apparent to those skilled in the art. In particular, it will be noted that the components described here are only examples and that other components may be formed in the insulated boxes 33, for example protective diodes or other electronic components, for example components of high frequency power.

On notera également que l'on pourra concevoir des structures similaires à celles présentées ici en inversant tous les types de conductivité et les types de dopage.It will also be appreciated that structures similar to those presented herein can be designed by inverting all types of conductivity and types of doping.

Claims (10)

Structure comprenant au moins un composant électronique formé dans un empilement semiconducteur comprenant une couche enterrée de silicium fortement dopé d'un premier type de conductivité (35) s'étendant sur un substrat de silicium faiblement dopé d'un second type de conductivité (31) et une tranchée isolante verticale (41) entourant le composant, caractérisée en ce que la tranchée (41) pénètre dans le substrat de silicium (31), en dessous de la couche de silicium (35), sur une profondeur supérieure à l'épaisseur de la zone de charge d'espace dans le substrat de silicium (31).A structure comprising at least one electronic component formed in a semiconductor stack comprising a buried layer of highly doped silicon of a first conductivity type (35) extending over a lightly doped silicon substrate of a second conductivity type (31) and a vertical insulating trench (41) surrounding the component, characterized in that the trench (41) penetrates the silicon substrate (31), below the silicon layer (35), to a depth greater than the thickness the space charge area in the silicon substrate (31). Structure selon la revendication 1, dans laquelle le substrat de silicium (31) est dopé à une concentration de dopants inférieure à 8,5.1013 atomes/cm3 et la couche de silicium enterrée (35) est dopée à une concentration de dopants supérieure à 1019 atomes/cm3.The structure of claim 1 wherein the silicon substrate (31) is doped at a dopant concentration of less than 8.5 x 10 13 atoms / cm 3 and the buried silicon layer (35) is doped at a dopant concentration greater than 10 19 atoms / cm 3 . Structure selon la revendication 1 ou 2, dans laquelle ladite zone de charge d'espace a une épaisseur comprise entre 1 µm et 3,3 µm.The structure of claim 1 or 2, wherein said space charge area has a thickness of between 1 μm and 3.3 μm. Structure selon l'une quelconque des revendications 1 à 3, comprenant en outre des régions fortement dopées du premier type de conductivité (37) formées le long de la tranchée (41), au-dessus de la couche fortement dopée du premier type de conductivité (35).The structure of any one of claims 1 to 3, further comprising highly doped regions of the first conductivity type (37) formed along the trench (41), above the highly doped layer of the first conductivity type (35). Structure selon l'une quelconque des revendications 1 à 4, dans laquelle la tranchée isolante (41) a des parois isolées et est remplie de silicium polycristallin.Structure according to any one of claims 1 to 4, wherein the insulating trench (41) has insulated walls and is filled with polycrystalline silicon. Structure selon l'une quelconque des revendications 1 à 5, dans laquelle le composant électronique est une diode (D1, D2) formée dans une couche de silicium supérieure (33) du premier type de conductivité s'étendant sur la couche de silicium fortement dopé du premier type de conductivité (35).Structure according to any one of claims 1 to 5, wherein the electronic component is a diode (D1, D2) formed in an upper silicon layer (33) of the first conductivity type extending over the heavily doped silicon layer of the first type of conductivity (35). Structure selon l'une quelconque des revendications 1 à 6, dans laquelle le premier type de conductivité est le type N.Structure according to any one of claims 1 to 6, wherein the first type of conductivity is type N. Procédé de fabrication d'une structure semiconductrice destinée à contenir un composant électronique (D1, D2), comprenant les étapes successives suivante : former une couche de silicium supérieure (33) s'étendant sur un substrat de silicium (31) faiblement dopé d'un second type de conductivité avec interposition d'une couche enterrée de silicium fortement dopé (35) du premier type de conductivité ; réaliser une tranchée (53), selon le contour du composant, dans la couche de silicium supérieure (33) ; doper, du premier type de conductivité, les parois de la couche de silicium supérieure à partir de la tranchée (53) ; prolonger la tranchée (53) dans le substrat de silicium (31), sur une profondeur supérieure à l'épaisseur de la zone de charge d'espace dans le substrat de silicium (31) ; et former, sur les parois et le fond de la tranchée (53), une couche isolante (43). A method of manufacturing a semiconductor structure for containing an electronic component (D1, D2), comprising the following steps: forming an upper silicon layer (33) extending over a low doped silicon substrate (31) of a second conductivity type with interposition of a deep doped silicon buried layer (35) of the first conductivity type; making a trench (53), according to the contour of the component, in the upper silicon layer (33); doping, of the first type of conductivity, the walls of the upper silicon layer from the trench (53); extending the trench (53) in the silicon substrate (31) to a depth greater than the thickness of the space charge region in the silicon substrate (31); and forming, on the walls and the bottom of the trench (53), an insulating layer (43). Procédé selon la revendication 8, comprenant en outre une étape de comblement de la tranchée (53) par du silicium polycristallin (45).The method of claim 8, further comprising a step of filling the trench (53) with polycrystalline silicon (45). Procédé selon la revendication 8 ou 9, dans lequel la couche enterrée de silicium fortement dopé (35) du premier type de conductivité est formée par implantation/diffusion de dopants en surface du substrat de silicium (31) et dans lequel la couche de silicium supérieure (33) est formée par épitaxie sur la couche de silicium enterrée (35).A method according to claim 8 or 9, wherein the buried layer of highly doped silicon (35) of the first conductivity type is formed by implantation / dopant diffusion at the surface of the silicon substrate (31) and wherein the upper silicon layer (33) is epitaxially formed on the buried silicon layer (35).
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