EP2195720B1 - Capless low drop-out voltage regulator with fast overvoltage response - Google Patents

Capless low drop-out voltage regulator with fast overvoltage response Download PDF

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Publication number
EP2195720B1
EP2195720B1 EP08807839.9A EP08807839A EP2195720B1 EP 2195720 B1 EP2195720 B1 EP 2195720B1 EP 08807839 A EP08807839 A EP 08807839A EP 2195720 B1 EP2195720 B1 EP 2195720B1
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Prior art keywords
output
voltage
transistor
output voltage
coupled
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EP08807839.9A
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German (de)
French (fr)
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EP2195720A1 (en
Inventor
Hui Zhao
Zhen Yang
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NXP BV
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NXP BV
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/569—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection
    • G05F1/571—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection with overvoltage detector

Definitions

  • LDO voltage regulators require an external capacitor to make the output voltage stable.
  • a low quiescent current, "capless” LDO voltage regulator is increasingly used.
  • these capless LDO voltage regulators experience problems when the load current changes very fast, e.g. from several tens of milliamperes to zero in less than 1ns.
  • the output voltage will jump to the supply voltage due to limited on-chip output capacitance and slow loop response.
  • the output voltage falls down to normal value very slowly, depending on the resistance of a resistor divider and the capacitance of the on-chip capacitor.
  • the output voltage of the LDO voltage regulator will deviate from the normal value and stay around the supply voltage for a prolonged period of time. Inevitably, the low voltage load circuits will be destroyed or malfunction as a result.
  • US 6201375 B1 describes an LDO voltage regulator includes an error amplifier having a first input coupled to a first reference voltage, a second input receiving a feedback signal, and an output producing a first control signal.
  • An output transistor has a gate, a drain coupled to an unregulated input voltage, and a source coupled to produce a regulated output voltage on an output conductor.
  • a feedback circuit is coupled between the output conductor and a second reference voltage.
  • An overvoltage comparator has a first input coupled to receive the first reference voltage and a second input coupled to respond to the feedback signal to produce a discharge control signal indicating occurrence of an output overvoltage of at least a predetermined magnitude to control a discharge transistor coupled between the output conductor and the second reference voltage.
  • An output current sensing circuit produces a control current representative of the drain current of the output transistor.
  • An offset capacitor is coupled between the output of the error amplifier and the gate of the output transistor, and a servo amplifier has a first input coupled to receive a third reference voltage, a second input coupled to the output of the error amplifier, and an output coupled to the gate of the output transistor to produce a second control signal thereon.
  • a current sensor circuit, a current capacitor, and an AND circuit operate to allow the discharge transistor to be turned on only if the output current is below a certain level.
  • An improved voltage regulator is needed that retains the advantages of capless LDO voltage regulators but that is not as susceptible to overvoltage conditions like the ones described.
  • a voltage regulator and voltage regulation method are provided according to the claims.
  • a combination of fast and slow discharger circuits is used to improve the load step response-i.e., to stop the output voltage from jumping too high and to pull it back to a stable value very quickly, such that the load circuits are protected.
  • the circuit can be made to consume very low power (e.g., about 5 ⁇ A static current) and exhibit very high speed.
  • the circuit can handle a full-range load step (rising/falling) as fast as 1ns.
  • the voltage regulator 100 forms part of a power management IC 201 that supplied power to a core processor 203.
  • the core processor 203 may be the processor of a mobile electronic device, for example.
  • Power is supplied to the power management IC 201 from an external battery or USB device 205, which provides an input voltage Vin.
  • the input voltage Vin is applied to the voltage regulator 100 and to a switching power supply 210 that includes a low voltage pulse width modulation (PWM) controller 211 and switches 213.
  • PWM pulse width modulation
  • An output voltage Vout of the voltage regulator 100 serves as an internal power supply for the PWM controller 211.
  • the PWM controller produces control signals (e.g., PWM1, PWM2) that are applied to switches 213 along with the input voltage Vin.
  • control signals e.g., PWM1, PWM2
  • the input voltage Vin is converted to a voltage Voutcp used to supply the core processor 203.
  • FIG. 1 a circuit diagram is shown of a voltage regulator (capless LDO voltage regulator) having a fast overvoltage response.
  • the voltage regulator is preferably realized in the form of a single integrated circuit.
  • the basic structure of the voltage regulator includes an output transistor M, an output voltage sensing arrangement in the form of a resistive divider R1, R2, an error amplifier OTA, and an output capacitor Co.
  • the output transistor M is preferably a PMOS transistor. It is coupled in series with the resistive divider R1, R2. The series combination of the output transistor M and the resistive divider R1, R2 is connected between the supply voltage Vin and ground.
  • An output voltage line L is connected to a node N1 between the output transistor M and the resistive divider R1, R2, across which an output voltage Vout is produced. At an intermediate node N2 of the resistive divider R1, R2, a feedback voltage is produced, indicative of the output voltage Vout.
  • the power supply terminals of the error amplifier OTA are also connected to the supply voltage Vin and ground.
  • the negative input terminal of the error amplifier OTA is connected to a reference voltage Vref.
  • the positive input terminal of the error amplifier OTA is connected to the feedback voltage Voutfb.
  • An output terminal of the error amplifier OTA is connected to a gate electrode of the output transistor M.
  • the conduction state of the output transistor M is thereby controlled by a feedback loop in accordance with the difference between the reference voltage Vref and a feedback voltage Voutfb.
  • the output capacitor Co is coupled between the output line L and ground and serves to smooth out variations in the output voltage Vout.
  • a fast discharger circuit 2 is connected between the output voltage line L and ground.
  • the fast discharger circuit will be described in more detail in connection with FIG. 2 .
  • a slow discharger circuit 3 is also connected between the output voltage line L and ground. The slow discharger circuit will be described in more detail in connection with FIG. 3 .
  • the fast discharger circuit includes a discharge transistor Md, which may be an NMOS transistor, connected between the output voltage line L and ground.
  • a trigger circuit is connected in parallel with the discharge transistor Md and includes a capacitor Cd and a resistor Rd.
  • a gate electrode of the discharge transistor Md is connected to a node N3 between the capacitor Cd and the resistor Rd.
  • a start-up transistor Ms is connected in parallel with the resistor Rd. It is used to bypass the resistor Rd during a power-up event to avoid mis-triggering of the discharge transistor Md.
  • a delay unit D is connected to the output voltage line L and produces a control signal CS connected to a gate electrode of the start-up transistor Ms. The delay unit D is also connected to the supply voltage Vin and ground. Normally, the control signal CS is low, and the start-up transistor Ms is OFF. During a power-on event, however, the control signal CS is raised high, turning on the start-up transistor Md and preventing the discharge transistor Md from being turned on. When the output voltage Vout has stabilized, the control signal CS is lowered, turning the start-up transistor Ms OFF.
  • the fast discharger 2 does not consume static current, and when the output voltage begins to rise very fast, the fast discharger circuit 2 will trigger with zero time delay and discharge the output node. It thereby effectively limits the peak value of the output voltage to within a safe range and pulls the output voltage back to a normal value very fast, protecting the low voltage load circuits from damage.
  • the fast discharger circuit 2 is most efficient for abrupt overvoltage conditions.
  • a slow discharger circuit 3 may be provided.
  • the slow discharge circuit 3 may have a construction as shown in FIG. 3 .
  • a discharge transistor Mt (preferably NMOS) is connected between the output voltage line and ground. It is controlled by an unbalanced voltage comparator 31.
  • the power supply terminals of the voltage comparator 31 are connected to the supply voltage Vin and ground.
  • the negative input terminal of the voltage comparator is connected to a reference voltage Vref.
  • the positive input terminal of the voltage comparator 31 is connected to the feedback voltage Voutfb.
  • the slow discharger circuit 3 can ensure that the output voltage is reduced to a normal value very quickly.
  • the unbalanced feature of comparator is to ensure that transistor Mt will not be mis-triggered ON when offset voltages exists due to process and mismatch variations.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)

Description

  • Traditional LDO voltage regulators require an external capacitor to make the output voltage stable. To increase battery life and save PCB area in portable applications, a low quiescent current, "capless" LDO voltage regulator is increasingly used. However, these capless LDO voltage regulators experience problems when the load current changes very fast, e.g. from several tens of milliamperes to zero in less than 1ns. The output voltage will jump to the supply voltage due to limited on-chip output capacitance and slow loop response. Furthermore, after jumping up, the output voltage falls down to normal value very slowly, depending on the resistance of a resistor divider and the capacitance of the on-chip capacitor. As a result, the output voltage of the LDO voltage regulator will deviate from the normal value and stay around the supply voltage for a prolonged period of time. Inevitably, the low voltage load circuits will be destroyed or malfunction as a result.
  • US 6201375 B1 describes an LDO voltage regulator includes an error amplifier having a first input coupled to a first reference voltage, a second input receiving a feedback signal, and an output producing a first control signal. An output transistor has a gate, a drain coupled to an unregulated input voltage, and a source coupled to produce a regulated output voltage on an output conductor. A feedback circuit is coupled between the output conductor and a second reference voltage. An overvoltage comparator has a first input coupled to receive the first reference voltage and a second input coupled to respond to the feedback signal to produce a discharge control signal indicating occurrence of an output overvoltage of at least a predetermined magnitude to control a discharge transistor coupled between the output conductor and the second reference voltage. An output current sensing circuit produces a control current representative of the drain current of the output transistor. An offset capacitor is coupled between the output of the error amplifier and the gate of the output transistor, and a servo amplifier has a first input coupled to receive a third reference voltage, a second input coupled to the output of the error amplifier, and an output coupled to the gate of the output transistor to produce a second control signal thereon. A current sensor circuit, a current capacitor, and an AND circuit operate to allow the discharge transistor to be turned on only if the output current is below a certain level.
  • An improved voltage regulator is needed that retains the advantages of capless LDO voltage regulators but that is not as susceptible to overvoltage conditions like the ones described.
  • A voltage regulator and voltage regulation method are provided according to the claims. A combination of fast and slow discharger circuits is used to improve the load step response-i.e., to stop the output voltage from jumping too high and to pull it back to a stable value very quickly, such that the load circuits are protected. The circuit can be made to consume very low power (e.g., about 5µA static current) and exhibit very high speed. In an exemplary embodiment, the circuit can handle a full-range load step (rising/falling) as fast as 1ns.
  • Other features and advantages will be understood upon reading and understanding the detailed description of exemplary embodiments, found herein below, in conjunction with reference to the drawings, a brief description of which is provided below.
    • FIG. 1 is a simplified circuit diagram of a voltage regulator with fast load step response;
    • FIG. 2 is a circuit diagram illustrating in greater detail the fast discharger circuit of FIG. 1;
    • FIG. 3 is a circuit diagram illustrating in greater detail the slow discharger circuit of FIG. 1;
    • FIG. 4 is a block diagram illustrating one application of the voltage regulator of FIG. 1.
  • There follows a more detailed description of the present invention. Those skilled in the art will realize that the following detailed description is illustrative only and is not intended to be in any way limiting. Other embodiments of the present invention will readily suggest themselves to such skilled persons having the benefit of this disclosure. Reference will now be made in detail to embodiments of the present invention as illustrated in the accompanying drawings. The same reference indicators will be used throughout the drawings and the following detailed description to refer to the same or like parts.
  • Referring first to FIG. 4, one possible application is shown of a voltage regulator 100, described in greater detail hereinafter. The voltage regulator 100 forms part of a power management IC 201 that supplied power to a core processor 203. The core processor 203 may be the processor of a mobile electronic device, for example. Power is supplied to the power management IC 201 from an external battery or USB device 205, which provides an input voltage Vin. The input voltage Vin is applied to the voltage regulator 100 and to a switching power supply 210 that includes a low voltage pulse width modulation (PWM) controller 211 and switches 213. An output voltage Vout of the voltage regulator 100 serves as an internal power supply for the PWM controller 211. The PWM controller produces control signals (e.g., PWM1, PWM2) that are applied to switches 213 along with the input voltage Vin. By suitable control of the switches 213, the input voltage Vin is converted to a voltage Voutcp used to supply the core processor 203.
  • Referring now to FIG. 1, a circuit diagram is shown of a voltage regulator (capless LDO voltage regulator) having a fast overvoltage response. The voltage regulator is preferably realized in the form of a single integrated circuit. The basic structure of the voltage regulator includes an output transistor M, an output voltage sensing arrangement in the form of a resistive divider R1, R2, an error amplifier OTA, and an output capacitor Co. The output transistor M is preferably a PMOS transistor. It is coupled in series with the resistive divider R1, R2. The series combination of the output transistor M and the resistive divider R1, R2 is connected between the supply voltage Vin and ground. An output voltage line L is connected to a node N1 between the output transistor M and the resistive divider R1, R2, across which an output voltage Vout is produced. At an intermediate node N2 of the resistive divider R1, R2, a feedback voltage is produced, indicative of the output voltage Vout.
  • The power supply terminals of the error amplifier OTA are also connected to the supply voltage Vin and ground. The negative input terminal of the error amplifier OTA is connected to a reference voltage Vref. The positive input terminal of the error amplifier OTA is connected to the feedback voltage Voutfb. An output terminal of the error amplifier OTA is connected to a gate electrode of the output transistor M. The conduction state of the output transistor M is thereby controlled by a feedback loop in accordance with the difference between the reference voltage Vref and a feedback voltage Voutfb. The output capacitor Co is coupled between the output line L and ground and serves to smooth out variations in the output voltage Vout.
  • A fast discharger circuit 2 is connected between the output voltage line L and ground. The fast discharger circuit will be described in more detail in connection with FIG. 2. Optionally, a slow discharger circuit 3 is also connected between the output voltage line L and ground. The slow discharger circuit will be described in more detail in connection with FIG. 3.
  • Referring now to FIG. 2, the fast discharger circuit includes a discharge transistor Md, which may be an NMOS transistor, connected between the output voltage line L and ground. A trigger circuit is connected in parallel with the discharge transistor Md and includes a capacitor Cd and a resistor Rd. A gate electrode of the discharge transistor Md is connected to a node N3 between the capacitor Cd and the resistor Rd. In operation, when Vout rises very fast, Cd behaves as a short circuit, and the transistor Md will be triggered ON to pull Vout down.
  • A start-up transistor Ms is connected in parallel with the resistor Rd. It is used to bypass the resistor Rd during a power-up event to avoid mis-triggering of the discharge transistor Md. A delay unit D is connected to the output voltage line L and produces a control signal CS connected to a gate electrode of the start-up transistor Ms. The delay unit D is also connected to the supply voltage Vin and ground. Normally, the control signal CS is low, and the start-up transistor Ms is OFF. During a power-on event, however, the control signal CS is raised high, turning on the start-up transistor Md and preventing the discharge transistor Md from being turned on. When the output voltage Vout has stabilized, the control signal CS is lowered, turning the start-up transistor Ms OFF.
  • The fast discharger 2 does not consume static current, and when the output voltage begins to rise very fast, the fast discharger circuit 2 will trigger with zero time delay and discharge the output node. It thereby effectively limits the peak value of the output voltage to within a safe range and pulls the output voltage back to a normal value very fast, protecting the low voltage load circuits from damage.
  • The fast discharger circuit 2 is most efficient for abrupt overvoltage conditions. To improve efficiency for less-abrupt overvoltage conditions, a slow discharger circuit 3 may be provided. The slow discharge circuit 3 may have a construction as shown in FIG. 3. A discharge transistor Mt (preferably NMOS) is connected between the output voltage line and ground. It is controlled by an unbalanced voltage comparator 31. The power supply terminals of the voltage comparator 31 are connected to the supply voltage Vin and ground. The negative input terminal of the voltage comparator is connected to a reference voltage Vref. The positive input terminal of the voltage comparator 31 is connected to the feedback voltage Voutfb.
  • When the output voltage rises less abruptly, the slow discharger circuit 3 can ensure that the output voltage is reduced to a normal value very quickly. The unbalanced feature of comparator is to ensure that transistor Mt will not be mis-triggered ON when offset voltages exists due to process and mismatch variations.

Claims (15)

  1. A voltage regulator (100) comprising:
    an output transistor (M) coupled to an output voltage line (L);
    an output voltage sensing arrangement (R1, R2) coupled to the output voltage line (L) for producing an output feedback voltage (Voutfb);
    an error amplifier (OTA) coupled to the output feedback voltage (Voutfb), the output transistor (M), and a reference voltage (Vref) for applying feedback control to the output transistor (M);
    a first discharger circuit (2) coupled to the output voltage line (L) and to a reference potential, the first discharger circuit (2) being triggered by a steep-rise overvoltage condition; and characterized by
    a second discharger circuit (3) having a response time greater than a response time of the first discharger circuit (2).
  2. The voltage regulator (100) of Claim 1, wherein the first discharger circuit (2) comprises:
    a first shunt transistor (Md) coupled between the output voltage line (L) and a reference potential; and
    a trigger circuit coupled to the output voltage line (L) and the first shunt transistor.
  3. The voltage regulator (100) of Claim 2, wherein the trigger circuit comprises a series combination of a capacitor (Cd) and a resistor (Rd).
  4. The voltage regulator (100) of Claim 3, wherein the series combination of a capacitor (Cd) and resistor (Rd) is coupled between the output voltage line (L) and the reference potential.
  5. The voltage regulator (100) of Claim 2, wherein the first discharger circuit comprises a bypass transistor (Ms) coupled to the resistor (Rd), the bypass transistor (Ms) being turned on immediately following a power-up event.
  6. The voltage regulator (100) of Claim 5, comprising a delay circuit (D) coupled to the output voltage line (L) and the bypass transistor (Ms) for turning off the bypass transistor (Ms) after a delay time has elapsed following the power-up event.
  7. The voltage regulator (100) of Claim 1, wherein the second discharger circuit (3) comprises a second shunt transistor (Mt) and a comparator (31) coupled to the output voltage line (L), a reference voltage (Vout) and the second shunt transistor (Mt) for controlling the second shunt transistor (Mt).
  8. The voltage regulator (100) of Claim 7, wherein the comparator (31) is unbalanced to avoid mis- triggering of the second shunt transistor (Mt) due to fabrication process variations.
  9. The voltage regulator (100) of Claim 1, wherein the error amplifier (OTA) is a cascode transconductance amplifier.
  10. The voltage regulator (100) of Claim 1, formed on a single integrated circuit.
  11. The voltage regulator (100) of Claim 10, comprising an output capacitor (Co) coupled to the output voltage line (L) and formed on the integrated circuit.
  12. The voltage regulator (100) of Claim 1, wherein the first discharger circuit (2) provides fast response to an abrupt over-voltage condition, and the second discharger circuit (3) provides for more efficient discharge in the case of a less-abrupt over-voltage condition.
  13. A method of regulating an output voltage using the voltage regulator of claim 1, the method comprising:
    sensing the output voltage (Vout);
    applying feedback control to the output transistor (M) according to the sensed output voltage, said feedback control entailing a delay;
    apart from said feedback control, a steep-rise overvoltage condition causing the first discharger circuit (2) to shunt current from the output voltage line (L); and
    causing the second discharger circuit (3) to shunt current from the output voltage line (L) in response to the sensed output voltage (Vout).
  14. The method of claim 13, wherein the first discharger circuit (2) has a response time much less than said delay.
  15. The method of Claim 13, comprising preventing the first discharger circuit (2) from operating during a power-on event.
EP08807839.9A 2007-09-30 2008-09-29 Capless low drop-out voltage regulator with fast overvoltage response Active EP2195720B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CNA2007101642176A CN101398694A (en) 2007-09-30 2007-09-30 Non-capacitance low voltage difference constant voltage regulator with rapid excess voltage response
PCT/IB2008/053952 WO2009044326A1 (en) 2007-09-30 2008-09-29 Capless low drop-out voltage regulator with fast overvoltage response

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EP2195720A1 EP2195720A1 (en) 2010-06-16
EP2195720B1 true EP2195720B1 (en) 2015-06-17

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US (1) US8648578B2 (en)
EP (1) EP2195720B1 (en)
CN (2) CN101398694A (en)
WO (1) WO2009044326A1 (en)

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US8648578B2 (en) 2014-02-11
EP2195720A1 (en) 2010-06-16
CN101398694A (en) 2009-04-01
CN101815974A (en) 2010-08-25
WO2009044326A1 (en) 2009-04-09
US20100277148A1 (en) 2010-11-04

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