EP2050241A1

EP2050241A1 - Chip equalizer and equalizing method

Info

Publication number: EP2050241A1
Application number: EP07793400A
Authority: EP
Inventors: Goon Seop Lee; Dong Hahk Lee; Jae Hwang Yu; Jong Tae Ihm; Se Hyun Oh
Original assignee: SK Telecom Co Ltd
Current assignee: SK Telecom Co Ltd
Priority date: 2006-08-07
Filing date: 2007-08-07
Publication date: 2009-04-22
Also published as: WO2008018736A1; KR101393428B1; CN101502068A; KR20090038001A; CN101502068B; EP2050241A4

Abstract

Disclosed are a chip equalizer and an equalizing method capable of minimizing complexity for signal demodulation in accordance with performance of a receiver. The chip equalizer comprises a delay control module that recognizes an area having a main signal included therein from a signal distribution of signals received from a tuner and determines a noise compensation area in accordance with a delay difference between neighboring main signals; at least one first unit delay module that delays, among the signals received from the tuner, a signal of the area having the main signal included therein at an interval of a chip unit and outputs it to a tap co¬ efficient estimation module; and at least one second module that delays, among the signals received from the tuner, a signal of an area having no main signal included therein at an interval of a chip unit.

Description

Description CHIP EQUALIZER AND EQUALIZING METHOD

Technical Field

[1] The invention relates to a communication system, and more particularly, to a chip equalizer and an equalizing method capable of minimizing complexity for signal demodulation depending on performance of a receiver and adaptively changing a calculation amount. Background Art

[2] In recent years, as user's needs for high-quality audio and video services are increased, the commercialization of a digital broadcasting service is extended. The digital broadcasting can be classified into satellite broadcasting and terrestrial broadcasting.

[3] For the satellite digital broadcasting, a satellite base station receives broadcasting data from each broadcasting station and transmits it to a satellite through an uplink transmission path of a designated band, and the satellite amplifies and frequency- converts the signal received from the satellite base station and sends it toward a service area.

[4] Thereby, a receiver in a satellite broadcasting service area receives the broadcasting signal from the satellite and plays video and/or audio of the broadcasting. Meanwhile, in order to solve a problem in which the signal is attenuated due to shadowing or blocking resulting from a building or shielding object, a gap filler is used to relay the broadcasting signal.

[5] Fig. 1 shows a concept of a general satellite broadcasting system.

[6] Referring to Fig. 1, a satellite broadcasting system comprises a broadcasting station

100, a satellite base station 110, a satellite 120, a satellite control station 130, a broadcasting receiving terminal 140 and a gap filler 150.

[7] The satellite base station 110 receives broadcasting data from the broadcasting station 100 and transmits it to the satellite 120 through an uplink transmission path of Ku band (12.5 GHz to 18 GHz). The broadcasting station 100 that transmits the broadcasting data to the satellite 120 through the one or more satellite base stations 110 may be plural.

[8] The satellite 120 amplifies the broadcasting signal of Ku band, which is received from the satellite base station 110, and converts it into a broadcasting signal of S band. Then, the satellite sends the converted broadcasting signal of S band toward a service area, together with the broadcasting signal of Ku band.

[9] The satellite control station 130 serves to monitor and control an operating state of the satellite 120.

[10] The broadcasting receiving terminal 140 in the satellite broadcasting service area receives the broadcasting signal from the satellite 120 and reproduces it.

[11] However, the gap filler 150 relays and transmits the broadcasting signal at a point in which the signal attenuation is serious due to shadowing or blocking resulting from a building or shielding object. The gap filler 150 receives a TDM (Time Division Multiplexing) signal of Ku band from the satellite 120, converts it into a CDM (Code Division Multiplexing) signal of S band, and then sends the converted signal.

[12] The broadcasting receiving terminal 140 in the satellite broadcasting service area demodulates the CDM signal of S band which is received from the satellite 120, and the CDM signal of S band which is received via the gap filler 150, and plays video and/or audio of the broadcasting. The broadcasting receiving terminal 140 may be a portable terminal (for example, mobile communication terminal, personal data assistant (PDA), terminal mounted to a vehicle and the like).

[13] Fig. 2 shows a frame structure of a baseband transmission signal of a general gap filler.

[14] Referring to Fig. 2, a frame structure has a basic frame of 12.75 ms. The six basic frames constitute a super frame of 76.5 ms. Each broadcasting channel is a QPSK signal consisting of 816 bytes (6528 bits), in which an I (In-Phase) channel and a Q (Quadrature-Phase) channel consist of 408 bytes, respectively. A pilot channel, which is allocated to a Walsh 0-number code, is used for frame synchronization and transmission of control data. A pilot symbol (PS) and control data (Di) consist of 25D unit, respectively. A single pilot channel frame consists of 102 blocks comprised of 32 bits (i.e., 125D, 2048 chips). In other words, the single pilot channel frame consists of 51 pilot symbols (PS) and control data (Di, i=l, 2,..., 51). Dl, which is first control data of the pilot channel, is a unique word for frame synchronization. The pilot symbol is sent in an order of "11111111 11111111 11111111 11111111 " and the unique word (Dl) is sent in an order of "01101010 10110101 01011001 10001010." The pilot symbol (PS) and the unique word (Dl) are pilot data that are already recognized in the broadcasting receiving terminal 140.

[15] Fig. 3 shows a structure of a general satellite broadcasting transmission system.

[16] As shown, a satellite broadcasting transmission system comprises Reed-Solomon

(RS) encoders 110-1-110-n, byte interleavers 120-l~120-n, convolutions encoders 130-l~130-n, and bit interleavers 140-l~140-n, which are parts for encoding an audio/ video (AV) signal. The satellite broadcasting transmission system also comprises an RS encoder 110-x, a byte interleaver 120-x, and a convolution encoder 130x, which are parts for encoding a pilot signal that is a control signal. The satellite broadcasting transmission system also comprises a modulator 150 for modulating the encoded AV signal and a pilot signal, and an up-con verter 160 for performing a frequency up- conversion to send a broadcasting signal through an antenna.

[17] In such transmission system, in order to allow an independent broadcasting for each broadcasting station and/or content, the broadcasting signal is transmitted using different orthogonal spread codes, and a receiving system uses a Walsh code so as to distinguish the different broadcasting/contents signals.

[18] Fig. 4 shows a structure of a general satellite broadcasting receiving system.

[19] A satellite broadcasting receiving system comprises tuners 210-1-210-2, a CDM

(Code Division Multiplexing) demodulation section 220, a channel demodulation section 230, a demultiplexer 240, and a pilot channel demodulation section 250.

[20] The CDM demodulation section 220 comprises a plurality of Rake fingers

2210-1-2210-2 that receive a broadcasting signal in accordance with a PN code, adders 2220-1-2220-2 that outputs signals from the signals received through the Rake fingers 2210-1-2210-2 in accordance with signal intensity and delay, and despreaders 2230-1-2230-2 that despread the output signals from the adders 2220-1-2220-2 using the Walsh code. The output signals of the CDM demodulation section 220 are divided into a broadcasting channel signal and a pilot channel signal. The broadcasting channel signal is decoded in the channel demodulation section 230, and the pilot channel signal is decoded in the pilot channel demodulation section 250.

[21] To this end, the channel demodulation section 230 comprises bit deinterleavers

2310-1-2310-2, viterbi decoders 2320-1-2320-2, byte deinterleavers 2330-1-2330-2, and RS decoders 2340-1-2340-2. The pilot channel demodulation section 250 comprises a viterbi decoder 2510, a byte deinterleaver 2520, a RS decoder 2530, and a receiver controller 2540.

[22] Furthermore, the signal that is restored into an audio signal and a video signal in the channel demodulation section 230 is demuliplexed in the demultiplexer 240 and played.

[23]

[24] The current satellite broadcasting receiving system has a problem in that the Walsh code orthogonality of the received signal is lost due to the delay of the received signal and the frequency spreading in the multi-path channel environment, and there may thus occur a multi-channel interference and a desired broadcasting signal cannot be correctly restored. The problems can be overcome in a manner of decreasing the interference signal. However, in this case, the broadcasting service channel is limited.

[25] Accordingly, there has been researched a method of minimizing the interference between the received signals while not limiting the broadcasting channel. As one solution, there is a method of introducing an equalizer to a receiving system.

[26] The equalization is a signal processing technology of removing channel noise and channel distortion due to the signal delay resulting from the multi-path, thereby providing uniform amplitude and phase properties over an entire frequency band. In general, an equalizer uses a fixed delay line having a tap attached thereto to adjust a tap coefficient depending on delay characteristics of an input signal, thereby compensating for the interference between the codes. The tap coefficient may be changed in accordance with the channel estimation information and may be determined in accordance with noise signals (i.e., delay signals) distributing in delay positions of the surroundings of the data signals. In other words, the tap coefficient is set as a value for removing the noise signals.

[27] Fig. 5 illustrates a receiving system using a general chip equalizer.

[28] A chip equalizer 300 comprises a first equalizer 302 that acquires channel information using a pilot channel signal recognized from a broadcasting signal received from a tuner and first updates a tap coefficient using the acquired channel information, a second equalizer 304 that produces a pilot signal restored in accordance with the tap coefficient updated in the first equalizer 302 and secondarily updates the tap coefficient using the restored pilot signal and the pilot channel signal recognized from the received broadcasting signal, and a detector 306 that restores the received broadcasting signal using the tap coefficient secondarily updated in the second equalizer 304 and transmits the restored broadcasting signal to a channel demodulator.

[29] The tap coefficient updating process in the chip equalizer 300 is described with reference to Fig. 6.

[30] Fig. 6 is a detailed view showing a structure of the equalizer shown in Fig. 5.

[31] As shown, the equalizer comprises a unit delay module 312 that delays the broadcasting signal, which is received through a tuner, at an interval of a chip unit, a tap coefficient estimation module 314 that applies a spread code to each of the signals outputted from each output terminal of the unit delay module 312, sums up spread code application results to calculates a restored pilot signal and then applies a current tap coefficient to output an updated tap coefficient, an adder 316 that calculates an error value from the output signal of the tap coefficient estimation module 314 and the pilot channel signal recognized from the received broadcasting signal, and a step size adjusting module 318 that updates a step size using the calculated error value and transmits a step size update result to the tap coefficient estimation module 314 to update the tap coefficient.

[32] In such equalizer structure, the unit delay module forms the received bit signal into

64 blocks, for example by moving a sequence combination of the Walsh code and PN code used in a common pilot corresponding to 64 chips at an interval of a chip unit, in which a sum of a single block becomes a bit unit.

[33] An example of the equalizer as described above is disclosed in a Korean Patent unexamined Publication No. 2006-39961.

[34] When applying an equalizer to a receiving system, it is possible to track a multi- path channel and to minimize the interference between the neighboring channels. However, since the tap coefficient should be applied to all the noise signals included in the received signal for compensation, the complexity of the receiving system is increased.

[35] In particular, since the mobile communication terminal for using the satellite broadcasting service has a poorer performance, as compared to the apparatus such as base station, when the chip equalizer as described above is applied thereto, the complexity is increased, thereby lowering the operating speed. Disclosure of Invention Technical Problem

[36] The invention has been made to solve the problems occurring in the prior art. An object of the invention is to provide a chip equalizer and an equalizing method capable of compensating for a noise signal only for a part in which a main signal component is included, thereby improving performance of a receiving system having an equalizer applied thereto and simplifying a receiving module.

[37] Another object of the invention is to adaptively change a calculation amount for noise signal compensation in accordance with performance of a receiving system, thereby modifying performance of the receiving system depending on usages thereof. Technical Solution

[38] In order to achieve the above objects, there is provided a chip equalizer according to an embodiment of the invention comprising: a delay control module that recognizes an area having a main signal included therein from a signal distribution of signals received from a tuner and determines a noise compensation area in accordance with a delay difference between neighboring main signals; at least one first unit delay module that delays, among the signals received from the tuner, a signal of the area having a main signal included therein at an interval of a chip unit and outputs it to a tap coefficient estimation module; and at least one second unit delay module that delays, among the signals received from the tuner, a signal of an area having no main signal included therein at an interval of a chip unit under control of the delay control module.

[39] In addition, according to another embodiment of the invention, there is provided a chip equalizer comprising: a delay control module that recognizes an area having a main signal included therein from a signal distribution of signals received from a tuner, checks a range of the area having a main signal included therein and determines noise compensation area and range in accordance with a delay difference between neighboring main signals; at least one first unit delay module that delays, among the signals received from the tuner, a signal of a frequency range having the main signal included therein at an interval of a chip unit and outputs it to a tap coefficient estimation module, under control of the delay control module; and at least one second unit delay module that delays, among the signals received from the tuner, a signal of an area having no main signal included therein at an interval of a chip unit, under control of the delay control module. [40] Further, according to another aspect of the invention, there is provided an equalizing method comprising: a first step of, as signals are received through a tuner, analyzing a profile of the received signals to recognize an area having a main signal included therein, thereby determining a window position (i.e., noise compensation area); a second step of estimating a tap coefficient for the area having the main signal included therein in accordance with the window position; a third step of calculating an error value by referring to the tap coefficient estimated in the second step and a pilot channel signal recognized from the received signals; a fourth step of updating a step size in accordance with the error value; and a fifth step of updating the estimated tap coefficient in accordance with the updated step size.

Advantageous Effects

[41] According to the invention, the calculation amount for signal demodulation is minimized in a receiving system to which the equalizer is applied, so that the power consumption of the receiving system is minimized and the calculation amount is minimized. Moreover, it is possible to simplify a structure of the receiving system.

[42] In addition, since the calculation amount for noise compensation can be adaptively changed in accordance with the performance of the receiving system, the performance of the receiving system can be changed depending on the usages thereof. Further, it is possible to receive and reproduce the various broadcasting signals without the interference of the neighboring channels in a small-scaled receiving system. Brief Description of the Drawings

[43] The above and other objects, features and advantages of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[44] FIG. 1 shows a concept of a general satellite broadcasting system;

[45] FIG. 2 shows a frame structure of a baseband transmission signal of a general gap filler;

[46] FIG. 3 shows a structure of a general satellite broadcasting transmission system;

[47] FIG. 4 shows a structure of a general satellite broadcasting receiving system;

[48] FIG. 5 illustrates a receiving system using a general chip equalize;

[49] FIG. 6 is a detailed view showing a structure of the equalizer shown in FIG. 5; [50] FIG. 7 shows a structure of a chip equalizer according to an embodiment of the invention;

[51] FIG. 8 shows a structure of a chip equalizer according to another embodiment of the invention; and

[52] FIG. 9 is a flow chart for illustrating an equalizing method of the invention.

[53] <Description of reference numerals for important part of drawings>

[54] 302 : first equalizer 304 : second equalizer

[55] 306 : detector 320 : chip equalizer

[56] 3210 : delay control module

[57] 3220, 3240 : first unit delay module

[58] 3230 : second unit delay module

[59] 3250 : tap coefficient estimation module

[60] 3260 : adder 3270 : step size adjusting module

Mode for the Invention

[61] Hereinafter, a preferred embodiment of the invention will be more specifically described with reference to the drawings.

[62]

[63] Fig. 7 shows a structure of a chip equalizer according to an embodiment of the invention.

[64] The chip equalizer 320 according to an embodiment of the invention comprises a delay control module 3210 that analyzes a profile of signals received from a tuner to recognize an area having a main signal included therein and an area having no main signal included therein from a distribution of the received signals and determines a noise compensation area in accordance with a delay difference between neighboring main signals; at least one first unit delay modules 3220, 3240 that delay, among the signals received from the tuner, a signal of the area having the main signal included therein at an interval of a chip unit; and at least one second unit delay module 3230 that delays, among the signals received from the tuner, a signal of an area having no main signal included therein at an interval of a chip unit.

[65] The delay control module 3210 determines, as the noise compensation area, the area in which the main signal of the received signals is included, and transmits the signal of the area having the main signal included therein to the first unit delay modules 3220, 3240. In addition, the delay control module 3210 transmits the signal of the area in which the main signal of the received signals is not included to the second unit delay module 3230.

[66] A tap coefficient estimation module 3250 that receives the signals outputted from each of output terminals of the first unit delay modules 3220, 3240 applies a spread code to each of the outputted signals, sums up spread code application results to calculate a restored pilot signal, and then applies a current tap coefficient to output an updated tap coefficient.

[67] An adder 3260 calculates an error value from the output signal of the tap coefficient estimation module 3250 and a pilot channel signal recognized from the received broadcasting signals. A step size adjusting module 3270 uses the error value calculated in the adder 3260 to update a step size and transmits the step size update result to the tap coefficient estimation module 3250 to update the tap coefficient. Here, the step size adjusting module 3270 may be implemented in an adaptive least mean square (LMS) manner.

[68] In this embodiment, considering a channel characteristic that all the main signals included in the received signals do not exist over a broad range but appear in a burst form in a state that there is a delay difference, only the noise for the area in which the main signal component is included is compensated and the other area is not subject to the compensation. Therefore, it is possible to minimize the calculation amount necessary for restoring the received signals in a receiving system which has a limit to the signal processing capacity such as mobile communication terminal.

[69]

[70] Fig. 8 shows a structure of a chip equalizer according to another embodiment of the invention.

[71] This embodiment provides a chip equalizer capable of controlling a noise compensation range of an area having a main signal component included therein, in addition to the constitutions of the chip equalizer described with reference to Fig. 7.

[72] Specifically, the chip equalizer 330 of this embodiment comprises a delay control module 3310 that recognizes an area having a main signal included therein and an area having no main signal included therein from a signal distribution of signals received through a tuner, checks a range of the area having the main signal included therein and determines noise compensation area and range in accordance with a delay difference between neighboring main signals; at least one first unit delay modules 3320, 3340 that delay, among the signals of the area having the main signal included therein; a signal included in the range determined by the delay control module 3310 at an interval of a chip unit; and at least one second unit delay module 3330 that delays, among the signals received from the tuner, a signal of an area having no main signal included therein at an interval of a chip unit.

[73] The signals outputted from each output terminal of the first unit delay modules

3220, 3240 are inputted to a tap coefficient estimation module 3350. The tap coefficient estimation module 3350, an adder 3360 and a step size adjusting module 3370 perform the functions similar to those described in Fig. 7. Therefore, the detailed de- scriptions thereof are omitted.

[74] The chip equalizer 320 according to an embodiment of the invention, which is described in Fig. 7, compensates for the noise for the signal in the frequency range, in which the main signal is included, with the same window (tap coefficient estimation window). The chip equalizer of Fig. 8 also enables the window sizes of the signals for compensating for the noise to be changed in accordance with the characteristics of the received signal.

[75] The window size of this embodiment has a size of the first delay modules 3220,

3240 surrounded by the dotted lines in Fig. 8 and means the number of chip delayers (Tc) that output a delay signal to the tap coefficient estimation module 3350 so as to compensate for the noise of the received signal.

[76]

[77] It is described a method of estimating a tap coefficient as a received signal is inputted into the chip equalizers shown in Figs. 7 and 8, and restoring an original signal with the tap coefficient.

[78] Fig. 9 is a flow chart for illustrating an equalizing method of the invention.

[79] As signals are received through a tuner, the delay control module 3210, 3310 analyzes a profile of the received signals (SlO) to recognize an area having a main signal included therein and an area having no main signal included therein, and determines a noise compensation area, i.e., window position in accordance with a delay difference between neighboring main signals (S20). Here, the delay control module 3210, 3310 may analyze a profile of the received signals and recognize, as a main signal, a signal having a predetermined value or more of intensity of the received signals.

[80] The received signals are delayed at an interval of a chip unit in the first unit delay modules 3220, 3240, 3320, 3340 in accordance with the window position determined in the step of S20 and then inputted into the tap coefficient estimation module 3250, 3350, so that a tap coefficient is estimated (S30). For the estimation of the tap coefficient in the step of S30, the tap coefficient estimation module 3250, 3350 applies spread codes to each of the outputted signals, sums up the spread code application results to calculate a restored pilot signal, and then applies the current tap coefficient to output an updated tap coefficient.

[81] After that, when an error value is calculated from the output signal of the tap coefficient estimation module 3250, 3350 and the pilot channel signal already recognized (S40), it is inputted into the step size adjusting module 3270, 3370. Thereby, when the step size is updated (S50), it is inputted into the tap coefficient estimation module 3250, 3350, so that the tap coefficient is updated (S60).

[82] In the mean time, in addition to the determination of the noise compensation area in accordance with the delay difference between neighboring main signals in the delay control module 3210, 3310 before carrying out the step of S30 and after the step of S20, a step of S25 for determining a noise compensation range, i.e., window size may be further performed. In this case, since the noise compensation range can be adaptively compensated, it is possible to further minimize the calculation amount for signal demodulation.

[83]

[84] While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made thereto without departing from the spirit and scope of the invention as defined by the appended claims.

[85]

Industrial Applicability

[86] According to the invention, the calculation amount for signal demodulation is minimized in a receiving system to which the equalizer is applied, so that the power consumption of the receiving system is minimized and the calculation amount is minimized. Moreover, it is possible to simplify a structure of the receiving system.

[87] In addition, since the calculation amount for noise compensation can be adaptively changed in accordance with the performance of the receiving system, the performance of the receiving system can be changed depending on the usages thereof. Further, it is possible to receive and reproduce the various broadcasting signals without the interference of the neighboring channels in a small-scaled receiving system.

Claims

[1] A chip equalizer for a receiving system comprising: a delay control module that recognizes an area having a main signal included therein from a distribution of signals received from a tuner and determines a noise compensation area in accordance with a delay difference between neighboring main signals; at least one first unit delay module that delays, among the signals received from the tuner, a signal of the area having the main signal included therein at an interval of a chip unit and outputs it to a tap coefficient estimation module; and at least one second unit delay module that delays, among the signals received from the tuner, a signal of an area having no main signal included therein at an interval of a chip unit under control of the delay control module.

[2] The chip equalizer according to claim 1, further comprising: a tap coefficient estimation module that applies a spread code to each signal outputted from each output terminal of the at least one first unit delay, sums up spread code application results to calculate a restored pilot signal, and then applies a current tap coefficient to output an updated tap coefficient; an adder that calculates an error value from the output signal of the tap coefficient estimation module and a pilot channel signal recognized from the signals from the tuner; and a step size adjusting module that uses the error value calculated in the adder to update a step size and transmits a step size update result to the tap coefficient estimation module.

[3] The chip equalizer according to claim 1, wherein the delay control module analyzes a profile of the received signals to recognize an area in which the main signal of the received signals is included.

[4] The chip equalizer according to claim 3, wherein the delay control module recognizes, as the main signal, a signal having a predetermined value or more of intensity of the received signals.

[5] The chip equalizer according to claim 1, wherein the delay control module transmits a signal of the area having the main signal of the received signals to the first unit delay module, and a signal of the area having no main signal of the received signals to the second unit delay module.

[6] A chip equalizer for a receiving system comprising: a delay control module that recognizes an area having a main signal included therein from a distribution of signals received from a tuner, checks a range of the area having a main signal included therein, and determines noise compensation area and range in accordance with a delay difference between neighboring main signals; at least one first unit delay module that delays, among the signals received from the tuner, a signal of a frequency range having the main signal included therein at an interval of a chip unit, and outputs it to a tap coefficient estimation module, under control of the delay control module; and at least one second unit delay module that delays, among the signals received from the tuner, a signal of an area having no main signal included therein at an interval of a chip unit, under control of the delay control module.

[7] The chip equalizer according to claim 6, further comprising: a tap coefficient estimation module that applies a spread code to each signal outputted from each output terminal of the at least one first unit delay, sums up spread code application results to calculate a restored pilot signal, and then applies a current tap coefficient to output an updated tap coefficient; an adder that calculates an error value from the output signal of the tap coefficient estimation module and a pilot channel signal recognized from the signals from the tuner; and a step size adjusting module that uses the error value calculated in the adder to update a step size and transmits a step size update result to the tap coefficient estimation module.

[8] The chip equalizer according to claim 6, wherein the delay control module analyzes a profile of the received signals to recognize an area in which the main signal of the received signals is included.

[9] The chip equalizer according to claim 8, wherein the delay control module recognizes, as the main signal, a signal having a predetermined value or more of intensity of the received signals.

[10] The chip equalizer according to claim 6, wherein the noise compensation range is the number of chip delayers in the first unit delay module, which output the signal delayed at an interval of a chip unit to the tap coefficient estimation module.

[11] The chip equalizer according to claim 6, wherein the delay control module transmits a signal of the area having the main signal of the received signals to the first unit delay module, and a signal of the area having no main signal of the received signals to the second unit delay module.

[12] An equalizing method in a receiving system, the method comprising: a first step of, as signals are received through a tuner, analyzing a profile of the received signals to recognize an area having a main signal included therein, thereby determining a window position; a second step of estimating a tap coefficient for the area having the main signal included therein in accordance with the window position; a third step of calculating an error value by referring to the tap coefficient estimated in the second step and a pilot channel signal recognized from the received signals; a fourth step of updating a step size in accordance with the error value; and a fifth step of updating the estimated tap coefficient in accordance with the updated step size. [13] The method according to claim 12, wherein a signal having a predetermined value or more of intensity of the received signals in the first step is recognized as a main signal. [14] The method according to claim 12, further comprising a step of determining a noise compensation range for an area in which the main signal is located, before performing the second step after the first step.