EP1986950A1

EP1986950A1 - Mems components and method for manufacturing same

Info

Publication number: EP1986950A1
Application number: EP07709443A
Authority: EP
Inventors: Frank Niklaus; Göran Stemme
Original assignee: Individual
Current assignee: Individual
Priority date: 2006-01-31
Filing date: 2007-01-31
Publication date: 2008-11-05
Also published as: EP1986950A4; WO2007089204A1

Abstract

The invention relates to a method for making a MEMS device having connectors for interconnecting components in the MEMS device. The method comprises applying a sacrificial material layer on a first substrate wafer, the thickness of the sacrificial layer essentially defining the length of the connectors. Connectors made of electrically conducting and/ or mechanically rigid material are provided and embedded in the sacrificial material layer. Components are provided on top of the sacrificial layer by 3D integration with wafer bonding, to connect the components to the connectors. It also relates to a MEMS device made by 3D integration with wafer bonding comprising first and a second components interconnected by connectors having a length of > 4μm. The components can comprise integrated circuits.

Description

MEMS COMPONENTS AND METHOD FOR MANUFACTURING SAME

Technical Field

The present invention concerns methods for manufacturing MEMS components with a large enough distance between the detector and the supporting substrate for improving the performance of the components. Typical components that benefit from a large distance between the component and the supporting substrate are e.g. thermal infrared detectors that decrease the thermal conduction between the detector and its surroundings and micro-mirrors that increase their maximum tilting or deflection angle.

Background of the Invention

The performance of certain MEMS components can be increased by increasing the distance between the substrate and the supporting substrate wafer. This is specifically true for (but not limited to) thermal infrared detectors and micro- mirror devices. Other devices that can make use of this technology are microphones, pressure sensors, accelerometers and gyroscopes.

Thermal Infrared detectors:

A large number of infrared imaging applications, such as e.g. thermography, firefighting, night vision, automotive and other person detection systems require infrared imaging arrays at extremely low costs. For many of these applications and systems, noise equivalent temperature differences on the order of 200 mK are sufficient. To provide infrared bolometer arrays at very low costs, it is desirable to operate them in an atmospheric pressure environment or at least in an environment with lower requirements on the vacuum atmosphere. Thus, the cost for the vacuum packaging of the infrared bolometer array can be reduced. Therefore, a technology is needed to manufacture and integrate infrared detectors on read-out electronic circuits and at the same time providing a good thermal insulation between the detector and its surrounding by providing a large distance between the detector and nearby surfaces. Thereby, the infrared detector(s) can achieve a useful sensitivity (noise equivalent temperature difference) even when it is operated inside a high gas pressure environment.

Micro-mirrors: Micro-mirrors and micro-mirror arrays are used for optical switching applications, imaging applications (e.g. projection display systems and mask- less lithography systems) and for diffractive optics. If the micro-mirrors are placed with a close distance between the supporting substrate and the mirror membrane, the deflection angle or stroke of the micro-mirror is very small. Increasing the distance between the mirror membrane and the supporting substrate increases the maximum possible deflection angle or stroke of the micro-mirror.

The MEMS devices described above can be manufactured by (1) bulk micromachining (2) surface micromachining or (3) 3D integration / transfer bonding.

In bulk micromachining, a large distance between the devices and the substrate can be achieved by free-etching or partly removing the substrate underneath the MEMS components. However it is not possible to integrate electronic circuits underneath the MEMS components and large arrays consisting of small MEMS devices (below 200 μm x 200 μm) are difficult to manufacture using bulk micromachining.

In surface micromachining the materials for the MEMS devices are typically deposited, structured and free-etched on the supporting substrate. If the MEMS devices are to be integrated on top of standard integrated circuit wafers, the deposition and processing temperatures for the MEMS materials can not be above about 400⁰C. Otherwise the underlying integrated circuit wafer is destroyed by the high temperatures. This prevents many high-temperature deposited and/or mono-crystalline MEMS materials from being used on top of integrated circuit wafers.

In 3D integration or transfer bonding (as described in US-7,054,052 and US- 7,067,345; incorporated herein in their entirety by reference) a high performance MEMS material is first deposited on a handle wafer with a suitable deposition process (e.g. high temperature deposition, epitaxial deposition etc.) or other manufacturing process. This high performance MEMS material(s) are then transferred from the handle wafer to the wafer with the integrated circuits using low- temperature wafer bonding processes. However, with these techniques it is not possible to manufacture MEMS devices with a large and still uniform distance (> 4 μm) to the supporting substrate wafer, specifically if the MEMS devices are small (below 200 μm x 200 μm) and the vias between the MEMS devices and the supporting substrate wafers have a high aspect ratio (> 3: 1). Vias with large aspect ratios between their diameter and their length are difficult to manufacture using 3D integration in combination with standard etching techniques.

Summary of the Invention

In view of the foregoing background, it would be desirable to have access to a method for manufacturing MEMS components with a larger distance, compared to the prior art, between the MEMS device and the supporting substrate in combination with small and high-aspect-ratio vias in order to achieve an increased device performance.

Accordingly it is an object of the present invention to provide an improved manufacturing method for MEMS devices which overcomes or at least reduces the above mentioned problems.

The method according to the invention is defined in claim 1.

In a first embodiment, the method comprises manufacturing a thick polymer layer (> 4 μm) or another thick film material that can be used as sacrificial layer with embedded high aspect ratio electrical vias (length to width aspect ratios on the order of 3: 1 or higher) on a substrate wafer . The MEMS components are then manufactured on top of the thick polymer layer with the embedded vias using 3D integration with wafer bonding or alternatively using surface micromachining. Finally the thick film polymer layer is optionally sacrificially removed with dry or wet etching to create free hanging membrane structures. In another embodiment, the invention further comprises integrated circuits on the substrate (or on at least one of the two substrates if substrate bonding (3D integration) is used) (e.g. see FIG. l).

In another embodiment, the invention further comprises sensors or actuators (or parts of them) on at least one of the two substrates if substrate bonding is used (e.g. see FIG. l).

In another embodiment, the invention further comprises infrared detectors (e.g. pyroelectric detectors, ferroelectric detectors, micro-bolometers or arrays of these type of detectors or parts of them etc).

In another embodiment, the invention further comprises infrared detectors made of high temperature deposited, sensing materials.

In another embodiment, the invention further comprises infrared detectors made of mono-crystalline semiconductor materials.

In another embodiment, the invention further comprises infrared detectors made of epitaxially grown, mono-crystalline materials.

In another embodiment, the invention further comprises infrared detectors made of high performance (low 1/f noise and high TCR) SiGe or GaAs quantum well structures.

In another embodiment, the invention further comprises micro mirrors or micro mirror arrays (e.g. torsional micro mirrors).

In another embodiment, the invention further comprises the micro mirrors made of high temperature deposited materials.

In another embodiment, the invention further comprises micro mirrors made of mono-crystalline semiconductor materials (e.g. Si, InP, GaAs) and optional coating these mirrors on one or both sides with a reflective layer (e.g. a metal layer).

In another embodiment the thick film polymer consists of a partially or fully cured thermosetting polymer.

In another embodiment the thick film polymer consists of a thermoplastic polymer.

In another embodiment the thick film polymer consists of a photosensitive polymer (e.g. photoresist or others).

In another embodiment the thick film polymer consists of a photosensitive polymer that is a fully or partially cured thermosetting polymer.

In another embodiment, coating a bonding agent (polymer layer, fully or partially cured thermosetting polymer, thermoplastic polymer layer etc.) either on one or both of the substrates to be bonded (for the 3D integration) and using this/these layers as the bonding layer (see FIG.8).

In another embodiment, electrical high aspect ratio vias that are made by micromachining techniques and subsequently coating the wafer and the vias with a thick polymer layer made of any of the previously mentioned polymers (see FIG.8).

In another embodiment, using the thick film polymer layer with the embedded high aspect ratio vias as the bonding agent (see FIG.2, 3, 7, 8).

In another embodiment creating electrical contacts between the substrates and the embedded vias at the same time as adhesively bonding the substrates (see FIG.3).

In another embodiment planarizing one or both substrates with e.g. chemical mechanic polishing or grinding prior to wafer-to-wafer bonding (see FIG.5). In another embodiment, the vias made in the subsequent 3D integration process (or in the subsequent surface micromachining process) having a lower or equal diameter as the (embedded) vias to the supporting substrate (see e.g. FIG. If).

In another embodiment, the components made in the subsequent 3D integration process (or in the subsequent surface micromachining process) having a high fill factor and thereby covering parts of the lower, high-aspect ratio vias. Thus, there is an overlap between the component and the lower vias in vertical direction (see e.g. FIG. If).

In another embodiment using a polymer layer as the sacrificial layer for surface micromachining the MEMS components on the supporting substrate (see FIG.9).

In another embodiment, thermal infrared detectors on top of a substrate containing integrated electronic circuits, having a distance to the supporting substrate (FIG.10) of D > 5 μm, D > 10 μm, D > 20 μm or D > 30 μm, optionally fabricated using the previously described technology.

In another embodiment, the above thermal infrared detectors containing a resonant optical cavity structure with the functionality as shown in FIG.10.

In another embodiment, the above thermal infrared detectors are bolometer or pyroelectric or ferroelectric detectors and consists of mono-crystalline temperature sensing materials (e.g. mono Si, SiGe, GaAs or multilayer structures thereof (quantum well structures)).

In another embodiment, the above thermal infrared detectors with integrated electronic circuits on the substrate underneath the detector structures.

In another embodiment, a micro-mirror made of monocrystalline materials (e.g. Si) on top of a substrate containing integrated electronic circuits, having a distance to the supporting substrate (FIG.10) of D > 5 μm, D > 10 μm or D > 20 μm, optionally fabricated using the with previously described technology. In another embodiment, the above micro-mirrors with integrated electronic circuits on the substrate underneath the mirror membranes.

Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter and the accompanying drawings which are given by way of illustration only, and thus not to be considered limiting on the present invention.

Brief Description of the Drawings

Fig. 1 shows different stages in the process according to a first embodiment of the invention;

Fig. 2 shows different stages in the process according to a second embodiment of the invention;

Fig. 3 shows different stages in the process according to a third embodiment of the invention;

Fig. 4 shows one variation on how to create the vias that are embedded in the thick sacrificial thick film material layer used in the processes from FIG 1-3 and FIG 6-9;

Fig. 5 shows another variation on how to create the vias that are embedded in the thick film material layer used in the processes from FIG 1-3 and FIG 6-9;

Fig. 6 shows different stages in the process according to a fourth embodiment of the invention;

Fig. 7 shows different stages in the process according to a fifth embodiment of the invention; Fig. 8 shows different stages in the process according to a sixth embodiment of the invention;

Fig. 9 shows different stages in the process according to a seventh embodiment of the invention; and

Fig. 10 two schematics of micro mirror (24) and infrared detector devices (28, 29, 30) for which the proposed invention can be used.

Detailed Description of Preferred Embodiments

For the purpose of this application, the terms "wafer" and "substrate" are used interchangeably, the differences between them merely amounting to dimensions thereof.

"Component" shall be taken to mean any structure that is provided as a subunit on a wafer or substrate, and can comprise entire devices, as well as details of such devices, even a single piece of material.

"Adhesive material" shall be taken to mean any material or material combination that can be used as an intermediate bonding material when bonding two wafers.

The method according to the present invention is particularly suited (but not limited) for the manufacturing of infrared detector arrays and micro-mirror arrays consisting of high performance (e.g. high temperature deposited or epitaxial grown or crystalline) MEMS materials.

"3D integration" or "transfer bonding" (as described in US-7,054,052 and US- 7,067,345; incorporated herein in their entirety by reference) comprises depositing/ providing high performance MEMS material(s) on a handle wafer with a suitable process (e.g. high temperature deposition, epitaxial deposition etc.). This/these high performance MEMS material(s) is/are then transferred from the handle wafer to the wafer with the integrated circuit wafers using low- temperature wafer bonding processes. Figure 1 to 9 illustrate schematically several variations of the manufacturing process according to the embodiments of the invention. In the Figures, 1 is a supporting substrate with optional components (e.g. electronic circuits manufactured on the wafer by conventional processes (not drawn), a passivation layer(s) (3) and electrical contact pads (2)). 4 is a thick film polymer layer, 4a is a unpatterned, non-photosensitive thick film polymer layer or other thick film material layer that can be used as sacrificial layer, 5 are electrical vias (e.g. metal), 6 is the sacrificial substrate, 7 is an optional etch stop layer, 8 are MEMS transducers or transducer material(s), 9 is the bonding layer(s), 10 are etched vias, 10a are second-level vias, 11 are MEMS transducer structures, 12 are vias that are not making up a flat surface with the thick film polymer layer, 13 are etched via holes in the thick film polymer layer or thick film sacrificial material layer, 14 is a patterned etching mask (e.g. resist, patterned metal, oxide or nitride layer), 15 is a bonding layer(s) that work at the same time as a planarization layer (s), 16 are vias that only partially fill the via holes in the thick film layer, 17 is a masking layer for fabrication the high aspect ratio vias, 18 are vias that are fabricated using micromachining techniques, 19 is a thick film polymer layer(s) or other thick film sacrificial material layer(s) in which the high aspect ratio vias are embedded, 20 is a sacrificial polymer layer(s) for the surface micromachining process, 21 are monolithically deposited MEMS transducers or transducer material(s), 22 are etched via holes, 22a are second-level vias, 23 are monolithically integrated MEMS transducers (surface micromachining), 24 are mono-crystalline micromirror membranes (or multilayer structures containing mono-crystalline layers), 25 are high-aspect ratio micromirror vias, 26 are substrates with integrated electronic circuits (e.g. read-out- electronics for the thermal infrared sensors or addressing electronics for the mirrors), 27 are high- aspect ratio vias for the thermal detectors, 28 are infrared antireflection/absorption layer(s), 29 are material layers consisting of structural membrane layers and mono-crystalline thermal sensing layers, 30 are infrared mirror layer(s) and λ is a distance close to the wavelength of the infrared radiation to be absorbed.

The aim of the present invention is the manufacturing of 3D integrated and/or so called surface micromachined MEMS transducers with a large distance, i.e. larger than about 4μm, between the MEMS structure and the supporting substrate. A typical size of the components, such as micromirrors or bolometers are from 2 x 2 μm² to 1000 x 1000 μm² with minimum feature sizes of 0.01 μm to 200 μm. The components could be arrayed components with up to several million of pixels per array.

3D integrated components with high distance to substrate

A typical variation of the present invention is detailed in FIG 1 , which is a schematic illustration of a CMOS wafer and described as follows. First components are provided on a first wafer (1) manufactured by some standard type and cost efficient process, such as those methods commonly employed in application specific integrated circuit (ASIC) production, in IC foundries and/ or in MEMS foundries. The components can for example be integrated electronic circuits, radio frequency circuits, pressure sensors, acceleration sensors, gyroscopes, micro-mirrors, thermal radiation sensor, (e.g. infrared bolometers), RF-MEMS devices or parts of these components (even a single material layer on the wafer).

Contact pads (2) are made on the wafer (1) as islets in a passivation layer, by deposition of the material for the passivation layer, patterning that layer and etching to open up holes which are subsequently filled with metal.

Next step is providing components (8) on a second wafer (6) that are manufactured by some standard type and cost efficient process, such as those methods commonly employed in application specific integrated circuit (ASIC) production, in IC foundries and/ or in MEMS foundries. The components (8) can for example be integrated electronic circuits, radio frequency circuits, pressure sensors, acceleration sensors, gyroscopes, micro-mirrors, thermal radiation sensor, (e.g. infrared bolometers), RF-MEMS devices or parts of these components, even a single material layer on the wafer. Thus, reference numeral 8 designates a general concept of a component. The processes used for fabricating the components on the two separate wafers do not need to be compatible with each other. On one of the two wafers (1, 6), in Fig. 1 on the first wafer (1), a thick film sacrificial layer (e.g. a polymer layer) (4) is deposited and patterned as shown in FIG Ib. Integrated high-aspect ratio vias (5) that connect to electrical contact pads (2) on the respective substrate are manufactured by e.g. electroless plating or plating or any other method for depositing metal in a hole as shown in FIG Ic. The thick film polymer can be between 4 and > 100 μm thick and the patterned vias can be between 0.1 and > 500 μm in diameter. The process of via fabrication can be repeated on one or both of the wafers to create even higher aspect ratio vias. The two wafers (1, 6) can then be bonded to each other using the intermediate bonding agent (e.g. a polymer layer) (9). Many such polymer bonding procedures typically require pressing the two wafers together and applying a certain temperature to cure, soften or melt the intermediate polymer material(s) and to create a bond between the substrates. There may be wafer-to-wafer alignment required between matching structures or components (8) and the vias (5) or contact pads (2) on the two wafers before/during/ after bonding, or the structures may be designed in a way that there is no alignment between the high aspect ration vias and the structures on the second wafer are required (e.g. if the structures (8) on the second wafer consist of un-patterned material film(s) (e.g. shown in FIG. Id). In principle, other bonding techniques, such a eutectic bonding or plasma assisted direct bonding can also be used. Therefore, suitable bonding layers and surface preparation techniques will be required, prior to the bonding of the substrates. After the substrate bonding, at least one substrate is sacrificially removed using e.g. wafer grinding or etching processes or a combination of those, leaving the structures or parts of them on top of the thick film polymer layer(s) (4 and 9) with the embedded vias (5) on top of the second wafer as shown in FIG Id, where the substrate (6) is sacrificially removed. For the sacrificial substrate removal, an etch-stop layer or a grinding stop-layer (7) could optionally be used which is subsequently removed by a selective etching process as shown in FIG Ie. The structures (11) can then be further processed (using semiconductor or other etching, patterning and/ or deposition processes) as shown in FIG Ie. Before, during or after that the components are processed, another level of vias (10a) are defined and deposited as shown in FIG Ie, that electrically connect the high-aspect ratio vias (5) and the components on top (11) . This can typically be done by via etching (10) as shown in FIG Ie and subsequent metal deposition (e.g. electro-less plating, electroplating, sputtering or evaporation with subsequent patterning and etching) (10a) as shown in FIG If. These vias (10a) can have a diameter of 0.01 to > 50 μm and a length of 0.1 to 20 μm. Finally, after the components (11) and the vias (10a) are manufactured, the intermediate polymer layer(s) (including the thick film polymer layer) (4 and 9) can optionally be sacrificially and selectively removed by wet or dry etching (e.g. in an oxygen plasma) as shown in FIG If. In a preferred embodiment the polymer is removed.

FIG 2 shows another variation of the invention in which the thick film polymer layer (4) with the embedded vias (5) is used as the adhesive bonding agent. Providing components on a first wafer (1) manufactured by some standard type and cost efficient process, such as those methods commonly employed in application specific integrated circuit (ASIC) production, in IC foundries and/ or in MEMS foundries. The components can for example be integrated electronic circuits, radio frequency circuits, pressure sensors, acceleration sensors, gyroscopes, micro-mirrors, thermal radiation sensor, (e.g. infrared bolometers), RF-MEMS devices or parts of these components (even a single material layer on the wafer). Providing components (8) on a second wafer (6) that are manufactured by some standard type and cost efficient process, such as those methods commonly employed in application specific integrated circuit (ASIC) production, in IC foundries and/or in MEMS foundries. The components (8) can for example be integrated electronic circuits, radio frequency circuits, pressure sensors, acceleration sensors, gyroscopes, micro-mirrors, thermal radiation sensor, (e.g. infrared bolometers), RF-MEMS devices or parts of these components (even a single material layer on the wafer). The processes used for fabricating the components on the two separate wafers do not need to be compatible with each other. On one of the two wafers (1, 6) or on both wafers, a thick film sacrificial layer (e.g. a polymer film) (4) is deposited and patterned as shown in FIG 2b. Integrated high-aspect ratio vias (5) that connect to electrical contact pads (2) on the respective substrate are manufactured as shown in FIG 2c. The thick film polymer can be between 4 and > 100 μm thick and the patterned vias can be between 0.1 and > 500 μm in diameter. The process of via fabrication can be repeated on one or both of the wafers to create even higher aspect ratio vias. The two wafers (1, 6) can then be bonded to each other using the thick film polymer layer (4) with the embedded vias (5) as the adhesive or direct bonding agent. Many such polymer bonding procedures typically require pressing the two wafers together and applying a certain temperature to cure, soften or melt the intermediate polymer material(s) and to create a bond between the substrates. There may be wafer-to-wafer alignment required between matching structures or components (8) and the vias (5) or contact pads (2) on the two wafers before/ during/ after bonding, or the structures may be designed in a way that there is no alignment between the high aspect ration vias and the structures on the second wafer are required (e.g. if the structures (8) on the second wafer consist of un-patterned material film(s) (e.g. shown in FIG.2d). In principle, other bonding techniques, such a eutectic bonding or plasma assisted direct bonding can also be used. Therefore, suitable bonding layers and surface preparation techniques will be required, prior to the bonding of the substrates. After the substrate bonding, at least one substrate is sacrificially removed using e.g. wafer grinding or etching processes or a combination of those, leaving the structures or parts of them on top of the thick film polymer layer(s) (4) with the embedded vias (5) on top of the second wafer as shown in FIG 2d, where the substrate (6) is sacrificially removed. For the sacrificial substrate removal, an etch-stop layer or a grinding stop-layer (7) could optionally be used. The structures (11) can then optionally be further processed (using semiconductor or other etching, patterning and/ or deposition processes) as shown in FIG 2e. Before, during or after the components are processed, another level of vias (10a) can be defined and deposited as shown in FIG 2e. Such vias will electrically connect the high-aspect ratio vias (5) and the components on top (11). This can typically be done by via etching (10) as shown in FIG 2e and subsequent metal deposition (e.g. electro-less plating, electroplating, sputtering or evaporation with subsequent patterning and etching) (10a) as shown in FIG 2f. These vias (10a) can have a diameter of 0.01 to > 50 μm and a length of 0.1 to 20 μm. Finally, after the components (11) and the vias (10a) are manufactured, the intermediate thick film polymer layer (4) can optionally be sacrificially and selectively removed by wet or dry etching (e.g. in an oxygen plasma) as shown in FIG 2f.

In principle there can already be an established electrical connection between structures 11 and vias 5 in the state shown in Fig. 5e, in which case the second level vias (10a) could be refrained from. Nevertheless, such vias (10a) could facilitate further attachment of other components at a later stage in the processing of the device.

FIG 3 shows a variation of the invention in which thick film polymer layer (4) with the embedded vias (5) is deposited on top of the substrate (6) and is used as the adhesive bonding agent, while at the same time as creating an adhesive bond between the substrates ( 1 and 6) also a direct bond between the vias (5) and the contact pads (2).

Components are provided on a first wafer (1) manufactured by some standard type and cost efficient process, such as those methods commonly employed in application specific integrated circuit (ASIC) production, in IC foundries and/ or in MEMS foundries. The components can for example be integrated electronic circuits, radio frequency circuits, pressure sensors, acceleration sensors, gyroscopes, micro-mirrors, thermal radiation sensor, (e.g. infrared bolometers), RF-MEMS devices or parts of these components (even a single material layer on the wafer). Providing components (8) on a second wafer (6) that are manufactured by some standard type and cost efficient process, such as those methods commonly employed in application specific integrated circuit (ASIC) production, in IC foundries and/or in MEMS foundries. The components (8) can for example be integrated electronic circuits, radio frequency circuits, pressure sensors, acceleration sensors, gyroscopes, micro-mirrors, thermal radiation sensor, (e.g. infrared bolometers), RF-MEMS devices or parts of these components (even a single material layer on the wafer). The processes used for fabricating the components on the two separate wafers do not need to be compatible with each other. On one of the two wafers (6), a thick polymer film (4) is deposited and the integrated vias (5) are manufactured as shown in FIG 3b. The integrated high-aspect ratio vias (5) may but do not have to connect to electrical contact areas on the substrate (6). The two wafers (1, 6) can then be bonded to each other using the thick film polymer layer (4) with the embedded vias (5) as the adhesive or direct bonding agent. At the same time while creating the adhesive wafer bond, bonding between the embedded vias (5) and the contact pads (2) is achieved, thereby electrically contacting the vias (5) and the contact pads (2) as shown in FIG 3c. The bonding between the vias (5) and the contact pads (2) may be metal- to-metal fusion bonding, eutectic bonding, metal- to-metal direct bonding, solder bonding, cold welding or any other suitable technique. Wafer-to-wafer alignment is required between the vias (5) and the contact pads (2) on the two wafers before/ during/ after bonding as shown in FIG 3b and c. After the substrate bonding, at least one substrate (6) is sacrificially removed using e.g. wafer grinding or etching processes or a combination of those, leaving the structures or parts of them on top of the thick film polymer layer (4) with the embedded vias (5) on top of the second wafer as shown in FIG 3d, where the substrate (6) is sacrificially removed. For the sacrificial substrate removal, an etch-stop layer or a grinding stop-layer (7) could optionally be used. The structures (11) can then be further processed (using semiconductor or other etching, patterning and/or deposition processes) as shown in FIG 3d. Before, during or after that the components are processed, another level of vias (10a) can optionally be defined and deposited as shown in FIG 3e, that electrically connect the high-aspect ratio vias (5) and the components on top (11) . This can typically be done by via etching (10) as shown in FIG 3e and subsequent metal deposition (e.g. electro-less plating, electroplating, sputtering or evaporation with subsequent patterning and etching) (10a) as shown in FIG 3e. The vias (10a) that are indicated in FIG.3e are not necessarily required in this variation of the invention but are optional (electrical contact between the contact areas of the components (8) may be established already at the moment when the vias (5) are fabricated as shown in FIG 3b. Finally, after the components (11) and the vias (10a) are manufactured, the intermediate thick film polymer layer (4) can optionally be sacrificially and selectively removed by wet or dry etching (e.g. in an oxygen plasma) as shown in FIG 3e.

FIG 4 shows one variation on how to create the vias that are embedded in the thick film sacrificial material (e.g. a polymer layer) used in the processes from FIG 1-3 and FIG 6-9. A thick film photoresist is spin-coated on the substrate (1 or 6) and patterned using photolithography, thereby defining the vias as shown in. FIG 4b. The defined vias in the resist can be filled by using electroplating or electroless-plating technologies to create the vias (12). Typical aspect ratios for the vias that are possible with this technology are on the order of 1:5 or higher. The thick film polymer (4) can be between 4 and > 100 μm thick and the patterned vias can be between 0.1 and > 500 μm in diameter. If the metal vias that are made become higher (see Fig. 4c) or lower (see Fig. 6c) than the thick film polymer (4) the surface can optionally be planarized by grinding the surfaces (polymer and/or vias), by chemical-mechanical-polishing the surfaces (polymer and/ or vias), by etching the surfaces (polymer and/ or vias) or by other suitable processes. FIG 4c shows a situation in which the vias before the surface planarization (12) are higher that the thick film polymer (4) and the surface is being planarized by e.g. grinding the surface (the vias) or by chemical- mechanical-polishing the surface (the vias) as shown in FIG 4d. The process for the via fabrication can be repeated (once or several times) on one or both of the wafers to create even higher aspect ratio vias.

The reason for vias being higher or lower as indicated above, can be a deliberate decision in the manufacturing process, since it can be difficult to make vias being exactly flush with the polymer, i.e. being in the same plane. Planarizing the structure from a situation as shown in either Fig. 4c or Fig. 6c would be more controllable than an unknown situation.

FIG 5 shows another variation on how to create the vias that are embedded in the thick film sacrificial material layer (e.g. a polymer layer) used in the processes from FIG 1-3 and FIG 6-9. A thick film sacrificial material layer (e.g. a polymer) (4a) is spin-coated or deposited with any other suitable technique on the substrate and patterned. For the patterning of the thick film polymer, a hard mask (14) is used. One possible way to create the hard mask, is to deposit the mask material (e.g. a metal, silicon nitride, silicon oxide or a similar material) on the thick film polymer using sputtering, evaporation, chemical vapor deposition, plasma enhanced vapor deposition or a similar technique. The mask material is patterned using resist patterning and etching of the mask material with wet or dry etching processes as shown in FIG 5c. Thereafter, the thick film polymer is unisotropically etched as shown in FIG 5c using e.g. dry etching such as e.g. deep reactive ion etching, thereby defining the vias. The hard mask can then be removed using wet or dry etching processes as shown in FIG 5d. The defined vias in the resist can be filled by using electroplating, electroless-plating technologies or any other suitable technique to create the vias (5). Typical aspect ratios for the vias that are possible with this technology are on the order of 1:5 or higher. The thick film polymer (4) can be between 4 and > 100 μm thick and the patterned vias can be between 0.1 and > 500 μm in diameter. If the metal vias are higher or lower than the thick film polymer (4) the surface can be planarized by grinding the surfaces (polymer and/ or vias), by chemical- mechanical-polishing the surfaces (polymer and/ or vias), by etching the surfaces (polymer and/or vias) or by other processes. The process for the via fabrication can be repeated (once or several times) on one or both of the wafers to create even higher aspect ratio vias.

FIG 6 shows another variation of the invention in which the vias (5) that are embedded in the thick film sacrificial layer (e.g. a polymer) are slightly shorter (or longer) than the thickness of the thick film polymer (4). Providing components on a first wafer (1) manufactured by some standard type and cost efficient process, such as those methods commonly employed in application specific integrated circuit (ASIC) production, in IC foundries and/or in MEMS foundries. The components can for example be integrated electronic circuits, radio frequency circuits, pressure sensors, acceleration sensors, gyroscopes, micro-mirrors, thermal radiation sensor, (e.g. infrared bolometers), RF-MEMS devices or parts of these components (even a single material layer on the wafer). Providing components (8) on a second wafer (6) that are manufactured by some standard type and cost efficient process, such as those methods commonly employed in application specific integrated circuit (ASIC) production, in IC foundries and/ or in MEMS foundries. The components (8) can for example be integrated electronic circuits, radio frequency circuits, pressure sensors, acceleration sensors, gyroscopes, micro-mirrors, thermal radiation sensor, (e.g. infrared bolometers), RF-MEMS devices or parts of these components (even a single material layer on the wafer). The processes used for fabricating the components on the two separate wafers do not need to be compatible with each other. On one of the two wafers (1, 6) or on both wafers, a thick polymer film (4) is deposited and patterned as shown in FIG 6b. Integrated high-aspect ratio vias (5) that connect to electrical contact pads (2) on the respective substrate are manufactured by electroplating, electroless plating etc. discussed before, as shown in FIG 6c. The vias (5) are slightly shorter than the height of the thick film polymer as shown in FIG 6c. The thick film polymer can be between 4 and > 100 μm thick and the patterned vias can be between 0.1 and > 500 μm in diameter. The surface of the thick film polymer with the embedded vias is planarized (or partially planarized) by spincoating or spray coating the intermediate bonding material (15) on one (as shown in FIG 6d) or on both of the wafer surfaces. The two wafers (1, 6) are then bonded to each other using the intermediate polymer layer (15). There may be wafer-to-wafer alignment required between matching structures or components (8) and the vias (5) or contact pads (2) on the two wafers before/during/ after bonding, or the structures may be designed in a way that there is no alignment between the high aspect ration vias and the structures on the second wafer are required (e.g. if the structures (8) on the second wafer consist of un-patterned material film(s) (as shown in FIG.6d). In principle, other bonding techniques, such a eutectic bonding or plasma assisted direct bonding can also be used. Therefore, suitable bonding layers and surface preparation techniques will be required, prior to the bonding of the substrates. After the substrate bonding, at least one substrate is sacrificially removed using e.g. wafer grinding or etching processes or a combination of those, leaving the structures or parts of them on top of the thick film polymer layer(s) (4 and 15) with the embedded vias (5) on top of the second wafer as shown in FIG 6d, where the substrate (6) is sacrificially removed. For the sacrificial substrate removal, an etch-stop layer or a grinding stop-layer (7) can optionally be used. The structures (11) are then further processed (using semiconductor or other etching, patterning and/ or deposition processes), electrically connected to the vias and free etched as described and shown in FIG le-f.

FIG 7 shows another variation of the invention in which the thick film polymer layer (4) with the embedded vias (16) that are shorter than the thickness of the thick film polymer layer is used as the adhesive bonding agent. Providing components on a first wafer (1) manufactured by some standard type and cost efficient process, such as those methods commonly employed in application specific integrated circuit (ASIC) production, in IC foundries and/or in MEMS foundries. The components can for example be integrated electronic circuits, radio frequency circuits, pressure sensors, acceleration sensors, gyroscopes, micro-mirrors, thermal radiation sensor, (e.g. infrared bolometers), RF-MEMS devices or parts of these components (even a single material layer on the wafer). Providing components (8) on a second wafer (6) that are manufactured by some standard type and cost efficient process, such as those methods commonly employed in application specific integrated circuit (ASIC) production, in IC foundries and/ or in MEMS foundries. The components (8) can for example be integrated electronic circuits, radio frequency circuits, pressure sensors, acceleration sensors, gyroscopes, micro-mirrors, thermal radiation sensor, (e.g. infrared bolometers), RF-MEMS devices or parts of these components (even a single material layer on the wafer). The processes used for fabricating the components on the two separate wafers do not need to be compatible with each other. On one of the two wafers (1, 6) or on both wafers, a thick sacrificial material layer (e.g. a polymer film) (4) is deposited and patterned as shown in FIG 7b. Integrated high-aspect ratio vias (16) that connect to electrical contact pads (2) on the respective substrate are manufactured as shown in FIG 7c. The vias (16) are slightly shorter than the thick film polymer layer (4). The thick film polymer can be between 4 and > 100 μm thick and the patterned vias can be between 0.1 and > 500 μm in diameter. The two wafers (1, 6) can then be bonded to each other using the thick film polymer layer (4) with the embedded vias (16) as the adhesive or direct bonding agent. Thus, the distance between the devices on the substrates is defined by the thickness of the thick film polymer. There may be wafer-to-wafer alignment required between matching structures or components (8) and the vias (16) or contact pads (2) on the two wafers before/ during/ after bonding, or the structures may be designed in a way that there is no alignment between the high aspect ration vias and the structures on the second wafer are required (e.g. if the structures (8) on the second wafer consist of un-patterned material film(s) (e.g. shown in FIG.7d). In principle, other bonding techniques, such a eutectic bonding or plasma assisted direct bonding can also be used. Therefore, suitable bonding layers and surface preparation techniques will be required, prior to the bonding of the substrates. After the substrate bonding, at least one substrate is sacrificially removed using e.g. wafer grinding or etching processes or a combination of those, leaving the structures or parts of them on top of the thick film polymer layer(s) (4) with the embedded vias (16) on top of the second wafer as shown in FIG 7d, where the substrate (6) is sacrificially removed. For the sacrificial substrate removal, an etch-stop layer or a grinding stop-layer (7) could optionally be used, which is subsequently removed by a selective etching process. The structures (11) can then be further processed (using semiconductor or other etching, patterning and/ or deposition processes) as shown in FIG 7e. Before, during or after that the components are processed, another level of vias (10a) are defined and deposited as shown in FIG 2e, that electrically and and/or mechanically connect the high-aspect ratio vias (16) and the components on top (11). The vias (10a) can have a diameter of 0.01 to > 50 μm and a length of 0.1 to 20 μm. Finally, after the components (11) and the vias (10a) are manufactured, the intermediate thick film polymer layer (4) can optionally be sacrificially and selectively removed by wet or dry etching (e.g. in an oxygen plasma) as shown in FIG 7f.

FIG 8 shows another variation on how to create the vias that are embedded in the thick film sacrificial material layer (e.g. a polymer layer) used in the processes from FIG 1-3 and FIG 6-9. In this variation, the high aspect ratio vias (18) are manufactured using e.g. metal deposition and subsequent deep etching processes with a lithographically defined etching mask or patterning a photoresist mold plating the vias (18) and subsequent removal of the resist as shown in FIG 8c. Next, as shown in FIG.8d, a thick film polymer layer (19) is deposited (e.g. by spin coating, spray coating, stamping, screen printing or other techniques) and fully or partially cured. The polymer can be a thermoplastic polymer, a thermosetting polymer that is fully or partially cured (cross-linked), an elastomer that is fully or partially cured (cross-linked), or polymer alloys and blends that are fully or partially cured (cross-linked). The surface can then optionally planarized (or partially planarized by spin-coating an additional polymer layer, by grinding the surfaces (polymer and/ or vias), by chemical- mechanical-polishing the surfaces (polymer and/ or vias), by etching the surfaces (polymer and/or vias) or by other processes. The process for the via fabrication can be repeated (once or several times) on one or both of the wafers to create even higher aspect ratio vias. One reason for using two materials as described above, is that for certain situations different properties of e.g. the polymers in different stages of processing can be of advantage during the processing of the device.

FIG 9 shows another variation of the invention in which the devices (23) are manufactured on top of the thick film polymer layer (4) with the embedded vias (5) are manufactured using conventional surface micromachining techniques. Providing components on a first wafer (1) manufactured by some standard type and cost efficient process, such as those methods commonly employed in application specific integrated circuit (ASIC) production, in IC foundries and/ or in MEMS foundries. The components can for example be integrated electronic circuits, radio frequency circuits, pressure sensors, acceleration sensors, gyroscopes, micro-mirrors, thermal radiation sensor, (e.g. infrared bolometers), RF-MEMS devices or parts of these components (even a single material layer on the wafer). A thick polymer film (4) is deposited and patterned on the wafer (1) as shown in FIG 9b. Integrated high-aspect ratio vias (5) that connect to electrical contact pads (2) on the respective substrate are manufactured as shown in FIG 2c. The thick film polymer can be between 4 and > 100 μm thick and the patterned vias can be between 0.1 and > 500 μm in diameter. The process of via fabrication can be repeated to create even higher aspect ratio vias. The surface can then optionally be planarized by spin-coating an additional polymer layer (20), by grinding the surfaces, by chemical-mechanical-polishing the surfaces (polymer and/or vias), by etching the surfaces (polymer and/or vias) or by other processes. On top of the thick film polymer (4) with the integrated vias (5), structures can then be further deposited and processed using conventional surface micromachining techniques as shown in FIG 9d-f. Before, during or after that the components are deposited and processed, they are electrically and/or mechanically connected to the high aspect ratio vias (5). This can be done by fabricating another level of vias (22a) as shown in FIG 9e-f, that electrically and/or mechanically connect the high-aspect ratio vias (5) and the components (23). This can typically be done by via etching and metal deposition (e.g. electro-less plating, electroplating, sputtering or evaporation with subsequent patterning and etching). The vias (22a) can have a diameter of 0.01 to > 50 μm and a length of 0.1 to 20 μm. Finally, after the components and the vias are manufactured, the intermediate polymer layer(s) (4, 20) are sacrificially and selectively removed by wet or dry etching (e.g. in an oxygen plasma) as shown in FIG 9f.

FIG 10 shows two schematic variations of micro mirror (24) and infrared detector devices (28, 29, 30) for which the proposed invention can be used.

Using the proposed technology the distance d between the devices (24, 28, 29, 30) and the substrate (26) shown in FIG 10 can be increased and defined in order to achieve better device performance.

Claims

CLAIMS:

1. A method for making a MEMS device having connectors for interconnecting components in the MEMS device, comprising: applying a sacrificial material layer on a first substrate wafer, the thickness of the sacrificial layer essentially defining the length of the connectors; providing electrically conducting and/ or mechanically rigid connectors; providing components on top of the sacrificial layer by 3D integration with wafer bonding, to connect the components to the connectors.

2. The method as claimed in claim 1, further comprising removing the sacrificial layer to provide free-hanging structures attached to the substrate via the connectors.

3. The method as claimed in claim 1 or 2, wherein the thickness of the sacrificial layer is > 4μm.

4. The method as claimed in claim 1, 2 or 3, wherein the connectors have an aspect ratio, i.e. a length:width ratio of the order of > 3: 1.

5. The method as claimed in any preceding claim, wherein the length of the connectors is from 4μm up to 100 μm.

6. The method as claimed in any preceding claim, wherein the components provided on top of the sacrificial layer are provided on a second substrate wafer, which is bonded to the first substrate wafer with said wafer bonding.

7. The method as claimed in any preceding claim, wherein one of the substrates comprises integrated circuits.

8. The method as claimed in any preceding claim, wherein one of the substrates comprises sensors or actuators.

9. The method as claimed in any preceding claim, wherein the components comprise infrared detectors such as pyroelectric detectors, ferroelectric detectors, micro-bolometers or arrays of these type of detectors.

10. The method as claimed in any of claims 1-7, wherein the components comprise micro mirrors or micro mirror arrays such as torsional micro mirrors.

11. The method as claimed in any preceding claim, wherein the thick film sacrificial layer consists of a material selected from a partially or fully cured thermosetting polymer; photosensitive polymer such as photoresists; a thermoplastic polymer; a photosensitive polymer that is a fully or partially cured thermosetting polymer; or combinations thereof.

12. The method as claimed in any preceding claim, wherein the wafer bonding comprises coating one or both of the substrates to be bonded with a bonding agent.

13. The method as claimed in claim 12, wherein the bonding agent is selected from a patterned or non patterned polymer layer, such as a fully or partially cured thermosetting polymer layer, a thermoplastic polymer layer or a polymer blend layer.

14. The method as claimed in any of claims 1 to 11, wherein the thick film sacrificial layer with the embedded high aspect ratio vias is used as the bonding agent.

15. The method as claimed in claim 14, further comprising of creating electrical contacts between the connectors and the substrate at the same time as bonding the substrates with the help of the bonding agent.

16. The method as claimed in any preceding claim, wherein the sacrificial layer is a polymer layer.

17. The method of any preceding claim, wherein providing said electrically conducting and/ or mechanically rigid connectors comprises making holes in the sacrificial layer extending down to the substrate wafer and filling the holes with material forming said electrically conducting and/ or mechanically rigid connectors such that they are embedded in the sacrificial layer.

18. The method of any of claims 1-16, wherein providing said electrically conducting and/ or mechanically rigid connectors comprises metal deposition and subsequent deep etching processes with a lithographically defined etching mask; depositing a thick film polymer layer (19); and optionally planarizing the surface.

19. The method of any of claims 1-16, wherein providing said electrically conducting and/ or mechanically rigid connectors comprises patterning a photoresist mold and plating the vias (18) and subsequent removal of the resist; depositing a thick film polymer layer (19); and optionally planarizing the surface.

20. A MEMS device made by 3D integration with wafer bonding comprising first and a second components interconnected by connectors having a length of > 4μm.

21. A MEMS device as claimed in claim 20, wherein the length of the connectors is from 4μm up to 100 μm.

22. A MEMS device as claimed in claim 20 or 21, wherein the components comprise integrated circuits.

23. A MEMS device as claimed in any of claims 20-22, wherein the components comprise sensors or actuators.

24. A MEMS device as claimed in any of claims 20-23, wherein the components comprise infrared detectors such as pyroelectric detectors, ferroelectric detectors, micro-bolometers or arrays of these type of detectors.

25. A MEMS device as claimed in any of claims 20-24, wherein the components comprise micro mirrors or micro mirror arrays such as torsional micro mirrors.