Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
  • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
  • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
  • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • H01L21/8232—Field-effect technology
  • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
  • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
  • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
  • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
  • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
  • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • H01L21/8232—Field-effect technology
  • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
  • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
  • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

Definitions

• SEMICONDUCTOR DEVICE INCLUDING SHALLOW TRENCH ISOLATION (STI) REGIONS WITH A SUPERLATTICE THEREBETWEEN AND ASSOCIATED METHODS
• the present invention relates to the field of semiconductors, and, more particularly, to semiconductors having enhanced properties based upon energy band engineering and associated methods.
• U.S. Patent No. 6,472,685 B2 to Takagi discloses a semiconductor device including a silicon and carbon layer sandwiched between silicon layers so that the conduction band and valence band of the second silicon layer receive a tensile strain. Electrons having a smaller effective mass, and which have been induced by an electric field applied to the gate electrode, are confined in the second silicon layer, thus, an n-channel MOSFET is asserted to have a higher mobility.
• U.S. Patent No. 4,937,204 to Ishibashi et al discloses a superlattice in which a plurality of layers, less than eight monolayers, and containing a fractional or binary or a binary compound semiconductor layer, are alternately and epitaxially grown. The direction of main current flow is perpendicular to the layers of the superlattice .
• U.S. Patent No. 5,357,119 to Wang et al discloses a Si-Ge short period superlattice with higher mobility achieved by reducing alloy scattering in the superlattice.
• U.S. Patent No. 5,683,934 to Candelaria discloses an enhanced mobility MOSFET including a channel layer comprising an alloy of silicon and a second material substitutionally present in the silicon lattice at a percentage that places the channel layer under tensile stress.
• U.S. Patent No. 5,216,262 to Tsu discloses a quantum well structure comprising two barrier regions and a thin epitaxially grown semiconductor layer sandwiched between the barriers. Each barrier region consists of alternate layers of SiO 2 /Si with a thickness generally in a range of two to six monolayers. A much thicker section of silicon is sandwiched between the barriers.
• An article entitled "Phenomena in silicon nanostructure devices" also to Tsu and published online September 6, 2000 by Applied Physics and Materials Science & Processing, pp. 391-402 discloses a semiconductor-atomic superlattice (SAS) of silicon and oxygen. The Si/O superlattice is disclosed as useful in a silicon quantum and light-emitting devices.
• SAS semiconductor-atomic superlattice
• a green electromuminescence diode structure was constructed and tested. Current flow in the diode structure is vertical, that is, perpendicular to the layers of the SAS.
• the disclosed SAS may include semiconductor layers separated by adsorbed species such as oxygen atoms, and CO molecules. The silicon growth beyond the adsorbed monolayer of oxygen is described as epitaxial with a fairly low defect density.
• One SAS structure included a 1.1 nm thick silicon portion that is about eight atomic layers of silicon, and another structure had twice this thickness of silicon.
• a semiconductor device may include a semiconductor substrate and a plurality of shallow trench isolation (STI) regions in the substrate. More particularly, at least some of the STI regions may include divots therein. The semiconductor device may further include a respective superlattice between adjacent STI regions, and respective non-monocrystalline stringers in the divots .
• STI shallow trench isolation
• each of the non- monocrystalline stringers may have a dopant therein.
• the dopant may be a channel -stop implant dopant, for example.
• the semiconductor device may further include a plurality of NMOS and PMOS transistor channels associated with the superlattices so that the semiconductor device comprises a CMOS semiconductor device.
• each superlattice may include a plurality of stacked groups of layers with each group comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon.
• the at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent base semiconductor portions.
• the at least one non- semiconductor monolayer may be a single monolayer thick. Additionally, each base semiconductor portion may be less than eight monolayers thick.
• the superlattice may further include a base semiconductor cap layer on an uppermost group of layers. All of the base semiconductor portions may be a same number of monolayers thick in some embodiments, and in other embodiments at least some of the base semiconductor portions may be a different number of monolayers thick. Furthermore, all of the base semiconductor portions may be a different number of monolayers thick.
• Each base semiconductor portion may include a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors, for example.
• each non-semiconductor layer may include a non- semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.
• Another aspect relates to a method for making the semiconductor device .
• the method may include forming a plurality of shallow trench isolation (STI) regions in a semiconductor substrate. Further, a plurality of layers may be deposited over the substrate to define respective superlattices over the substrate between adjacent STI regions and to define respective non-monocrystalline regions over the STI regions .
• the method may further include selectively removing at least portions of the non-monocrystalline regions using at least one active area (AA) mask.
• AA active area
• the method may further include forming a plurality of NMOS and PMOS transistor channels associated with the superlattices so that the semiconductor device comprises a CMOS semiconductor device.
• selectively removing may include patterning a photoresist layer with the at least one AA mask to expose the non-monocrystalline regions, and performing at least one plasma etching of the exposed amorphous regions .
• the at least one AA mask may be a single baseline AA mask.
• the at least one AA mask may include a first oversized channel- stop AA mask for NMOS transistors, and a second oversized channel-stop AA mask for PMOS transistors.
• the method may further include performing a first channel-stop implant using the first oversized channel- stop AA mask, and performing a second channel -stop implant using the second oversized channel -stop AA mask.
• a first etch may be performed prior to the first channel-stop implant, and a second etch performed prior to the second channel-stop implant.
• non- monocrystalline stringers may be formed in divots in the STI regions, and at least a partial etch may be performed of the non-monocrystalline stringers.
• FIG. 1 is a cross-sectional view of a semiconductor device in accordance with the present invention including a superlattice.
• FIGS. 2A through 2D are cross-sectional views illustrating formation of the semiconductor device of FIG. 1 and potential difficulties associated therewith.
• FIG. 3 is a top view of a portion of the semiconductor device of FIG. 1 after gate electrode pattern and etch.
• FIG. 4 is a flow diagram illustrating a process flow for making the semiconductor device of FIG. 1.
• FIGS. 5A and 5B are top views of NFET and PFET channel-stop masks used in the method of FIG. 4.
• FIGS. 6A through 6B are cross-sectional views illustrating the masking and channel-stop implantation steps of the method of FIG. 4.
• FIG. 7 is a top view of the device structure after gate electrode pattern and etch, showing the device regions where the channel-stop implant is targeted to benefit, as part of the method of FIG. 4.
• FIGS. 8A through 8C are cross-sectional views illustrating the resist stripping, gate doping, spacer formation, and source/drain doping steps of the method of FIG. 4.
• FIG. 9 is a flow diagram illustrating an alternative process flow for making the semiconductor device of FIG. 1.
• FIGS. 1OA through 1OB are cross-sectional views illustrating the non-monocrystalline semiconductor etching, channel-stop implant, and gate deposition/implantation steps of the method of FIG. 9.
• FIG. 11 is a top view of the device structure after the spacer formation step of the method of FIG. 9.
• FIGS. 12A and 12B are cross-sectional views of the device structure after suicide formation taken parallel and perpendicular to the gate layer, respectively.
• FIGS. 13A and 13B are top views illustrating active area and tab channel-stop masking steps in accordance with another alternative process flow for making the semiconductor device of FIG. 1.
• FIG. 14 is a greatly enlarged schematic cross- sectional view of the superlattice as shown in FIG. 1.
• FIG. 15 is a perspective schematic atomic diagram of a portion of the superlattice shown in FIG. 14.
• FIG. 16 is a greatly enlarged schematic cross- sectional view of another embodiment of a superlattice that may be used in the device of FIG. 1.
• FIG. 17A is a graph of the calculated band structure from the gamma point (G) for both bulk silicon as in the prior art, and for the 4/1 Si/0 superlattice as shown in FIGS . 14.
• FIG. 17B is a graph of the calculated band structure from the Z point for both bulk silicon as in the prior art, and for the 4/1 Si/O superlattice as shown in FIG. 14.
• FIG. 17C is a graph of the calculated band structure from both the gamma and Z points for both bulk silicon as in the prior art, and for the 5/1/3/1 Si/0 superlattice as shown in FIG. 16.
• the present invention relates to controlling the properties of semiconductor materials at the atomic or molecular level to achieve improved performance within semiconductor devices. Further, the invention relates to the identification, creation, and use of improved materials for use in the conduction paths of semiconductor devices.
• f is the Fermi-Dirac distribution
• E F is the Fermi energy
• T is the temperature (Kelvin)
• E(k,n) is the energy of an electron in the state corresponding to wave vector k and the n th energy band
• the indices i and j refer to Cartesian coordinates x, y and z
• the integrals are taken over the Brillouin zone (B.Z.)
• the summations are taken over bands with energies above and below the Fermi energy for electrons and holes respectively.
• Applicants' definition of the conductivity reciprocal effective mass tensor is such that a tensorial component of the conductivity of the material is greater for greater values of the corresponding component of the conductivity reciprocal effective mass tensor.
• the superlattices described herein set the values of the conductivity reciprocal effective mass tensor so as to enhance the conductive properties of the material, such as typically for a preferred direction of charge carrier transport .
• the inverse of the appropriate tensor element is referred to as the conductivity effective mass.
• the conductivity effective mass for electrons/holes as described above and calculated in the direction of intended carrier transport is used to distinguish improved materials.
• the illustrated MOSFET 20 includes a substrate 21 with shallow trench isolation (STI) regions 80, 81 therein.
• the MOSFET device 20 may be a complementary MOS (CMOS) device including N and P-channel transistors with respective superlattice channels, in which the STI regions are for electrically insulating adjacent transistors, as will be appreciated by those skilled in the art.
• the substrate 21 may be a semiconductor (e.g., silicon) substrate or a silicon-on-insulator (SOI) substrate.
• the STI regions 80, 81 may include an oxide such as silicon dioxide, for example, although other suitable materials may be used in other embodiments.
• the MOSFET 20 further illustratively includes lightly doped source/drain extension regions 22, 23, more heavily doped source/drain regions 26, 27, and a channel region therebetween provided by the superlattice 25.
• Halo implant regions 42, 43 are illustratively included between the source and drain regions 26, 27 below the superlattice 25.
• Source/drain suicide layers 30, 31 overlie the source/drain regions, as will be appreciated by those skilled in the art.
• a gate 35 illustratively includes a gate dielectric layer 37 adjacent the channel provided by the superlattice 25, and a gate electrode layer 36 on the gate dielectric layer. Sidewall spacers 40, 41 are also provided in the illustrated MOSFET 20, as well as a suicide layer 34 on the gate electrode layer 36.
• Process integration of the superlattice 25 into state-of-the-art CMOS flow may require the removal of the superlattice film 25 that is formed over the STI regions 80, 81 to prevent shorting or leakage between adjacent device structures.
• fabrication may begin with the substrate 21 which has the STI regions 80, 81 formed therein as well as a sacrificial oxide layer 85 thereon and a V ⁇ implant 84 (represented by a row of "+" signs) .
• the silicon deposition results in non- monocrystalline (i.e., polycrystalline or amorphous) silicon deposits 86, 87 overlying the STI regions 80, 81.
• the non-monocrystalline silicon deposits 86, 87 typically need to be removed to prevent shorting or leakage between adjacent device structures, as noted above .
• the masking and etching operations may advantageously be modified to provide non- monocrystalline semiconductor stringers or unetched tabs 82, 83 with channel -stop implants in divots and edges of the STI regions 80, 81, as shown in FIG. 1.
• the non-monocrystalline semiconductor deposition occurs during the epitaxial growth of the semiconductor monolayers of the superlattice 25, which over the STI regions 80, 81 results in a non-monocrystalline silicon.
• the non-monocrystalline stringers 82, 83 are preferably advantageously doped with a channel-stop implant dopant, for example, as will be discussed further in the various fabrication examples set forth below.
• V ⁇ wells are implanted (through 150A pad oxide 85'), at Block 91, followed by a dry etch (120A oxide), at Block 92. This is followed by a hydrofluoric acid (HF) exposure (SCI/100 : 1, 50A), at Block 93.
• HF hydrofluoric acid
• the partial dry etch of the pad oxide 85' and relatively short HF exposure time may help to reduce the depth of the STI divots, for example.
• a first, oversized N channel AA mask is formed (FIGS. 5A and 6A), at Block 96, followed by a plasma etch of the non- monocrystalline semiconductor material over the STI regions adjacent the N-channel regions (Block 97) and an NFET channel-stop implant (FIG. 9B) using the oversized N channel AA mask, at Block 98.
• FIGS. 5A and 6A a first, oversized N channel AA mask is formed (FIGS. 5A and 6A), at Block 96, followed by a plasma etch of the non- monocrystalline semiconductor material over the STI regions adjacent the N-channel regions (Block 97) and an NFET channel-stop implant (FIG. 9B) using the oversized N channel AA mask, at Block 98.
• the N and P oversized masks are indicated with reference numerals 88n/ and 88p' , respectively, and the N and P active areas are indicated with reference numerals 21n' , 21p' , respectively.
• reverse N and P wells are indicated with reference numerals 79n' and 79p' , respectively.
• an over-sized P-channel mask is then formed (FIG. 5B), at Block 99, followed by a plasma etch of the non-monocrystalline silicon over the STI regions adjacent the P-channel region (Block 100) and the PFET channel-stop implantation, at Block 101.
• the NFET and PFET channel-stop implants are preferably performed at an angle or tilt, such as a thirty degree angle, for example, as illustrated in FIG. 6B, although other angles may also be used.
• the channel-stop implantations are illustratively shown with arrows in the drawings.
• boron may be used for the NFET channel-stop implant, and arsenic or phosphorous may be used for the PFET channel-stop implant.
• the stringers 82', 83' in the STI region 80', 81' divots and unetched silicon tabs at STI edges are preferably highly counter-doped by the channel-stop implant to neutralize or lessen the diffusion creep of dopants from source-drain regions into the non-monocrystalline silicon in the STI divots or tabs at the corner of the channel of the device to advantageously provide a higher diode break down voltage, higher threshold voltage and lower off current of this parasitic edge device.
• the use of two different oversized masks for the P and N channel devices advantageously helps protect the AA alignment marks during the non- monocrystalline silicon etching, as well as to protect each active device during channel stop implant of the opposite type of device.
• a pre-gate clean (SPM/HF/RCA) is performed, at Block 102 (FIG. 8A) , followed by gate oxide 37' formation (approximately 20A), at Block 103, and non- monocrystalline silicon gate electrode 36 deposition and implantation doping, at Block 104 (FIG. 8B) .
• Gate patterning and etching is then performed, at Block 105, followed by sidewall spacer 40', 41' formation (e.g., IOOA oxide) (Block 106) and LDD 22', 23 and halo 42', 43' implantations, at Block 107 (FIG. 8C).
• the spacers 40', 41' are then etched (e.g., 1900A oxide), at Block 108.
• the spacer 40, 41 formation is followed by the source/drain 26', 27' implants and annealing (e.g., 1000 0 C for 10 seconds), at Block 109, and silicide formation (Block 110) to provide the device 20 shown in FIG. 1.
• the silicide may be TiSi 2 (e.g., Ti deposition, germanium implant, RTA @ 690 0 C, selective strip, followed by RTA at 750 0 C) .
• FIGS. 12A and 12B are cross-sectional views of the device structure after silicide formation taken parallel and perpendicular to the gate layer 36' , respectively.
• the non-monocrystalline stringers 82', 83' are shown with stippling to indicate that they have been doped with the channel-stop implant. It should be noted that the depth of the silicon recess in the source/drain areas will depend upon the amount of over-etch used to remove the non-monocrystalline stringers and unetched tabs (due to use of oversized active-area channel-stop masks) 82', 83' in the STI divots and STI edges. Moreover, excessive recesses may lead to increased series RSD or loss of contact between the source/drain and the LDD regions, as will be appreciated by those skilled in the art. As such, these depths may require adjustment depending upon the given implantation.
• the illustrated method includes an NSD masking step (Block 122') , followed by an N+ gate implant and cap oxide deposition, at Blocks 123', 124'.
• NSD masking step Block 122'
• N+ gate implant and cap oxide deposition Blocks 123', 124'.
• Other process variations from the above-described approach include an etching of the non-monocrystalline silicon 86'', 87'' on the STI regions 80", 81" (e.g., 300A), at Block 125', followed by etching of the cap oxide layer (with a high selectivity to silicon) , at Block 126' .
• Those remaining process steps not specifically discussed here are similar to those discussed above with reference to FIG. 4.
• FIGS. 13A and 13B Yet another alternative process flow will now be described with reference to FIGS. 13A and 13B.
• This process flow uses a common oversized AA mask for etching the non-monocrystalline silicon 86' ' ' , 87"' on the STI regions 80''', 81''', followed by two separate masking steps for patterning tab openings. More particularly, an NFET channel-stop mask 13On'" and a PFET channel-stop mask 13Op'" are used (FIG. 13B) . The NFET and PFET masking steps are followed by channel-stop implantation steps to dope the non-monocrystalline silicon in the tab openings . The foregoing steps may be performed prior to gate oxidation.
• the exemplary process flows outlined above advantageously allow. the etching of the non-monocrystalline semiconductor material on the STI regions prior to gate oxide growth.
• the channel-stop implants with appropriate energy and dose would electrically neutralize dopant diffusion from adjacent source and drain regions into any unetched superlattice stringers inadvertently hiding in recessed STI divots at active area edges or tabs of the non-monocrystalline silicon on the STI oxide, surrounding the active area due to the over-sized active-area mask.
• suitable materials and process flow parameters besides the exemplary ones noted above may be used in different implementations .
• the superlattice 25 has a structure that is controlled at the atomic or molecular level and may be formed using known techniques of atomic or molecular layer deposition.
• the superlattice 25 includes a plurality of layer groups 45a-45n arranged in stacked relation, as noted above, as perhaps best understood with specific reference to the schematic cross-sectional view of FIG. 14.
• Each group of layers 45a-45n of the superlattice 25 illustratively includes a plurality of stacked base semiconductor monolayers 46 defining a respective base semiconductor portion 46a-46n and an energy band-modifying layer 50 thereon.
• the energy band- modifying layers 50 are indicated by stippling in FIG. 14 for clarity of illustration.
• the energy-band modifying layer 50 illustratively includes one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. That is, opposing base semiconductor monolayers 46 in adjacent groups of layers 45a-45n are chemically bound together. For example, in the case of silicon monolayers 46, some of the silicon atoms in the upper or top semiconductor monolayer of the group of monolayers 46a will be covalently bonded with silicon atoms in the lower or bottom monolayer of the group 46b. This allows the crystal lattice to continue through the groups of layers despite the presence of the non-semiconductor monolayer (s) (e.g., oxygen monolayer (s) ).
• s non-semiconductor monolayer
• more than one non- semiconductor layer monolayer may be possible.
• the number of non-semiconductor monolayers in the energy band-modifying layer 50 may preferably be less than about five monolayers to thereby provide desired energy band-modifying properties.
• non-semiconductor or semiconductor monolayer means that the material used for the monolayer would be a non- semiconductor or semiconductor if formed in bulk. That is, a single monolayer of a material, such as semiconductor, may not necessarily exhibit the same properties that it would if formed in bulk or in a relatively thick layer, as will be appreciated by those skilled in the art.
• energy band-modifying layers 50 and adjacent base semiconductor portions 46a-46n cause the superlattice 25 to have a lower appropriate conductivity effective mass for the charge carriers in the parallel layer direction than would otherwise be present.
• this parallel direction is orthogonal to the stacking direction.
• the band modifying layers 50 may also cause the superlattice 25 to have a common energy band structure, while also advantageously functioning as an insulator between layers or regions vertically above and below the superlattice.
• this structure also advantageously provides a barrier to dopant and/or material bleed or diffusion and to carrier flow between layers vertically above and below the superlattice 25.
• the superlattice 25 provides a higher charge carrier mobility based upon the lower conductivity effective mass than would otherwise be present.
• all of the above-described properties of the superlattice 25 need not be utilized in every application.
• the superlattice 25 may only be used for its dopant blocking/insulation properties or its enhanced mobility, or it may be used for both in other applications, as will be appreciated by those skilled in the art .
• a cap layer 52 is on an upper layer group 45n of the superlattice 25.
• the cap layer 52 may comprise a plurality of base semiconductor monolayers 46.
• the cap layer 52 may have between 2 to 100 monolayers of the base semiconductor, and, more preferably between 10 to 50 monolayers. Other thicknesses may be used as well.
• Each base semiconductor portion 46a-46n may comprise a base semiconductor selected from the group consisting of Group IV semiconductors, Group III -V semiconductors, and Group II -VI semiconductors.
• Group IV semiconductors also includes Group IV-IV semiconductors, as will be appreciated by those skilled in the art.
• the base semiconductor may comprise at least one of silicon and germanium, for example.
• Each energy band-modifying layer 50 may comprise a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon- oxygen, for example. The non-semiconductor is also desirably thermally stable through deposition of a next layer to thereby facilitate manufacturing.
• the non-semiconductor may be another inorganic or organic element or compound that is compatible with the given semiconductor processing, as will be appreciated by those skilled in the art.
• the term "monolayer” is meant to include a single atomic layer and also a single molecular layer.
• the energy band- modifying layer 50 provided by a single monolayer is also meant to include a monolayer wherein not all of the possible sites are occupied. For example, with particular reference to the atomic diagram of FIG. 15, a 4/1 repeating structure is illustrated for silicon as the base semiconductor material, and oxygen as the energy band-modifying material. Only half of the possible sites for oxygen are occupied.
• this one half occupation would not necessarily be the case as will be appreciated by those skilled in the art . Indeed it can be seen even in this schematic diagram, that individual atoms of oxygen in a given monolayer are not precisely aligned along a flat plane as will also be appreciated by those of skill in the art of atomic deposition. By way of example, a preferred occupation range is from about one-eighth to one-half of the possible oxygen sites being full, although other numbers may be used in certain embodiments. [0068] Silicon and oxygen are currently widely used in conventional semiconductor processing, and, hence, manufacturers will be readily able to use these materials as described herein. Atomic or monolayer deposition is also now widely used.
• semiconductor devices incorporating the superlattice 25 in accordance with the invention may be readily adopted and implemented, as will be appreciated by those skilled in the art.
• a superlattice such as the Si/O superlattice
• the number of silicon monolayers should desirably be seven or less so that the energy band of the superlattice is common or relatively uniform throughout to achieve the desired advantages.
• the 4/1 repeating structure shown in FIGS. 14 and 15, for Si/O has been modeled to indicate an enhanced mobility for electrons and holes in the X direction.
• the calculated conductivity effective mass for electrons is 0.26 and for the 4/1 SiO superlattice in the X direction it is 0.12 resulting in a ratio of 0.46.
• the calculation for holes yields values of 0.36 for bulk silicon and 0.16 for the 4/1 Si/O superlattice resulting in a ratio of 0.44.
• other devices may benefit from a more uniform increase in mobility in any direction parallel to the groups of layers. It may also be beneficial to have an increased mobility for both electrons and holes, or just one of these types of charge carriers, as will be appreciated by those skilled in the art. It may also be beneficial to have a decreased carrier mobility in a direction perpendicular to the groups of layers.
• the lower conductivity effective mass for the 4/1 Si/0 embodiment of the superlattice 25 may be less than two-thirds the conductivity effective mass than would otherwise occur, and this applies for both electrons and holes. It may be especially appropriate to dope some portion of the superlattice 25 in some embodiments, particularly when the superlattice is to provide a portion of a channel as in the device 20, for example. In other embodiments, it may be preferably to have one or more groups of layers 45 of the superlattice 25 substantially undoped depending upon its position within the device.
• FIG. 16 another embodiment of a superlattice 25' in accordance with the invention having different properties is now described.
• a repeating pattern of 3/1/5/1 is illustrated. More particularly, the lowest base semiconductor portion 46a' has three monolayers, and the second lowest base semiconductor portion 46b' has five monolayers. This pattern repeats throughout the superlattice 25' .
• the energy band-modifying layers 50' may each include a single monolayer.
• the enhancement of charge carrier mobility is independent of orientation in the plane of the layers.
• all of the base semiconductor portions 46a-46n of a superlattice 25 may ⁇ be a same number of monolayers thick. In other embodiments, at least some of the base semiconductor portions 46a-46n may be a different number of monolayers thick. In still other embodiments, all of the base semiconductor portions 46a-46n may be a different number of monolayers thick.
• FIGS. 17A-17C band structures calculated using Density Functional Theory (DFT) are presented. It is well known in the art that DFT underestimates the absolute value of the bandgap. Hence all bands above the gap may be shifted by an appropriate "scissors correction.” However the shape of the band is known to be much more reliable. The vertical energy axes should be interpreted in this light.
• DFT Density Functional Theory
• FIG. 17A shows the calculated band structure from the gamma point (G) for both bulk silicon (represented by continuous lines) and for the 4/1 Si/0 superlattice 25 as shown in FIG. 14 (represented by dotted lines) .
• the directions refer to the unit cell of the 4/1 Si/0 structure and not to the conventional unit cell of Si, although the (001) direction in the figure does correspond to the (001) direction of the conventional unit cell of Si, and, hence, shows the expected location of the Si conduction band minimum.
• the (100) and (010) directions in the figure correspond to the (110) and (-110) directions of the conventional Si unit cell.
• the bands of Si on the figure are folded to represent them on the appropriate reciprocal lattice directions for the 4/1 Si/0 structure.
• the conduction band minimum for the 4/1 Si/0 structure is located at the gamma point in contrast to bulk silicon (Si) , whereas the valence band minimum occurs at the edge of the Brillouin zone in the (001) direction which we refer to as the Z point.
• the greater curvature of the conduction band minimum for the 4/1 Si/O structure compared to the curvature of the conduction band minimum for Si owing to the band splitting due to the perturbation introduced by the additional oxygen layer.
• FIG. 17B shows the calculated band structure from the Z point for both bulk silicon (continuous lines) and for the 4/1 Si/0 superlattice 25 (dotted lines) of FIG. 14. This figure illustrates the enhanced curvature of the valence band in the (100) direction.
• FIG. 17C shows the calculated band structure from both the gamma and Z point for both bulk silicon (continuous lines) and for the 5/1/3/1 Si/O structure of the superlattice 25' of FIG. 16 (dotted lines) . Due to the symmetry of the 5/1/3/1 Si/O structure, the calculated band structures in the (100) and (010) directions are equivalent. Thus the conductivity effective mass and mobility are expected to be isotropic in the plane parallel to the layers, i.e.

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