EP1897132A4 - Method for fabricating shallow trenches - Google Patents

Method for fabricating shallow trenches

Info

Publication number
EP1897132A4
EP1897132A4 EP05789067.5A EP05789067A EP1897132A4 EP 1897132 A4 EP1897132 A4 EP 1897132A4 EP 05789067 A EP05789067 A EP 05789067A EP 1897132 A4 EP1897132 A4 EP 1897132A4
Authority
EP
European Patent Office
Prior art keywords
shallow trenches
fabricating shallow
fabricating
trenches
shallow
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP05789067.5A
Other languages
German (de)
French (fr)
Other versions
EP1897132A1 (en
Inventor
Ya-Hong Xie
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of California
Original Assignee
University of California
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/169,243 external-priority patent/US7045437B1/en
Application filed by University of California filed Critical University of California
Priority claimed from PCT/US2005/022673 external-priority patent/WO2007001297A1/en
Publication of EP1897132A1 publication Critical patent/EP1897132A1/en
Publication of EP1897132A4 publication Critical patent/EP1897132A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76227—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials the dielectric materials being obtained by full chemical transformation of non-dielectric materials, such as polycristalline silicon, metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76245—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using full isolation by porous oxide silicon, i.e. FIPOS techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
EP05789067.5A 2005-06-27 2005-06-28 Method for fabricating shallow trenches Withdrawn EP1897132A4 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/169,243 US7045437B1 (en) 2005-06-27 2005-06-27 Method for fabricating shallow trenches
PCT/US2005/022673 WO2007001297A1 (en) 2005-06-27 2005-06-28 Method for fabricating shallow trenches

Publications (2)

Publication Number Publication Date
EP1897132A1 EP1897132A1 (en) 2008-03-12
EP1897132A4 true EP1897132A4 (en) 2014-11-26

Family

ID=40445211

Family Applications (1)

Application Number Title Priority Date Filing Date
EP05789067.5A Withdrawn EP1897132A4 (en) 2005-06-27 2005-06-28 Method for fabricating shallow trenches

Country Status (2)

Country Link
EP (1) EP1897132A4 (en)
JP (1) JP2009508323A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7858503B2 (en) * 2009-02-06 2010-12-28 Applied Materials, Inc. Ion implanted substrate having capping layer and method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61180449A (en) * 1985-02-05 1986-08-13 Toko Inc Dielectric-isolated semiconductor integrated circuit substrate and manufacture thereof
WO2002045146A1 (en) * 2000-11-30 2002-06-06 Telephus, Inc. Fabrication method of selectively oxidized porous silicon (sops) layer and multi-chip package using the same
US6437417B1 (en) * 2000-08-16 2002-08-20 Micron Technology, Inc. Method for making shallow trenches for isolation

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5311438B2 (en) * 1974-04-30 1978-04-21
JPS51279A (en) * 1974-06-18 1976-01-05 Matsushita Electric Ind Co Ltd HANDOTAISHUSEKIKAIROKITAINO SEIZOHOHO
JPS6094738A (en) * 1983-10-28 1985-05-27 Matsushita Electric Works Ltd Semiconductor substrate
JPS60138937A (en) * 1983-12-27 1985-07-23 Toko Inc Substrate for integrated circuit
US6103590A (en) * 1997-12-12 2000-08-15 Texas Instruments Incorporated SiC patterning of porous silicon
US6376859B1 (en) * 1998-07-29 2002-04-23 Texas Instruments Incorporated Variable porosity porous silicon isolation

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61180449A (en) * 1985-02-05 1986-08-13 Toko Inc Dielectric-isolated semiconductor integrated circuit substrate and manufacture thereof
US6437417B1 (en) * 2000-08-16 2002-08-20 Micron Technology, Inc. Method for making shallow trenches for isolation
WO2002045146A1 (en) * 2000-11-30 2002-06-06 Telephus, Inc. Fabrication method of selectively oxidized porous silicon (sops) layer and multi-chip package using the same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2007001297A1 *

Also Published As

Publication number Publication date
JP2009508323A (en) 2009-02-26
EP1897132A1 (en) 2008-03-12

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Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

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17P Request for examination filed

Effective date: 20071121

AK Designated contracting states

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Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU MC NL PL PT RO SE SI SK TR

DAX Request for extension of the european patent (deleted)
A4 Supplementary search report drawn up and despatched

Effective date: 20141024

RIC1 Information provided on ipc code assigned before grant

Ipc: H01L 21/762 20060101ALI20141020BHEP

Ipc: H01L 21/76 20060101AFI20141020BHEP

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20150106