EP1844548A2 - Device comprising a latch - Google Patents

Device comprising a latch

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Publication number
EP1844548A2
EP1844548A2 EP06710725A EP06710725A EP1844548A2 EP 1844548 A2 EP1844548 A2 EP 1844548A2 EP 06710725 A EP06710725 A EP 06710725A EP 06710725 A EP06710725 A EP 06710725A EP 1844548 A2 EP1844548 A2 EP 1844548A2
Authority
EP
European Patent Office
Prior art keywords
latch
deciding
coupled
tracking
transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP06710725A
Other languages
German (de)
French (fr)
Inventor
Mihai A. T. Sanduleanu
Eduard F. Stikvoort
Antoon M. H. Tombeur
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Priority to EP06710725A priority Critical patent/EP1844548A2/en
Publication of EP1844548A2 publication Critical patent/EP1844548A2/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
    • H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
    • H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
    • H03K3/286—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable
    • H03K3/288—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable using additional transistors in the input circuit
    • H03K3/2885—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable using additional transistors in the input circuit the input circuit having a differential configuration

Definitions

  • the invention relates to a device comprising a latch, and also relates to a latch, and to a method.
  • Examples of such a device are blocks such as dividers, shift registers, generators, multiplexers, demultiplexers and parts of phase locked loops, and consumer products comprising such blocks, and examples of such a latch are so-called D-latches.
  • CMOS CML buffers and latches A prior art device is known from the article "Design of Ultra High Speed CMOS CML buffers and latches", by Payam Heydari and Ravi Mohavavelu, ISCAS '03, Proceedings of the 2003 International Symposium on Circuits and Systems, Volume 2, 25-28 May 2003, 0-7803-7761-3/03/$17.00 ⁇ 2003IEEE, which discloses in its Fig. 6 a latch comprising an input tracking stage (transistors MN1,MN2) for, in a track mode, tracking a data variation and comprising a latch pair (transistors MN3,MN4) for, in a latch mode, storing the data.
  • the track and latch modes are determined by a clock signal supplied to a differential pair (transistors MN5,MN6). In the track mode, the input tracking stage is enabled and the latch pair is disabled, and in the latch mode, the input tracking stage is disabled and the latch pair is enabled.
  • the known device is disadvantageous, inter alia, owing to the fact that the latch uses the available time relatively inefficiently. This results from the fact that the latch pair needs to be switched from a disabled situation into an enabled situation and that, in the disabled situation, the latch pair is not doing anything.
  • objects of the invention are, inter alia, to provide a latch and a method which use the available time relatively efficiently.
  • the device comprises a latch, which latch comprises a tracking circuit for, in a tracking mode, tracking a data signal and which latch comprises a deciding circuit for, in a deciding mode, deciding about the data signal, the latch being arranged to, in the tracking mode, prepare the deciding circuit.
  • the latch uses the available time more efficiently.
  • the deciding circuit is not to be switched between a disabled situation and an enabled situation, but is to be kept in the enabled situation.
  • An embodiment of the device according to the invention is defined by the tracking circuit being arranged to, in the tracking mode, supply a signal value derived from the data signal to the deciding circuit, and the deciding circuit being arranged to, in the deciding mode, amplify the signal value.
  • the deciding circuit In the tracking mode, the deciding circuit has a relatively low or a zero amplification, and in the deciding mode, the deciding circuit has a relatively high amplification.
  • An embodiment of the device according to the invention is defined by the tracking circuit comprising a capacitance for storing the signal value.
  • the capacitance stores the signal value and informs the deciding circuit of this signal value.
  • An embodiment of the device according to the invention is defined by the deciding circuit comprising a first transistor and a second transistor, first main electrodes of the first and second transistors being coupled to each other and second main electrodes of the respective first and second transistors being coupled to control electrodes of the respective second and first transistors.
  • This is a construction also known as latching circuit or latch pair.
  • An embodiment of the device according to the invention is defined by the tracking circuit comprising a first diode and a second diode, first main electrodes of the first and second diodes being coupled to each other and second main electrodes of the respective first and second diodes being coupled to the control electrodes of the respective first and second transistors and constituting respective first and second data inputs of the latch.
  • This is an advantageous construction owing to the fact that, compared to the prior art, between the data inputs of the latch a reduced voltage swing is sufficient for a proper performance of the latch. Such a reduced voltage swing allows the latch to perform at a higher speed.
  • the parasitic capacitor present between both second main electrodes of the diodes forms the capacitance for storing the signal value.
  • the respective first and second data inputs of the latch are for example a D+ and a D- input (balanced situation) and receive the data signal.
  • An embodiment of the device according to the invention is defined by the second main electrodes of the respective first and second diodes being coupled via respective first and second resistors and respective first and second current sources to a voltage supply. These current sources allow a compensation for performance loss at higher temperatures by automatically adjusting the currents of the current sources in dependence of the temperature.
  • An embodiment of the device according to the invention is defined by the control electrodes of the respective first and second transistors being coupled to control electrodes of respective third and fourth transistors, first main electrodes of the third and fourth transistors being coupled to each other and second main electrodes of the respective third and fourth transistors constituting respective first and second data outputs of the latch.
  • the respective first and second data outputs of the latch are for example a Q- and a Q+ output (balanced situation) and generate an output signal.
  • An embodiment of the device according to the invention is defined by the control electrodes of the respective first and second transistors being coupled to control electrodes of respective fifth and sixth transistors, first main electrodes of the fifth and sixth transistors being coupled to each other and second main electrodes of the respective fifth and sixth transistors being coupled via respective third and fourth resistors to a voltage supply and constituting respective third and fourth data outputs of the latch.
  • the respective third and fourth data outputs of the latch are for example an OUT- and an OUT+ output (balanced situation) and generate a further output signal. The isolation between these outputs and the data inputs prevents that the latch is loaded with parasitic capacitances of a load.
  • An embodiment of the device according to the invention is defined by the second main electrodes of the respective first and second diodes being coupled via respective first and second resistors and respective fifth and sixth resistors to a voltage supply, a common point of the first and fifth resistors constituting a third data output of the latch and a common point of the second and sixth resistors constituting a fourth data output of the latch.
  • the fifth and sixth resistors replace the current sources and allow, compared to the embodiment with the current sources, between the data inputs of the latch a further reduced voltage swing for a proper performance of the latch. Such a further reduced voltage swing allows the latch to perform at a further higher speed.
  • An embodiment of the device according to the invention is defined by the first main electrodes of the diodes further being coupled to a second main electrode of a seventh transistor, a first main electrode of the seventh transistor being coupled to ground and a control electrode of the seventh transistor constituting a first clock input of the latch, the first main electrodes of the third and fourth transistors further being coupled to a second main electrode of an eighth transistor, a first main electrode of the eighth transistor being coupled to ground and a control electrode of the eighth transistor constituting a second clock input of the latch.
  • the first clock input is for example a CK+ input and the second clock input is for example a CK- input (balanced situation) for receiving a clock signal.
  • An embodiment of the device according to the invention is defined by the first main electrodes of the first and second transistors further being coupled to a second main electrode of a ninth transistor, a first main electrode of the ninth transistor being coupled to ground and a control electrode of the ninth transistor being coupled to the second clock input of the latch.
  • Embodiments of the latch according to the invention and of the method according to the invention correspond with the embodiments of the device according to the invention. Further embodiments related to non-balanced situations are not to be excluded.
  • the invention is based upon an insight, inter alia, that it takes time to switch a deciding circuit or latching circuit on and off, and is based upon a basic idea, inter alia, that in the tracking mode, the deciding circuit is not to be kept disabled, but is to be kept enabled, just like in the deciding mode.
  • the invention solves the problem, inter alia, to provide a device comprising a latch which uses the available time relatively efficiently, and is advantageous, inter alia, in that the latch can be used at a higher speed.
  • Fig. 1 shows diagrammatically a device according to the invention comprising a latch according to the invention
  • Fig. 2 shows diagrammatically a device according to the invention comprising a latch according to the invention
  • Fig. 3 shows diagrammatically a device according to the invention comprising a latch according to the invention
  • Fig. 4 shows diagrammatically a device according to the invention in the form of a divider comprising two latches according to the invention
  • Fig. 5 shows diagrammatically a device according to the invention in the form of a D-flipflop comprising two latches according to the invention.
  • the device 101 according to the invention as shown in Fig. 1 comprises a latch 1 according to the invention.
  • the latch 1 comprises a tracking circuit 4 for, in a tracking mode, tracking a data signal and comprises a deciding circuit 5 for, in a deciding mode, deciding about the data signal.
  • the deciding circuit 5 comprises a first transistor 11 and a second transistor 12, first main electrodes (electrodes) of the first and second transistors 11,12 being coupled to each other and to ground and second main electrodes (collectors) of the respective first and second transistors 11,12 being coupled to control electrodes (basis) of the respective second and first transistors 11,12.
  • the tracking circuit 4 comprises a first diode 21 and a second diode 22, first main electrodes (anodes) of the first and second diodes 21,22 being coupled to each other and second main electrodes (cathodes) of the respective first and second diodes 21,22 being coupled to the control electrodes of the respective first and second transistors 11,12 and constituting respective first and second data inputs 31,32 (D+,D-) of the latch 1 for receiving the data signal.
  • the first diode 21 and the second diode 22 are in fact transistors of which the collectors and the basis are coupled to each other.
  • the second main electrodes of the respective first and second diodes 21,22 are coupled via respective first and second resistors 23,24 and respective first and second current sources 25,26 to a voltage supply 40.
  • control electrodes of the respective first and second transistors 11,12 are coupled to control electrodes (basis) of respective third and fourth transistors 13,14, first main electrodes (electrodes) of the third and fourth transistors 13,14 being coupled to each other and second main electrodes (collectors) of the respective third and fourth transistors 13,14 constituting respective first and second data outputs 33,34 (Q-,Q+) of the latch 1 for generating an output signal.
  • the control electrodes of the respective first and second transistors 11,12 are coupled to control electrodes (basis) of respective fifth and sixth transistors 15,16, first main electrodes (electrodes) of the fifth and sixth transistors 15,16 being coupled to each other and second main electrodes (collectors) of the respective fifth and sixth transistors 15,16 being coupled via respective third and fourth resistors 27,28 to a voltage supply 40 and constituting respective third and fourth data outputs 35,36 (OUT-,OUT+) of the latch 1 for generating a further output signal.
  • the first main electrodes of the diodes 21,22 further are coupled to a second main electrode (collector) of a seventh transistor 17, a first main electrode (emitter) of the seventh transistor 17 being coupled to ground and a control electrode (basis) of the seventh transistor 17 constituting a first clock input 37 (CK+) of the latch 1, the first main electrodes of the third and fourth transistors 13,14 further being coupled to a second main electrode (collector) of an eighth transistor 18, a first main electrode (emitter) of the eighth transistor 18 being coupled to ground and a control electrode (basis) of the eighth transistor 18 constituting a second clock input 38 (CK-) of the latch 1.
  • the clock inputs 37,38 receive a clock signal.
  • the device 102 according to the invention as shown in Fig. 2 comprises a latch 2 according to the invention which corresponds with the latch 1 shown in Fig. 1, apart from the following.
  • the first main electrodes of the first and second transistors 11,12 further are coupled to a second main electrode (collector) of a ninth transistor 19, a first main electrode (emitter) of the ninth transistor 19 being coupled to ground and a control electrode (basis) of the ninth transistor 19 being coupled to the second clock input 38 of the latch 2.
  • the device 103 according to the invention as shown in Fig. 3 comprises a latch 3 according to the invention which corresponds with the latch 2 shown in Fig. 2, apart from the following.
  • the current sources 25,26 are replaced by fifth and sixth resistors 29,30, a common point of the first and fifth resistors 23,29 constituting a third data output 35 (OUT-) of the latch 3 and a common point of the second and sixth resistors 24,30 constituting a fourth data output 36 (OUT+) of the latch 3.
  • the latch 1-3 is arranged to, in the tracking mode, prepare the deciding circuit 5, for example as follows.
  • the tracking circuit 4 supplies, in the tracking mode, a signal value derived from the data signal as supplied to the data inputs 31 ,32 to the deciding circuit 5, and the deciding circuit 5 amplifies, in the deciding mode, the signal value.
  • This signal value is for example a voltage stored across a capacitance of the tracking circuit 4.
  • This capacitance is for example realized via the parasitic capacitor present between the cathodes of the diodes 21,22. So, by already preparing the deciding circuit 5 in the tracking mode, the latch 1-3 uses the available time more efficiently.
  • the deciding circuit 5 is not to be switched between a disabled situation and an enabled situation, but is to be kept in the enabled situation.
  • the tracking circuit 4 comprising the diodes 21,22 forms an advantageous construction owing to the fact that, compared to the prior art, between the data inputs 31,32 of the latch 1-3 a reduced voltage swing is sufficient for a proper performance of the latch 1- 3. Such a reduced voltage swing allows the latch 1-3 to perform at a higher speed.
  • the current sources 25,26 shown in Fig. 1 and 2 allow a compensation for performance loss at higher temperatures by automatically adjusting the currents of the current sources in dependence of the temperature.
  • the fifth and sixth resistors 29,30 shown in Fig. 3 replace the current sources 25,26 of Fig. 1 and 2 and allow, compared to the embodiment with the current sources 25,26, between the data inputs 31,32 of the latch 3 a further reduced voltage swing for a proper performance of the latch 3. Such a further reduced voltage swing allows the latch 3 to perform at a further higher speed.
  • the clock input signals to be supplied to the clock inputs 37,38 result in the latch 1-3 being brought into the tracking mode or into the deciding mode.
  • the transistor 19 shown in Fig. 2 and 3 allows the deciding circuit 5 to be clocked, which is an advantage in case of using the latch 2 and 3 in a multiplexer or a generator environment.
  • the device 104 according to the invention in the form of a divider (a divide- by-two-divider or prescaler) shown in Fig. 4 comprises two latches 1-3 with outputs of a first latch being coupled to inputs of a second latch and with outputs of the second latch being fed back to inputs of the first latch.
  • a divider a divide- by-two-divider or prescaler
  • the device 105 according to the invention in the form of a D-flipflop shown in Fig. 5 comprises two latches 1-3 with outputs of a first latch being coupled to inputs of a second latch and with outputs of the second latch now not being fed back to inputs of the first latch. Instead of that, the inputs of the first latch form the inputs of the D-flipflop and the outputs of the second latch form the outputs of the D-flipflop.
  • the transistors shown are NPN bipolar transistors, alternatively PNP bipolar transistors might be used, further alternatively Field Effect Transistors might be used, such as NMOS or PMOS transistors. Further embodiments related to non-balanced situations are not to be excluded.

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  • Power Engineering (AREA)
  • Logic Circuits (AREA)
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Abstract

Devices (101-105) comprising latches (1-3) with tracking circuits (4) for, in tracking modes, tracking data signals and with deciding circuits (5) for, in deciding modes, deciding about the data signal can use their available time more efficiently by, in the tracking modes, preparing the deciding circuits (5). Thereto, the deciding circuits (5) are not to be switched between disabled/enabled situations, but are to be kept enabled. The tracking circuits (4), in the tracking modes, supply signal values derived from the data signals to the deciding circuits (5), and the deciding circuits (5), in the deciding modes, amplify the signal values. The tracking circuits (4) comprise diodes (21,22) to allow reduced voltage swings in the data signals to be sufficient for proper performances of the latch (1-3). Such reduced voltage swings allow the latches (1-3) to perform at higher speeds. The parasitic capacitors present between the cathodes of the diodes (21,22) form capacitances for storing the signal values and allow the deciding circuits (5) to be prepared.

Description

Device comprising a latch
The invention relates to a device comprising a latch, and also relates to a latch, and to a method.
Examples of such a device are blocks such as dividers, shift registers, generators, multiplexers, demultiplexers and parts of phase locked loops, and consumer products comprising such blocks, and examples of such a latch are so-called D-latches.
A prior art device is known from the article "Design of Ultra High Speed CMOS CML buffers and latches", by Payam Heydari and Ravi Mohavavelu, ISCAS '03, Proceedings of the 2003 International Symposium on Circuits and Systems, Volume 2, 25-28 May 2003, 0-7803-7761-3/03/$17.00©2003IEEE, which discloses in its Fig. 6 a latch comprising an input tracking stage (transistors MN1,MN2) for, in a track mode, tracking a data variation and comprising a latch pair (transistors MN3,MN4) for, in a latch mode, storing the data. The track and latch modes are determined by a clock signal supplied to a differential pair (transistors MN5,MN6). In the track mode, the input tracking stage is enabled and the latch pair is disabled, and in the latch mode, the input tracking stage is disabled and the latch pair is enabled.
The known device is disadvantageous, inter alia, owing to the fact that the latch uses the available time relatively inefficiently. This results from the fact that the latch pair needs to be switched from a disabled situation into an enabled situation and that, in the disabled situation, the latch pair is not doing anything.
It is an object of the invention, inter alia, to provide a device comprising a latch which uses the available time relatively efficiently.
Furthers objects of the invention are, inter alia, to provide a latch and a method which use the available time relatively efficiently.
The device according to the invention comprises a latch, which latch comprises a tracking circuit for, in a tracking mode, tracking a data signal and which latch comprises a deciding circuit for, in a deciding mode, deciding about the data signal, the latch being arranged to, in the tracking mode, prepare the deciding circuit.
By already preparing the deciding circuit (latching circuit) in the tracking mode, the latch uses the available time more efficiently. To be able to prepare the deciding circuit, the deciding circuit is not to be switched between a disabled situation and an enabled situation, but is to be kept in the enabled situation.
An embodiment of the device according to the invention is defined by the tracking circuit being arranged to, in the tracking mode, supply a signal value derived from the data signal to the deciding circuit, and the deciding circuit being arranged to, in the deciding mode, amplify the signal value. In the tracking mode, the deciding circuit has a relatively low or a zero amplification, and in the deciding mode, the deciding circuit has a relatively high amplification.
An embodiment of the device according to the invention is defined by the tracking circuit comprising a capacitance for storing the signal value. The capacitance stores the signal value and informs the deciding circuit of this signal value.
An embodiment of the device according to the invention is defined by the deciding circuit comprising a first transistor and a second transistor, first main electrodes of the first and second transistors being coupled to each other and second main electrodes of the respective first and second transistors being coupled to control electrodes of the respective second and first transistors. This is a construction also known as latching circuit or latch pair.
An embodiment of the device according to the invention is defined by the tracking circuit comprising a first diode and a second diode, first main electrodes of the first and second diodes being coupled to each other and second main electrodes of the respective first and second diodes being coupled to the control electrodes of the respective first and second transistors and constituting respective first and second data inputs of the latch. This is an advantageous construction owing to the fact that, compared to the prior art, between the data inputs of the latch a reduced voltage swing is sufficient for a proper performance of the latch. Such a reduced voltage swing allows the latch to perform at a higher speed. The parasitic capacitor present between both second main electrodes of the diodes forms the capacitance for storing the signal value. The respective first and second data inputs of the latch are for example a D+ and a D- input (balanced situation) and receive the data signal.
An embodiment of the device according to the invention is defined by the second main electrodes of the respective first and second diodes being coupled via respective first and second resistors and respective first and second current sources to a voltage supply. These current sources allow a compensation for performance loss at higher temperatures by automatically adjusting the currents of the current sources in dependence of the temperature.
An embodiment of the device according to the invention is defined by the control electrodes of the respective first and second transistors being coupled to control electrodes of respective third and fourth transistors, first main electrodes of the third and fourth transistors being coupled to each other and second main electrodes of the respective third and fourth transistors constituting respective first and second data outputs of the latch. The respective first and second data outputs of the latch are for example a Q- and a Q+ output (balanced situation) and generate an output signal. An embodiment of the device according to the invention is defined by the control electrodes of the respective first and second transistors being coupled to control electrodes of respective fifth and sixth transistors, first main electrodes of the fifth and sixth transistors being coupled to each other and second main electrodes of the respective fifth and sixth transistors being coupled via respective third and fourth resistors to a voltage supply and constituting respective third and fourth data outputs of the latch. The respective third and fourth data outputs of the latch are for example an OUT- and an OUT+ output (balanced situation) and generate a further output signal. The isolation between these outputs and the data inputs prevents that the latch is loaded with parasitic capacitances of a load.
An embodiment of the device according to the invention is defined by the second main electrodes of the respective first and second diodes being coupled via respective first and second resistors and respective fifth and sixth resistors to a voltage supply, a common point of the first and fifth resistors constituting a third data output of the latch and a common point of the second and sixth resistors constituting a fourth data output of the latch. The fifth and sixth resistors replace the current sources and allow, compared to the embodiment with the current sources, between the data inputs of the latch a further reduced voltage swing for a proper performance of the latch. Such a further reduced voltage swing allows the latch to perform at a further higher speed.
An embodiment of the device according to the invention is defined by the first main electrodes of the diodes further being coupled to a second main electrode of a seventh transistor, a first main electrode of the seventh transistor being coupled to ground and a control electrode of the seventh transistor constituting a first clock input of the latch, the first main electrodes of the third and fourth transistors further being coupled to a second main electrode of an eighth transistor, a first main electrode of the eighth transistor being coupled to ground and a control electrode of the eighth transistor constituting a second clock input of the latch. The first clock input is for example a CK+ input and the second clock input is for example a CK- input (balanced situation) for receiving a clock signal. Clock input signals at these clock inputs result in the latch being brought into the tracking mode or into the deciding mode. An embodiment of the device according to the invention is defined by the first main electrodes of the first and second transistors further being coupled to a second main electrode of a ninth transistor, a first main electrode of the ninth transistor being coupled to ground and a control electrode of the ninth transistor being coupled to the second clock input of the latch. This construction, compared to an embodiment according to which the first main electrodes of the first and second transistors are coupled to ground, allows the deciding circuit to be clocked, which is an advantage in case of using the latch in a multiplexer or a generator environment.
Embodiments of the latch according to the invention and of the method according to the invention correspond with the embodiments of the device according to the invention. Further embodiments related to non-balanced situations are not to be excluded.
The invention is based upon an insight, inter alia, that it takes time to switch a deciding circuit or latching circuit on and off, and is based upon a basic idea, inter alia, that in the tracking mode, the deciding circuit is not to be kept disabled, but is to be kept enabled, just like in the deciding mode. The invention solves the problem, inter alia, to provide a device comprising a latch which uses the available time relatively efficiently, and is advantageous, inter alia, in that the latch can be used at a higher speed.
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments(s) described hereinafter.
In the drawings:
Fig. 1 shows diagrammatically a device according to the invention comprising a latch according to the invention, Fig. 2 shows diagrammatically a device according to the invention comprising a latch according to the invention,
Fig. 3 shows diagrammatically a device according to the invention comprising a latch according to the invention, Fig. 4 shows diagrammatically a device according to the invention in the form of a divider comprising two latches according to the invention, and
Fig. 5 shows diagrammatically a device according to the invention in the form of a D-flipflop comprising two latches according to the invention.
The device 101 according to the invention as shown in Fig. 1 comprises a latch 1 according to the invention. The latch 1 comprises a tracking circuit 4 for, in a tracking mode, tracking a data signal and comprises a deciding circuit 5 for, in a deciding mode, deciding about the data signal.
The deciding circuit 5 comprises a first transistor 11 and a second transistor 12, first main electrodes (electrodes) of the first and second transistors 11,12 being coupled to each other and to ground and second main electrodes (collectors) of the respective first and second transistors 11,12 being coupled to control electrodes (basis) of the respective second and first transistors 11,12.
The tracking circuit 4 comprises a first diode 21 and a second diode 22, first main electrodes (anodes) of the first and second diodes 21,22 being coupled to each other and second main electrodes (cathodes) of the respective first and second diodes 21,22 being coupled to the control electrodes of the respective first and second transistors 11,12 and constituting respective first and second data inputs 31,32 (D+,D-) of the latch 1 for receiving the data signal. The first diode 21 and the second diode 22 are in fact transistors of which the collectors and the basis are coupled to each other.
The second main electrodes of the respective first and second diodes 21,22 are coupled via respective first and second resistors 23,24 and respective first and second current sources 25,26 to a voltage supply 40.
The control electrodes of the respective first and second transistors 11,12 are coupled to control electrodes (basis) of respective third and fourth transistors 13,14, first main electrodes (electrodes) of the third and fourth transistors 13,14 being coupled to each other and second main electrodes (collectors) of the respective third and fourth transistors 13,14 constituting respective first and second data outputs 33,34 (Q-,Q+) of the latch 1 for generating an output signal.
The control electrodes of the respective first and second transistors 11,12 are coupled to control electrodes (basis) of respective fifth and sixth transistors 15,16, first main electrodes (electrodes) of the fifth and sixth transistors 15,16 being coupled to each other and second main electrodes (collectors) of the respective fifth and sixth transistors 15,16 being coupled via respective third and fourth resistors 27,28 to a voltage supply 40 and constituting respective third and fourth data outputs 35,36 (OUT-,OUT+) of the latch 1 for generating a further output signal. The first main electrodes of the diodes 21,22 further are coupled to a second main electrode (collector) of a seventh transistor 17, a first main electrode (emitter) of the seventh transistor 17 being coupled to ground and a control electrode (basis) of the seventh transistor 17 constituting a first clock input 37 (CK+) of the latch 1, the first main electrodes of the third and fourth transistors 13,14 further being coupled to a second main electrode (collector) of an eighth transistor 18, a first main electrode (emitter) of the eighth transistor 18 being coupled to ground and a control electrode (basis) of the eighth transistor 18 constituting a second clock input 38 (CK-) of the latch 1. The clock inputs 37,38 receive a clock signal.
The device 102 according to the invention as shown in Fig. 2 comprises a latch 2 according to the invention which corresponds with the latch 1 shown in Fig. 1, apart from the following.
The first main electrodes of the first and second transistors 11,12 further are coupled to a second main electrode (collector) of a ninth transistor 19, a first main electrode (emitter) of the ninth transistor 19 being coupled to ground and a control electrode (basis) of the ninth transistor 19 being coupled to the second clock input 38 of the latch 2.
The device 103 according to the invention as shown in Fig. 3 comprises a latch 3 according to the invention which corresponds with the latch 2 shown in Fig. 2, apart from the following.
The current sources 25,26 are replaced by fifth and sixth resistors 29,30, a common point of the first and fifth resistors 23,29 constituting a third data output 35 (OUT-) of the latch 3 and a common point of the second and sixth resistors 24,30 constituting a fourth data output 36 (OUT+) of the latch 3.
The latch 1-3 is arranged to, in the tracking mode, prepare the deciding circuit 5, for example as follows. The tracking circuit 4 supplies, in the tracking mode, a signal value derived from the data signal as supplied to the data inputs 31 ,32 to the deciding circuit 5, and the deciding circuit 5 amplifies, in the deciding mode, the signal value. This signal value is for example a voltage stored across a capacitance of the tracking circuit 4. This capacitance is for example realized via the parasitic capacitor present between the cathodes of the diodes 21,22. So, by already preparing the deciding circuit 5 in the tracking mode, the latch 1-3 uses the available time more efficiently. To be able to prepare the deciding circuit 5, the deciding circuit 5 is not to be switched between a disabled situation and an enabled situation, but is to be kept in the enabled situation. The tracking circuit 4 comprising the diodes 21,22 forms an advantageous construction owing to the fact that, compared to the prior art, between the data inputs 31,32 of the latch 1-3 a reduced voltage swing is sufficient for a proper performance of the latch 1- 3. Such a reduced voltage swing allows the latch 1-3 to perform at a higher speed.
The current sources 25,26 shown in Fig. 1 and 2 allow a compensation for performance loss at higher temperatures by automatically adjusting the currents of the current sources in dependence of the temperature.
The isolation between the outputs 35,36 and the data inputs 31,32 shown in Fig. 1 and 2 prevents that the latch 1,2 is loaded with parasitic capacitances of a load.
The fifth and sixth resistors 29,30 shown in Fig. 3 replace the current sources 25,26 of Fig. 1 and 2 and allow, compared to the embodiment with the current sources 25,26, between the data inputs 31,32 of the latch 3 a further reduced voltage swing for a proper performance of the latch 3. Such a further reduced voltage swing allows the latch 3 to perform at a further higher speed.
The clock input signals to be supplied to the clock inputs 37,38 result in the latch 1-3 being brought into the tracking mode or into the deciding mode.
The transistor 19 shown in Fig. 2 and 3 allows the deciding circuit 5 to be clocked, which is an advantage in case of using the latch 2 and 3 in a multiplexer or a generator environment.
The device 104 according to the invention in the form of a divider (a divide- by-two-divider or prescaler) shown in Fig. 4 comprises two latches 1-3 with outputs of a first latch being coupled to inputs of a second latch and with outputs of the second latch being fed back to inputs of the first latch.
The device 105 according to the invention in the form of a D-flipflop shown in Fig. 5 comprises two latches 1-3 with outputs of a first latch being coupled to inputs of a second latch and with outputs of the second latch now not being fed back to inputs of the first latch. Instead of that, the inputs of the first latch form the inputs of the D-flipflop and the outputs of the second latch form the outputs of the D-flipflop.
The transistors shown are NPN bipolar transistors, alternatively PNP bipolar transistors might be used, further alternatively Field Effect Transistors might be used, such as NMOS or PMOS transistors. Further embodiments related to non-balanced situations are not to be excluded.
It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. Use of the verb "to comprise" and its conjugations does not exclude the presence of elements or steps other than those stated in a claim. The article "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. In the device claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

CLAIMS:
1. Device (101-105) comprising a latch (1-3), which latch (1-3) comprises a tracking circuit (4) for, in a tracking mode, tracking a data signal and which latch (1-3) comprises a deciding circuit (5) for, in a deciding mode, deciding about the data signal, the latch (1-3) being arranged to, in the tracking mode, prepare the deciding circuit (5).
2. Device (101-105) according to claim 1, the tracking circuit (4) being arranged to, in the tracking mode, supply a signal value derived from the data signal to the deciding circuit (5), and the deciding circuit (5) being arranged to, in the deciding mode, amplify the signal value.
3. Device (101-105) according to claim 2, the tracking circuit (4) comprising a capacitance for storing the signal value.
4. Device (101-105) according to claim 1, the deciding circuit (5) comprising a first transistor (11) and a second transistor (12), first main electrodes of the first and second transistors (11,12) being coupled to each other and second main electrodes of the respective first and second transistors (11,12) being coupled to control electrodes of the respective second and first transistors (11,12).
5. Device (101-105) according to claim 4, the tracking circuit (4) comprising a first diode (21) and a second diode (22), first main electrodes of the first and second diodes (21,22) being coupled to each other and second main electrodes of the respective first and second diodes (21,22) being coupled to the control electrodes of the respective first and second transistors (11,12) and constituting respective first and second data inputs (31,32) of the latch (1-3).
6. Device (101-105) according to claim 5, the second main electrodes of the respective first and second diodes (21,22) being coupled via respective first and second resistors (23,24) and respective first and second current sources (25,26) to a voltage supply (40).
7. Device (101-105) according to claim 5, the control electrodes of the respective first and second transistors (11,12) being coupled to control electrodes of respective third and fourth transistors (13,14), first main electrodes of the third and fourth transistors (13,14) being coupled to each other and second main electrodes of the respective third and fourth transistors (13,14) constituting respective first and second data outputs (33,34) of the latch (1-3).
8. Device (101-105) according to claim 7, the control electrodes of the respective first and second transistors (11,12) being coupled to control electrodes of respective fifth and sixth transistors (15,16), first main electrodes of the fifth and sixth transistors (15,16) being coupled to each other and second main electrodes of the respective fifth and sixth transistors (15,16) being coupled via respective third and fourth resistors (27,28) to a voltage supply (40) and constituting respective third and fourth data outputs (35,36) of the latch (1-3).
9. Device (101-105) according to claim 7, the second main electrodes of the respective first and second diodes (21,22) being coupled via respective first and second resistors (23,24) and respective fifth and sixth resistors (29,30) to a voltage supply (40), a common point of the first and fifth resistors (23,29) constituting a third data output (35) of the latch (1-3) and a common point of the second and sixth resistors (24,30) constituting a fourth data output (36) of the latch (1-3).
10. Device (101-105) according to claim 7, the first main electrodes of the diodes
(21,22) further being coupled to a second main electrode of a seventh transistor (17), a first main electrode of the seventh transistor (17) being coupled to ground and a control electrode of the seventh transistor (17) constituting a first clock input (37) of the latch (1-3), the first main electrodes of the third and fourth transistors (13,14) further being coupled to a second main electrode of an eighth transistor (18), a first main electrode of the eighth transistor (18) being coupled to ground and a control electrode of the eighth transistor (18) constituting a second clock input (38) of the latch (1-3).
11. Device (101-105) according to claim 10, the first main electrodes of the first and second transistors (11,12) further being coupled to a second main electrode of a ninth transistor (19), a first main electrode of the ninth transistor (19) being coupled to ground and a control electrode of the ninth transistor (19) being coupled to the second clock input (38) of the latch (1-3).
12. Latch (1-3) comprising a tracking circuit (4) for, in a tracking mode, tracking a data signal and comprising a deciding circuit (5) for, in a deciding mode, deciding about the data signal, the latch (1-3) being arranged to, in the tracking mode, prepare the deciding circuit (5).
13. Method for latching a data signal and comprising a tracking step of, in a tracking mode, tracking the data signal and a deciding step of, in a deciding mode, deciding about the data signal and a preparing step of, in the tracking mode, preparing the deciding step.
EP06710725A 2005-01-28 2006-01-23 Device comprising a latch Withdrawn EP1844548A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP06710725A EP1844548A2 (en) 2005-01-28 2006-01-23 Device comprising a latch

Applications Claiming Priority (3)

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EP05100549 2005-01-28
PCT/IB2006/050242 WO2006079966A2 (en) 2005-01-28 2006-01-23 Device comprising a latch
EP06710725A EP1844548A2 (en) 2005-01-28 2006-01-23 Device comprising a latch

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Publication number Priority date Publication date Assignee Title
JPS5912661A (en) * 1982-07-13 1984-01-23 Fujitsu Ltd Variable threshold value type differential signal receiver
US4622475A (en) * 1984-03-05 1986-11-11 Tektronix, Inc. Data storage element having input and output ports isolated from regenerative circuit
JP2621311B2 (en) * 1988-03-10 1997-06-18 日本電気株式会社 Comparator with latch circuit
DE58906599D1 (en) * 1989-09-11 1994-02-10 Siemens Ag Toggle switch with switching hysteresis.
JPH06101671B2 (en) * 1989-09-27 1994-12-12 株式会社東芝 Voltage comparison circuit
US5347175A (en) * 1992-05-12 1994-09-13 The United States Of America As Represented By The Secretary Of Commerce Voltage comparator with reduced settling time

Non-Patent Citations (1)

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Title
See references of WO2006079966A3 *

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CN101107778A (en) 2008-01-16
JP2008529391A (en) 2008-07-31
WO2006079966A3 (en) 2006-10-12
WO2006079966A2 (en) 2006-08-03

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