EP1829358B1 - Auf fehlerdiffusion basierende bildverarbeitung - Google Patents

Auf fehlerdiffusion basierende bildverarbeitung Download PDF

Info

Publication number
EP1829358B1
EP1829358B1 EP05854565.8A EP05854565A EP1829358B1 EP 1829358 B1 EP1829358 B1 EP 1829358B1 EP 05854565 A EP05854565 A EP 05854565A EP 1829358 B1 EP1829358 B1 EP 1829358B1
Authority
EP
European Patent Office
Prior art keywords
pixel
value
error
accelerator unit
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Not-in-force
Application number
EP05854565.8A
Other languages
English (en)
French (fr)
Other versions
EP1829358A1 (de
Inventor
Eric Roberts
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of EP1829358A1 publication Critical patent/EP1829358A1/de
Application granted granted Critical
Publication of EP1829358B1 publication Critical patent/EP1829358B1/de
Not-in-force legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/40—Picture signal circuits
    • H04N1/405—Halftoning, i.e. converting the picture signal of a continuous-tone original into a corresponding signal showing only two levels
    • H04N1/4051—Halftoning, i.e. converting the picture signal of a continuous-tone original into a corresponding signal showing only two levels producing a dispersed dots halftone pattern, the dots having substantially the same size
    • H04N1/4052—Halftoning, i.e. converting the picture signal of a continuous-tone original into a corresponding signal showing only two levels producing a dispersed dots halftone pattern, the dots having substantially the same size by error diffusion, i.e. transferring the binarising error to neighbouring dot decisions

Definitions

  • the application relates generally to data processing, and, more particularly, to image processing.
  • Error diffusion is a process for approximating the display of digital images (such as continuous-tone digital images) on output devices that have limited color (tone) range. Error diffusion is most commonly used in printers to simulate multiple color shades with binary dot values. For example, a printer capable of only printing black dots may simulate multiple shades of gray using error diffusion.
  • Document EP 0606988 discloses a method and apparatus for reducing the speed with which a half toning method must be performed by performing the half toning of an output image in parallel by simultaneously error diffusing more than one line of input at a time.
  • Document US 2004/0008382 discloses a system and method for error diffusion screening with parallel processing, in which the calculation of an error diffused output image is divided into two distinct processes.
  • Error diffusion may include three operations.
  • a first operation includes quantizing a current pixel value to generate an output value.
  • the original pixel value is adjusted to include the errors diffused from surrounding pixels.
  • the output value for this adjusted current pixel value may be zero or one based on a comparison of the adjusted value to a threshold value.
  • a second operation for error diffusion includes computing the difference (i.e., the error) between the output value and the original pixel value.
  • a third operation for error diffusion includes distributing fractional error values to surrounding pixels. While any of a number of error diffusion filters may be used to diffuse errors to the surrounding pixels, in some embodiments, the Floyd-Steinberg filter is used. Other filters that may be used include the Burkes filter, the Stucki filter, etc.
  • Figure 1A illustrates distributing of errors from a pixel to surrounding pixels, according to some embodiments of the invention.
  • Figure 1A illustrates part of an image that includes pixels 102-118.
  • the pixels 102-118 are pixels P(i-1, j-1), P(i-1, j), P(i-1, j+1), P(i, j-1), P(i, j), P(i, j+1), P(i+1, j-1), P(i+1, j) and P(i+1, j+1), respectively.
  • the pixel 110 diffuses 7/16, 3/16, 5/16 and 1/16 of its error value to the pixels 112, 114, 116 and 118, respectively.
  • Figure 1B illustrates distributing of errors to a pixel from surrounding pixels, according to some embodiments of the invention.
  • Figure 1B illustrates that errors are computed and then distributed to a particular pixel prior to the threshold operation for error diffusion.
  • Figure 1B illustrates part of an image that includes pixels 120-136.
  • the pixels 120-136 are pixels P(i-1, j-1), P(i-1, j), P(i-1, j+1), P(i, j-1), P(i, j), P(i, j+1), P(i+1, j-1), P(i+1, j) and P(i+1, j+1), respectively.
  • the pixel 128 receives a fractional error value eA of 1/16 from the pixel 120.
  • the pixel 128 receives a fractional error value eB of 5/16 from the pixel 122.
  • the pixel 128 receives a fractional error value eC of 3/16 from the pixel 124.
  • the pixel 128 receives a fractional error value eD of 7/16 from the pixel 126.
  • Figure 2 illustrates pseudo code for error distribution, according to some embodiments of the invention.
  • Figure 2 illustrates pseudo code 200 that may be used to perform the error distribution shown in Figure 1 , according to some embodiments of the invention.
  • a code block 202 includes the assignment of the intermediate error values (1/16 * eA, 5/16 * eB, 3/16 * eC, and 7/16 * eD) to an accumulator variable.
  • a code statement 204 adds in the value of the pixel at location (i,j) in the image to the accumulator variable. Accordingly, the accumulator variable equals the value of the pixel at location (i,j) plus the intermediate error values received from the surrounding pixels. Examples of the surrounding pixels are set forth below.
  • a code block 206 assigns a value of zero to the pixel at location (i,j) if the accumulator is less a threshold value (e.g., 0.5) and assigns a value of one to this pixel if the accumulator is not less than the threshold value.
  • a code statement 208 updates the error buffer based on a difference between the actual value (the value stored in the accumulator) and the assigned value (zero or one).
  • Figure 3 illustrates data flow of intermediate error values to multiple pixels from surrounding pixels, according to some embodiments of the invention.
  • Figure 3 illustrates part of an image that includes pixels 302-324.
  • the pixels 302-324 are pixels P(i-1, j-1), P(i-1, j), P(i-1, j+1), P(i-1, j+2), P(i,j-1), P(i, j), P(i, j+1), P(i, j+2), P(i+1, j-1), P(i+1, j), P(i+1, j+1) and P(i+1, j+2), respectively.
  • the pixels 312 and 314 are defined as the current pixel and the next pixel with regard to computation.
  • a fractional error value eD (7/16) may be diffused from the pixel 310 to the current pixel 312.
  • the fractional error value eD may be generated from an input image 316 and diffused to the current pixel 302.
  • a fractional error value eD (7/16) may be diffused from the current pixel 312 to the next pixel 314. Therefore, the fractional error value eD may be computed as part of the previous pixel's error computation.
  • an error buffer stores a number of intermediate error values that may be diffused from surrounding pixels in the previous row to the current pixel 312 and the next pixel 314.
  • a fractional error value may be diffused from the pixel 302 to the current pixel 312 (as eA - 1/16).
  • a fractional error value may be diffused from the pixel 304 to the current pixel 312 (as eB - 5/16) and to the next pixel 314 (as eC - 3/16).
  • a fractional error value may be diffused from the pixel 306 to the current pixel 312 (as eC 3/16) and to the next pixel 314 (as eB - 5/16).
  • a fractional error value may be diffused from the pixel 308 to the next pixel 314 (as eC - 3/16).
  • eB for the current pixel is eA for the next pixel.
  • eC for the current pixel is eB for the next pixel.
  • eC for the next pixel may be retrieved from the error buffer, and eD for the next pixel is from the error computation for the current pixel.
  • FIG. 4 illustrates a more detailed block diagram of an image signal processor, according to some embodiments of the invention.
  • An image signal processor 400 includes an input processor element 402, an output processor element 404, a number of processor elements 406A-406C, a number of registers 408, a number of accelerator units 410A-410B, a memory 414 and a memory controller 416.
  • the input processor element 402, the output processor element 404, the processor elements 406A-406C, the accelerator units 510A-410B and the memory 414 (through the memory controller 416) are coupled to the registers 408.
  • the registers 408 allow the processor elements 402, 404 and 406, the accelerator units 410A-410B and the memory 414 to exchange data and can be used as general purpose registers for a given processor element 402, 404 and 406 and the accelerator units 410A-410B. Moreover, the processor elements 402, 404 and 406 and the accelerator units 410A-410B may include a number of local registers (not shown).
  • the input processor element 402, the output processor element 404 and the processor elements 406A-406C include an instruction memory and an arithmetic-logic unit (ALU) for processing data.
  • the input processor element 402 and the output processor element 404 are coupled to ports of the image signal processor 400 through a port ring to receive data being input into and to transmit data being output from, respectively, the image signal processor 400.
  • An architecture having such a configuration, according to some embodiments, is described in more detail below.
  • the input processor element 402 and/or the output processor element 404 may process the data similar to the processing provided by the processor elements 406A-406C.
  • the different processor elements 406A-406C may be general-purpose processor elements or special-purpose processor elements.
  • the processor elements 406A-406C may be Multiply-Accumulate (MAC) processor elements that include an instruction set for general-purpose processing as well as an instruction set for MAC functionality.
  • the processor elements 406A-406C may be a combination of general-purpose processor elements and special-purpose processor elements.
  • the processor elements 406A and 406C may be MAC processor elements
  • the processor elements 406B may be a general-purpose processor element. While Figure 4 illustrates five processor elements within the image signal processor 400, in other embodiments, a lesser or greater number of such processor elements may be incorporated into the image signal processor 400.
  • the input processor element 402 is a general-purpose processor element with a port interface as an input port.
  • the instructions within the input processor element 402 have the ports as additional input operands along with the registers 408 and the local registers within the input processor element 402.
  • the output processor element 404 is a general-purpose processor element with a port interface as an output port.
  • the instructions within the output processor element 404 have the ports as additional output operands along with the registers 408 and the local registers within the output processor element 404.
  • Figure 5 illustrates a more detailed block diagram of an image signal processor for error diffusion operations, according to some embodiments of the invention.
  • Figure 5 illustrates a more detailed block diagram of the image signal processors 400, according to some embodiments of the invention.
  • Figure 5 includes a number of the elements of Figure 4 , wherein a same element is distributed across a number of different blocks to illustrate the flow of data among such elements. Accordingly, a same reference element refers to different blocks within Figure 5 . Moreover, such blocks may include description of the type of operation performed therein.
  • the unpack input pixel block of the input processor element 402 is coupled to receive a packed input pixel 504.
  • the unpack error block of the input processor element 402 is coupled to receive intermediate error values from an error buffer 502.
  • An output from the unpack input pixel block of the input processor element 402 is coupled to an input of the error filter (even) block of the accelerator unit 410A and an input of the error filter (odd) block of the accelerator unit 410B.
  • An output from the unpack error block of the input processor element 402 is coupled to an input of the error cache of the processor element 406A.
  • An output of the error cache of the processor element 406A is coupled to an input of the error filter (even) block of the accelerator unit 410A and an input of the error filter (odd) block accelerator unit 410B.
  • An output of the error filter (even) block of the accelerator unit 410A is coupled to an input of the comparison block and the subtractor block of the accelerator unit 410B.
  • An output of the error filter (odd) block of the accelerator unit 410B is coupled to an input of the comparison block and the subtractor block of the accelerator unit 410A.
  • a threshold input 507 is coupled to an input of the comparison blocks. The threshold input 507 may be different for the two different comparison blocks.
  • An output of the comparison block of the accelerator unit 410B is coupled to an input of the subtractor block of the accelerator unit 410B and an input of the pack output pixel block of the output processor element 404.
  • An output of the comparison block of the accelerator unit 410A is coupled to an input of the subtractor block of the accelerator unit 410A and an input of the pack output pixel block of the output processor element 404.
  • the output from the pack output pixel block is the packed output pixel 506.
  • An output of the subtractor block of the accelerator unit 410B is coupled to an input of the pack new error block of the output processor element 404 and to an input of the error filter (even) block.
  • An output of the subtractor block of the accelerator unit 410A is coupled to an input of the pack new error block of the output processor element 404 and to an input of the error filter (odd) block.
  • An output of the pack new error block is coupled to an input of the error buffer 502.
  • Figure 6 illustrates a flow diagram for error diffusion-based image processing, according to some embodiments of the invention.
  • Figure 6 includes a flow diagram 600 that illustrates the operations of the image signal processor 400 shown in Figure 5 , according to some embodiments of the invention.
  • pixels of an image are received.
  • the unpack input pixel block of the input processor element 402 may receive the pixels of the image.
  • the pixels may be received from a different image signal processor 400, a memory or input/output device (such as a sensor).
  • the pixels may be received from one of such components based on the data driven operations (as described above).
  • the image may be a continuous-tone digital image. Control continues at block 604.
  • error diffusion is performed for more than one pixel, at overlapping times.
  • the time of execution for error diffusion for one pixel overlaps with the time of execution for error diffusion of one or more other pixels.
  • the different blocks of the input processor element 402, the accelerator units 410A-410B, the processor element 406A and the output processor element 404 may perform such operations. A more detailed description of such operations is set forth below in conjunction with the description of Figure 7 .
  • Figure 7 illustrates a table of operations for error diffusion-based image processing by multiple elements within an image signal processor, according to some embodiments of the invention.
  • Figure 7 illustrates a table 700 that sets forth the operations of the input processor element 402, the accelerator units 410A-410B, the processor element 406A and the output processor element 404, relative to each other. More specifically, the table 700 illustrates performing of error diffusion for more than one pixel, partially in parallel. In other words, the performing of error diffusion for one pixel is partially in parallel with the performing of error diffusion for one or more other pixels.
  • the columns may be representative of the timing of such operations. Accordingly, operations in a same column may be performed simultaneously, at least in part.
  • the input processor element 402 and the accelerator unit 410A may perform operations.
  • the unpack error of the input processor element 402 may read in two intermediate error values from the previous row from the error buffer 502.
  • the unpack error block may read in eC even (eC used for the even pixel) and eC odd (eC used for the odd pixel) from the error buffer 502.
  • the error filter (even) block of the accelerator unit 410A may receive eA from the error cache of the processor element 406A.
  • the error filter (even) block may compute (1 * eA) for the even pixel and notify the processor element 406A after completion of this computation.
  • the input processor element 402, the accelerator unit 410A and the processor element 406A may perform operations.
  • the unpack error block of the input processor element 402 may unpack the error values, eC, for the even pixel and the odd pixel.
  • the error filter (even) block of the accelerator unit 410A may receive eB from the error cache of the processor element 406A.
  • the error filter (even) block may compute (5 * eB) for the even pixel and notify the processor element 406A after completion of this computation.
  • the processor element 406A may load the value of eB into eA.
  • the processor element 406A may notify the error filter (odd) block of the accelerator unit 410B after completion of this load operation. As described above, eB for the current pixel is eA for the next pixel. Because the accelerator unit 410A has completed using of eA for the even pixel, such value may be overwritten with eA for the odd pixel (eB for the even pixel).
  • the input processor element 402, the accelerator unit 410A, the processor element 406A and the accelerator unit 410B may perform operations.
  • the unpack input pixel block of the input processor element 402 may read in two input pixels (p even and p odd ).
  • the error filter (even) block of the accelerator unit 410A may receive eC from the error cache of the processor element 406A.
  • the error filter (even) block may compute (5 * eC) for the even pixel.
  • the processor element 406A may load the value of eC into eB. Additionally, the processor element 406A may notify the error filter (odd) block of the accelerator unit 410B after completion of this load operation.
  • the error filter (odd) block of the accelerator unit 410B may receive eA from the error cache of the processor element 406A.
  • the error filter (even) block may compute (1 * eA) for the odd pixel and notify the processor element 406A after completion of this computation.
  • the input processor element 402, the accelerator unit 410A, the processor element 406A and the accelerator unit 410B may perform operations.
  • the unpack input pixel block of the input processor element 402 may unpack the two input pixels (p even and p odd ).
  • the input processor element 402 may forward the input pixels (p even and p odd ) to the error filter (even) block of the accelerator unit 410A and the error filter (odd) block of the accelerator unit 410B, respectively.
  • the error filter (even) block of the accelerator unit 410A may receive eD from the error cache of the processor element 406A.
  • the error filter (even) block may compute (7 * eD) for the even pixel.
  • the processor element 406A may load the value of eB into eA. Additionally, partially in parallel, the error filter (odd) block of the accelerator unit 410B may receive eB from the error cache of the processor element 406A. The error filter (even) block may compute (5 * eB) for the odd pixel and notify the processor element 406A after completion of this computation.
  • the accelerator unit 410A, the processor element 406A and the accelerator unit 410B may perform operations.
  • the error filter (even) block of the accelerator unit 410A may compute the error value for the even pixel. Specifically, the error filter (odd) block may add together the computed fractional error values from the surrounding pixels (1*eA, 5*eB, 3*eC, and 7*eD) and divide the result by 16. Partially in parallel, the processor element 406A may load the value of eC into eB. Partially in parallel, the error filter (even) block of the accelerator unit 410B may receive eC from the error cache of the processor element 406A. The error filter (odd) block may compute (3 * eC) for the odd pixel. Additionally, at some point after reading in the current two input pixels, the unpack input pixel block of the input processor element 402 may read in the next two input pixels.
  • the accelerator unit 410A and the accelerator unit 410B may perform operations.
  • the error filter (even) block of the accelerator unit 410A may commence computing the error diffusion for the next unprocessed pixel (the next even pixel).
  • the error filter (even) block may receive eA from the error cache of the processor element 406A.
  • the error filter (even) block may compute (1 * eA) for the even pixel and notify the processor element 406A after completion of this computation.
  • the error filter (odd) block may compute the threshold for the even pixel. Referring to Figure 5 , the error filter (odd) block may perform the threshold operation shown in the code block 1606.
  • the comparison block for the accelerator unit 410B may determine whether the accumulated value for the even pixel is greater than a threshold value from the threshold input 507.
  • the output from the comparison block may be a binary value (0 or 1) depending of whether the accumulated value for the even pixel exceeds the threshold value (as shown in the code block 406 of Figure 4 ).
  • the accelerator unit 410A, the processor element 406A, the accelerator unit 410B and the output processor element 404 may perform operations.
  • the error filter (even) block may receive eB from the error cache of the processor element 406A.
  • the error filter (even) block may compute (5 * eB) for the next even pixel and notify the processor element 406A after completion of this computation.
  • the processor element 406A may load the value of eB into eA. Additionally, the processor element 406A may notify the error filter (odd) block of the accelerator unit 410B after completion of this load operation.
  • the error filter (odd) block of the accelerator unit 410B may compute the error computation for the even pixel.
  • the error filter (odd) block may perform the error computation operation shown in the code statement 208.
  • the subtractor block of the accelerator unit 410B may determine a difference between the actual value (the accumulated value) and the outputted value (zero or one). This error value (even) 508 is inputted into the error filter (odd) block of the accelerator unit 410B.
  • the accelerator unit 410A, the processor element 406A, the accelerator unit 410B and the output processor element 404 may perform operations.
  • the error filter (even) block of the accelerator unit 410A may receive eC from the error cache of the processor element 406A.
  • the error filter (even) block may compute (3 * eC) for the next even pixel.
  • the processor element 406A may load the value of eC into eB. Additionally, the processor element 406A may notify the error filter (odd) block of the accelerator unit 410B after completion of this load operation.
  • the error filter (odd) block of the accelerator unit 410B may compute (7*eD) for the odd pixel.
  • the pack output pixel block of the output processor element 404 may pack the value of the even pixel (received from the comparison block of the accelerator unit 410B).
  • the packed output pixel block may output this value as the packed output pixel 506.
  • the accelerator unit 410B and the output processor element 404 may perform operations.
  • the error filter (odd) block of the accelerator unit 410B may compute the error value for the odd pixel. Specifically, the error filter (odd) block may add together the computed fractional error values from the surrounding pixels (1*eA, 5*eB, 3*eC, and 7*eD) and divide the result by 16. Partially in parallel, the pack new error block of the output processor element 404 may update the error buffer 502 with this new error value for the even pixel.
  • the accelerator unit 410A and the accelerator unit 410B may perform operations.
  • the error filter (even) block of the accelerator unit 410A may compute the threshold for the odd pixel.
  • the error filter (odd) block may perform the threshold operation shown in the code block 1606.
  • the comparison block for the accelerator unit 410B may determine whether the accumulated value for the odd pixel is greater than a threshold value from the threshold input 507.
  • the output from the comparison block may be a binary value (zero or one) depending of whether the accumulated value for the odd pixel exceeds the threshold value (as shown in the code block 206 of Figure 2 ).
  • the error filter (odd) block of the accelerator unit 410B may receive eA from the error cache of the processor element 406A.
  • the error filter (even) block may compute (1 * eA) for the next odd pixel and notify the processor element 406A after completion of this computation.
  • the accelerator unit 410A, the processor element 406A, the accelerator unit 410B and the output processor element 404 may perform operations.
  • the error filter (even) block of the accelerator unit 410A may compute the error computation for the odd pixel.
  • the error filter (odd) block may perform the error computation operation shown in the code statement 208.
  • the subtractor block of the accelerator unit 410B may determine a difference between the actual value (the accumulated value) and the outputted value (zero or one). This error value (odd) 510 is inputted into the error filter (even) block of the accelerator unit 410B.
  • the processor element 406A may load the value of eB into eA and notify the processor element 406A after completion of this computation.
  • the error filter (odd) block of the accelerator unit 4108 may receive eB from the error cache of the processor element 406A.
  • the error filter (even) block may compute (5 * eB) for the next odd pixel and notify the processor element 406A after completion of this computation.
  • the pack output pixel block of the output processor element 404 may pack the value of the odd pixel (received from the comparison block of the accelerator unit 410A).
  • the packed output pixel block may output this value as the packed output pixel 506.
  • the accelerator unit 410A, the processor element 406A and the output processor element 404 may perform operations.
  • the error filter (even) block of the accelerator unit 410A may receive eD from the error cache of the processor element 406A.
  • the error filter (even) block may compute (7 * eD) for the next even pixel.
  • the processor element 406A may load the value of eC into eB and notify the error filter (odd) block of the accelerator unit 410B after completion of this load operation.
  • the pack new error block of the output processor element 404 may update the error buffer 502 with the new error value for the odd pixel.
  • Some embodiments may incorporate error diffusion operations to output continuous-tone digital images on output devices (such as printers, screens, etc.) that have limited color (tone) range. Some embodiments may be used to perform error diffusion, partially in parallel, for more than one pixel. As described, some embodiments allow a processor to keep multiple execution engines occupied by processing multiple pixels non-serially or simultaneously at least in part. Moreover during this processing of multiple pixels, some embodiments share intermediate errors values from surrounding pixels. Accordingly, as described, this parallel processing of pixels of an image may continue until all of the pixels in the image are processed.
  • Figure 8 illustrates a processor architecture for performing error diffusion operations, according to some embodiments of the invention.
  • Figure 8 illustrates a system for processor-to-processor communication in a data driven architecture, according to some embodiments of the invention.
  • Figure 8 illustrates a system 800 that includes an image processor 802 that is coupled to receive an input data stream 818 from a sensor 816. While the sensor 816 may be of different types, in an embodiment, the sensor 816 is a Charge Coupled Device (CCD) sensor. In an embodiment, the sensor 816 is a Complementary Metal Oxide Semiconductor (CMOS) sensor. The sensor 816 scans and digitizes images, thereby producing the input data stream 818.
  • the system 800 is embedded within a scanner that scans and processes images (such as documents, photos, etc.).
  • the image processor 802 has an architecture that is data driven, wherein the transmission and receipt of data across different elements within the image processor 802 drives the execution of the operations therein. In other words, a given operation within an element of the image processor 802 commences when the necessary data is available for execution.
  • the image processor 802 is coupled to memories 804A-804B.
  • the memories 804A-804B are different types of random access memory (RAM).
  • the memories 804A-804B are double data rate (DDR) Synchronous Dynamic RAM (SDRAM).
  • DDR double data rate
  • SDRAM Synchronous Dynamic RAM
  • elements within the image processor 802 store data related to image processing into the memories 804A-804B.
  • a processor element within the image processor 802 may store results from a first image processing operation into one of the memories 804A-804B, which is subsequently retrieved by a different processor element within the image processor 802 to perform a second image processing operation.
  • the image processor 802 is coupled to bus 814, which in an embodiment may be a Peripheral Component Interface (PCI) bus.
  • the system 800 also includes a memory 806, a host processor 808, a number of input/output (I/O) interfaces 810 and a network interface 812.
  • the host processor 808 is coupled to the memory 806.
  • the memory 806 may be different types of RAM (e.g., Synchronous Dynamic RAM (SDRAM), DRAM, DDR-SDRAM, etc.), while in an embodiment, the host processor 808 may be different types of general-purpose processors.
  • the I/O interface 810 provides an interface to I/O devices or peripheral components for the system 800.
  • the I/O interface 810 may comprise any suitable interface controllers to provide for any suitable communication link to different components of the system 800.
  • the I/O interface 810 for an embodiment provides suitable arbitration and buffering for one of a number of interfaces.
  • the I/O interface 810 provides an interface to one or more suitable integrated drive electronics (IDE) drives, such as a hard disk drive (HDD) or compact disc read only memory (CD ROM) drive for example, to store data and/or instructions, for example, one or more suitable universal serial bus (USB) devices through one or more USB ports, an audio coder/decoder (codec), and a modem codec.
  • IDE integrated drive electronics
  • USB universal serial bus
  • codec audio coder/decoder
  • the I/O interface 810 for an embodiment also provides an interface to a keyboard, a mouse, one or more suitable devices, such as a printer for example, through one or more ports.
  • the network interface 812 provides an interface to one or more remote devices over one of a number of communication networks (the Internet, an Intranet network, an Ethernet-based network, etc.).
  • the host processor 808, the I/O interfaces 810 and the network interface 812 are coupled together with the image processor 802 through the bus 814.
  • instructions executing within the host processor 808 configure the image processor 802 for different types of image processing.
  • the host processor 808 establishes a number of different logical connections among the different processor elements within the image processor 802.
  • the host processor 808 may download microcode to and check the status of the different components in the image processor 802 therein. To illustrate, a more detailed description of one embodiment of the image processor 802 will now be described.
  • references in the specification to "one embodiment”, “an embodiment”, “an example embodiment”, etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
  • Embodiments of the invention include features, methods or processes that may be embodied within machine-executable instructions provided by a machine-readable medium.
  • a machine-readable medium includes any mechanism that provides (i.e., stores and/or transmits) information in a form accessible by a machine (e.g., a computer, a network device, a personal digital assistant, manufacturing tool, any device with a set of one or more processors, etc.).
  • a machine-readable medium includes volatile and/or non-volatile media (e.g., read only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.), as well as electrical, optical, acoustical or other form of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.)).
  • volatile and/or non-volatile media e.g., read only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.
  • electrical, optical, acoustical or other form of propagated signals e.g., carrier waves, infrared signals, digital signals, etc.
  • Such instructions are utilized to cause a general-purpose or special-purpose processor, programmed with the instructions, to perform methods or processes of the embodiments of the invention.
  • the features or operations of embodiments of the invention are performed by specific hardware components that contain hard-wired logic for performing the operations, or by any combination of programmed data processing components and specific hardware components.
  • Embodiments of the invention include software, data processing hardware, data processing system-implemented methods, and various processing operations, further described herein.
  • a number of figures show block diagrams of systems and apparatus for error diffusion-based image processing, in accordance with some embodiments of the invention.
  • a number of figures show flow diagrams illustrating error diffusion-based image processing, in accordance with some embodiments of the invention.
  • the operations of the flow diagrams have been described with reference to the systems/apparatus shown in the block diagrams. However, it should be understood that the operations of the flow diagrams could be performed by embodiments of systems and apparatus other than those discussed with reference to the block diagrams, and embodiments discussed with reference to the systems/apparatus could perform operations different than those discussed with reference to the flow diagrams.

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Image Processing (AREA)
  • Facsimile Image Signal Circuits (AREA)

Claims (12)

  1. Verfahren, umfassend:
    Empfangen (602) von mehr als einem Pixel eines Bildes;
    Durchführen (604), zu überlappenden Zeiten, einer Fehlerdiffusion für das mehr als eine Pixel, indem, zu überlappenden Zeiten, fraktionale Fehlerwerte zu dem mehr als einen Pixel verteilt werden, wobei das Verteilen zu überlappenden Zeiten Folgendes umfasst:
    Akkumulieren von fraktionalen Fehlerwerten für ein ausgewähltes Pixel des Bildes von umliegenden Pixeln an einer Beschleunigereinheit (410) eines Bildsignalprozessors (802);
    Hinzufügen der akkumulierten fraktionalen Fehlerwerte zu einem Wert des ausgewählten Pixels, um einen akkumulierten Wert zu erzeugen, unter Verwendung der Beschleunigereinheit (410);
    Vergleichen des akkumulierten Werts mit einem Schwellenwert in einem Vergleichsblock der Beschleunigereinheit (410);
    Zuweisen eines Ausgangswerts zu dem ausgewählten Pixel basierend auf dem Vergleich,
    wobei der Vergleichsblock einen Null-Wert zuweist, wenn der akkumulierte Wert nicht größer ist als der Schwellenwert, und dem ausgewählten Pixel einen Eins-Wert zuweist, wenn der akkumulierte Wert den Schwellenwert überschreitet;
    Subtrahieren des Ausgangswerts des ausgewählten Pixels von dem akkumulierten Wert, um einen Fehlerwert zu erzeugen, unter Verwendung eines Subtrahiererblocks der Beschleunigereinheit (410); und
    Bereitstellen des Ausgangswerts an ein Ausgangsprozessorelement (406) des Bildsignalprozessors (802).
  2. Verfahren nach Anspruch 1, wobei die fraktionalen Fehlerwerte basierend auf einem Floyd-Steinberg-Fehlerfilter berechnet werden.
  3. Verfahren nach Anspruch 1, ferner umfassend:
    Zusammenpacken des Ausgangswerts mit anderen Ausgangswerten, um gepackte Ausgangspixel zu erzeugen, unter Verwendung des Ausgangsprozessorelements; und
    Ausgeben der gepackten Ausgangspixel von dem Ausgangsprozessorelement zu einer Einrichtung mit einem Farbbereich, der kleiner ist als ein Farbbereich des Bildes.
  4. Verfahren nach Anspruch 1, wobei:
    der Empfangsschritt ferner ein Empfangen (602) von Werten eines ersten Pixels und eines zweiten Pixels eines Bildes umfasst, wobei das erste Pixel ein gerades Pixel und das zweite Pixel ein ungerades Pixel des Bildes ist;
    die Ansammel- und Hinzufügeschritte ferner ein nicht serielles Verteilen von fraktionalen Fehlerwerten von umliegenden Pixeln zu dem ersten Pixel und dem zweiten Pixel umfassen, um einen ersten akkumulierten Wert bzw. einen zweiten akkumulierten Wert zu erzeugen;
    der Vergleichsschritt ferner ein Vergleichen des ersten akkumulierten Werts mit einer ersten Schwelle und eines zweiten akkumulierten Werts mit einer zweiten Schwelle umfasst;
    der Zuweisungsschritt ferner ein Zuweisen von Ausgangswerten zu dem ersten Pixel und dem zweiten Pixel basierend auf dem Vergleich umfasst, wobei die zugewiesenen Ausgangswerte Binärwerte umfassen;
    der Subtrahierungsschritt ferner ein Subtrahieren der Ausgangswerte von dem ersten und zweiten akkumulierten Wert umfasst, um einen ersten und zweiten Fehlerwert für das erste und zweite Pixel zu erzeugen; und
    der Ausgabeschritt ferner ein Ausgeben der Ausgangswerte zu einer Ausgabeeinrichtung umfasst, die einen Farbbereich aufweist, der kleiner ist als ein Farbbereich des Bildes.
  5. Verfahren nach Anspruch 4, wobei das Empfangen von Werten des ersten Pixels und des zweiten Pixels des Bildes ein Empfangen von Werten des ersten Pixels und des zweiten Pixels eines digitalen Bildes mit einem ungefähr kontinuierlichen Farbton umfasst.
  6. Verfahren nach Anspruch 4, wobei das Verteilen von fraktionalen Fehlerwerten ein nicht serielles Berechnen der fraktionalen Fehlerwerte für das erste Pixel und für das zweite Pixel umfasst.
  7. Vorrichtung, umfassend:
    einen Bildsignalprozessor (802), der Folgendes beinhaltet:
    eine erste Beschleunigereinheit (410A) zum Durchführen von zumindest einem Teil einer Fehlerdiffusionsoperation an einem ersten Pixel eines Bildes basierend auf fraktionalen Fehlerwerten von umliegenden Pixeln, wobei die erste Beschleunigereinheit (410A) fraktionale Fehlerwerte von umliegenden Pixeln zu einem Wert des ersten Pixels hinzufügen soll, um einen ersten akkumulierten Wert zu erzeugen; und
    eine zweite Beschleunigereinheit (410B) zum Durchführen von zumindest einem Teil einer Fehlerdiffusionsoperation an einem zweiten Pixel des Bildes, teilweise parallel mit der Fehlerdiffusion durch die erste Beschleunigereinheit (410A), basierend auf fraktionalen Fehlerwerten von umliegenden Pixeln,
    wobei die zweite Beschleunigereinheit (410B) fraktionale Fehlerwerte von umliegenden Pixeln zu einem Wert des zweiten Pixels hinzufügen soll, um einen zweiten akkumulierten Wert zu erzeugen;
    wobei die zweite Beschleunigereinheit (410B) eine erste Schwelle für das erste Pixel berechnen soll, die zweite Beschleunigereinheit (410B) den ersten akkumulierten Wert mit der ersten Schwelle vergleichen soll und dem ersten Pixel einen ersten Binärwert basierend auf dem Vergleich zuweisen soll, die zweite Beschleunigereinheit (410B) den ersten Binärwert von dem ersten akkumulierten Wert subtrahieren soll, um einen ersten Fehlerwert zu erzeugen,
    wobei die erste Beschleunigereinheit (410A) eine zweite Schwelle für das zweite Pixel berechnen soll, die erste Beschleunigereinheit (410A) den zweiten akkumulierten Wert mit der zweiten Schwelle vergleichen soll und dem zweiten Pixel einen zweiten Binärwert basierend auf dem Vergleich zuweisen soll, die erste Beschleunigereinheit (410A) den zweiten Binärwert von dem zweiten akkumulierten Wert subtrahieren soll, um einen zweiten Fehlerwert zu erzeugen.
  8. Vorrichtung nach Anspruch 7, wobei das Bild ein digitales Bild mit einem ungefähr kontinuierlichen Farbton ist.
  9. Vorrichtung nach Anspruch 7, wobei, als Teil der Fehlerdiffusionsoperation für das erste Pixel, die erste Beschleunigereinheit (410A) den Wert des ersten Pixels basierend auf den fraktionalen Fehlerwerten von den umliegenden Pixeln aktualisieren soll.
  10. Vorrichtung nach Anspruch 9, wobei, als Teil der Fehlerdiffusionsoperation für das zweite Pixel, die zweite Beschleunigereinheit (410B) den Wert des zweiten Pixels basierend auf den fraktionalen Fehlerwerten von den umliegenden Pixeln aktualisieren soll.
  11. System, umfassend:
    einen Charge-Coupled-Device-Sensor (816) zum Aufnehmen eines Bildes mit einem ungefähr kontinuierlichen Farbton; und
    einen Bildsignalprozessor (802), der Folgendes beinhaltet:
    ein Eingangsprozessorelement zum Empfangen eines ersten Pixels und eines zweiten Pixels, die gerade bzw. ungerade Pixel des Bildes mit dem ungefähr kontinuierlichen Farbton umfassen;
    eine erste Beschleunigereinheit (410A) zum Durchführen von Operationen für eine Fehlerdiffusion für das erste Pixel und für das zweite Pixel basierend auf fraktionalen Fehlerwerten von umliegenden Pixeln, wobei die erste Beschleunigereinheit (410A) fraktionale Fehlerwerte von umliegenden Pixeln zu dem ersten Pixel hinzufügen soll, um einen ersten akkumulierten Wert zu erzeugen, wobei die erste Beschleunigereinheit (410A) einen zweiten Schwellenwert berechnen soll, der mit dem zweiten Pixel assoziiert ist;
    eine zweite Beschleunigereinheit (410B), zum Durchführen von Operationen für die Fehlerdiffusion für das erste Pixel und für das zweite Pixel, zu überlappenden Zeiten mit den Operationen durch die erste Beschleunigereinheit (410A), basierend auf fraktionalen Fehlerwerten von umliegenden Pixeln, wobei die zweite Beschleunigereinheit (410B) fraktionale Fehlerwerte von umliegenden Pixeln zu dem zweiten Pixel hinzufügen soll, um einen zweiten akkumulierten Wert zu erzeugen, wobei die zweite Beschleunigereinheit (410B) einen ersten Schwellenwert berechnen soll, der mit dem ersten Pixel assoziiert ist; und
    ein Ausgangsprozessorelement (404) zum Ausgeben von Werten für das erste Pixel und das zweite Pixel nach der Fehlerdiffusion zu einer Ausgabeeinrichtung mit einem Farbbereich, der kleiner ist als ein Farbbereich des Bildes mit dem ungefähr kontinuierlichen Farbton;
    wobei, als Teil der Fehlerdiffusionsoperation für das erste Pixel, die zweite Beschleunigereinheit (410B) einen ersten Binärwert für das erste Pixel basierend auf einem Vergleich zwischen dem ersten akkumulierten Wert für das erste Pixel und dem ersten Schwellenwert zuweisen soll, um einen ersten Ausgangswert zu erzeugen, und die zweite Beschleunigereinheit (410B) eine erste Differenz zwischen dem ersten Ausgangswert und dem Binärwert berechnen soll, wobei die erste Differenz einen ersten Fehlerwert umfasst; und
    wobei, als Teil der Fehlerdiffusionsoperation für das zweite Pixel, die erste Beschleunigereinheit (410A) einen zweiten Binärwert für das zweite Pixel basierend auf einem Vergleich zwischen dem zweiten akkumulierten Wert für das zweite Pixel und dem zweiten Schwellenwert zuweisen soll, um einen zweiten Ausgangswert zu erzeugen, und die erste Beschleunigereinheit (410A) eine zweite Differenz zwischen dem zweiten Ausgangswert und dem zweiten Binärwert berechnen soll, wobei die zweite Differenz einen zweiten Fehlerwert umfasst.
  12. Maschinenlesbares Medium, das Anweisungen bereitstellt, die bei Ausführung durch eine Maschine bewirken, dass die Maschine alle Schritte des Verfahrens nach einem der Ansprüche 1 bis 6 durchführt.
EP05854565.8A 2004-12-14 2005-12-13 Auf fehlerdiffusion basierende bildverarbeitung Not-in-force EP1829358B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/011,737 US7639887B2 (en) 2004-12-14 2004-12-14 Error diffusion-based image processing
PCT/US2005/045884 WO2006066185A1 (en) 2004-12-14 2005-12-13 Error diffusion-based image processing

Publications (2)

Publication Number Publication Date
EP1829358A1 EP1829358A1 (de) 2007-09-05
EP1829358B1 true EP1829358B1 (de) 2018-09-05

Family

ID=36094865

Family Applications (1)

Application Number Title Priority Date Filing Date
EP05854565.8A Not-in-force EP1829358B1 (de) 2004-12-14 2005-12-13 Auf fehlerdiffusion basierende bildverarbeitung

Country Status (7)

Country Link
US (3) US7639887B2 (de)
EP (1) EP1829358B1 (de)
JP (1) JP4705645B2 (de)
KR (1) KR100889410B1 (de)
CN (2) CN101076995B (de)
TW (1) TWI319283B (de)
WO (1) WO2006066185A1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1345411B1 (de) * 2002-03-15 2018-11-21 Canon Kabushiki Kaisha Bildverarbeitungsvorrichtung, Bildverarbeitungsverfahren und Programm
US7639887B2 (en) * 2004-12-14 2009-12-29 Intel Corporation Error diffusion-based image processing
CN100435548C (zh) 2006-09-15 2008-11-19 北京大学 一种能够同时产生多位调频网点的方法及装置
US8184917B2 (en) * 2009-08-05 2012-05-22 Brother Kogyo Kabushiki Kaisha Image processor
KR101328793B1 (ko) * 2009-11-23 2013-11-13 엘지디스플레이 주식회사 오차 확산 방법과 이를 이용한 액정표시장치
WO2012075384A2 (en) 2010-12-04 2012-06-07 3M Innovative Properties Company Illumination assembly and method of forming same
KR20130126943A (ko) 2010-12-04 2013-11-21 쓰리엠 이노베이티브 프로퍼티즈 컴파니 조명 조립체 및 이를 형성하는 방법
JP5955109B2 (ja) * 2012-06-05 2016-07-20 キヤノン株式会社 画像処理方法及び画像処理装置

Family Cites Families (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US670127A (en) * 1900-12-10 1901-03-19 Edgar O Butterfield Foot-support for wagon-boxes.
US5051844A (en) * 1989-01-30 1991-09-24 Eastman Kodak Company Digital halftoning with error diffusion
US5087981A (en) * 1990-01-02 1992-02-11 Eastman Kodak Company Error diffusion of overlapping dots
JPH03274963A (ja) * 1990-03-26 1991-12-05 Canon Inc フアクシミリ装置
US5278671A (en) * 1990-10-05 1994-01-11 Nippon Steel Corporation Image processing apparatus with correction of diffusion errors of overlapping dots
US5172247A (en) * 1990-10-24 1992-12-15 Eastman Kodak Company High speed digital error diffusion process for continuous tone image-to-binary image conversion
US5130823A (en) * 1991-06-27 1992-07-14 Cactus Error diffusion system
US5276535A (en) * 1991-12-24 1994-01-04 Levien Raphael L Method and apparatus for halftoning of images using grayscale error diffusion
US5243443A (en) * 1991-12-06 1993-09-07 Xerox Corporation Halftoning with error feedback and image dependent enhancement
US5245678A (en) * 1991-12-20 1993-09-14 Xerox Corporation Image conversion with lossy adaptive error diffusion
US5271070A (en) 1992-11-06 1993-12-14 Xerox Corporation Multi-dimensional error diffusion technique
US5553165A (en) 1993-01-11 1996-09-03 Canon, Inc. Parallel error diffusion method and apparatus
US5434672A (en) * 1993-06-23 1995-07-18 Hewlett-Packard Company Pixel error diffusion method
US5521989A (en) * 1993-08-05 1996-05-28 Xerox Corporation Balanced error diffusion system
US5467201A (en) * 1994-05-31 1995-11-14 Xerox Corporation Iterative error diffusion system
US6427030B1 (en) * 1994-08-03 2002-07-30 Xerox Corporation Method and system for image conversion utilizing dynamic error diffusion
US5581371A (en) * 1995-03-07 1996-12-03 Eastman Kodak Company Error diffusion method
US5757517A (en) * 1995-03-23 1998-05-26 Eastman Kodak Company Adaptive error diffusion method
IL118180A (en) 1996-05-08 2000-12-06 Modus Biolog Membranes Ltd Pharmaceutical compositions comprising a phosphatidic acid (PA) enriched natural phospholipid preparation and the production of such preparation
US5668638A (en) * 1996-06-27 1997-09-16 Xerox Corporation Error diffusion method with symmetric enhancement
JPH1093819A (ja) * 1996-09-12 1998-04-10 Canon Inc 画像処理装置
US5848224A (en) 1996-09-26 1998-12-08 Hewlett-Packard Company Optimally pipelined error diffusion architecture for converting scanned image into four-color printed image
JP3834901B2 (ja) * 1996-12-27 2006-10-18 ブラザー工業株式会社 中間調画像の２値化方法
US5974228A (en) 1997-01-28 1999-10-26 Hewlett-Packard Company Image rendition by plural-row error diffusion, for faster operation and smaller integrated circuits
US5982992A (en) * 1997-09-05 1999-11-09 Xerox Corporation Error diffusion in color printing where an intra-gamut colorant is available
US6307978B1 (en) 1998-06-03 2001-10-23 Wellesley College System and method for parallel error diffusion dithering
US6501564B1 (en) * 1999-05-07 2002-12-31 Hewlett-Packard Company Tone dependent plane dependent error diffusion halftoning
US6760127B1 (en) * 2000-06-01 2004-07-06 Xerox Corporation Multi-level semi-vector error diffusion
AUPR234700A0 (en) * 2000-12-29 2001-01-25 Canon Kabushiki Kaisha Error diffusion using next scanline error impulse response
US6907457B2 (en) 2001-01-25 2005-06-14 Dell Inc. Architecture for access to embedded files using a SAN intermediate device
US7355745B2 (en) * 2001-04-13 2008-04-08 Hewlett Packard Document-to-printer color gamut matching
US7355747B2 (en) * 2002-01-18 2008-04-08 Hewlett-Packard Development Company, L.P. System for improving the speed of data processing
JP2003283829A (ja) 2002-03-22 2003-10-03 Ricoh Co Ltd 画像処理装置および方法
US20040008382A1 (en) 2002-07-09 2004-01-15 Barbalet Thomas Samuel System and method for error diffusion screening with parallel processing
JP2005012726A (ja) * 2003-06-23 2005-01-13 Konica Minolta Business Technologies Inc 画像処理装置および画像処理方法
US7518753B2 (en) * 2004-05-20 2009-04-14 Agfa Graphics Nv Full control multilevel error diffusion
US7639887B2 (en) * 2004-12-14 2009-12-29 Intel Corporation Error diffusion-based image processing
KR100648656B1 (ko) * 2004-12-14 2006-11-24 삼성전자주식회사 오차확산 처리방법 및 그 처리장치
US7440140B2 (en) * 2005-04-29 2008-10-21 Hewlett-Packard Development Company, L.P. Sequential color error diffusion with forward and backward exchange of information between color planes

Also Published As

Publication number Publication date
US8705888B2 (en) 2014-04-22
US7639887B2 (en) 2009-12-29
TWI319283B (en) 2010-01-01
TW200627926A (en) 2006-08-01
JP4705645B2 (ja) 2011-06-22
CN101076995B (zh) 2013-03-27
CN103179321A (zh) 2013-06-26
US20120057054A1 (en) 2012-03-08
KR100889410B1 (ko) 2009-03-20
KR20070086126A (ko) 2007-08-27
US8077993B2 (en) 2011-12-13
US20100053655A1 (en) 2010-03-04
JP2008523739A (ja) 2008-07-03
CN103179321B (zh) 2016-01-20
CN101076995A (zh) 2007-11-21
US20060126957A1 (en) 2006-06-15
EP1829358A1 (de) 2007-09-05
WO2006066185A1 (en) 2006-06-22

Similar Documents

Publication Publication Date Title
US8705888B2 (en) Error diffusion-based image processing
US11470337B2 (en) Image processor, image processing system including image processor, system-on-chip including image processing system, and method of operating image processing system
US20120050815A1 (en) Image processing apparatus and image processing method
US20070263234A1 (en) Systems, methods and devices for rotating images
US20090244080A1 (en) Line buffer circuit, image processing apparatus, and image forming apparatus
US7480078B2 (en) Method and system for performing multi-pixel parallel error diffusion enabling high-speed diffusion processing without increasing the system clock rate
US6633975B1 (en) Data processing system having plurality of processors and executing series of processings in prescribed order
US20220417542A1 (en) Image processing device, image processing system including image processing device, system-on-chip including image processing system, and method of operating image processing system
JPH0638031A (ja) 画像濃度再現方法
JPH0638035A (ja) シェーディング補正方法およびシェーディング補正装置
JP5612965B2 (ja) 画像処理装置及び画像処理方法
JPH1093819A (ja) 画像処理装置
JP2004289846A (ja) 取込画像のノイズを補償するシステムおよび方法
JP4262148B2 (ja) 画像処理装置及び画像処理方法
AU745942B2 (en) A system for performing halftoning
JP2008035035A (ja) 画像処理装置
JP3074222B2 (ja) 画像処理装置
JPH0730756A (ja) 画像処理方法及び装置
JPH11308448A (ja) 画像処理装置及び画像処理方法
JP2005050341A (ja) 画像処理装置およびその方法
JPH02107064A (ja) 画像信号処理装置
JP2001333282A (ja) 画像処理装置
JP2002010080A (ja) 擬似階調変換装置および擬似階調変換方法
Park et al. A VLSI implementation of image processor for facsimile and digital copier
JP2005286360A (ja) 画像処理装置及び画像処理方法ならびにそのプログラム

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20070709

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC NL PL PT RO SE SI SK TR

DAX Request for extension of the european patent (deleted)
17Q First examination report despatched

Effective date: 20090320

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

INTG Intention to grant announced

Effective date: 20180404

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC NL PL PT RO SE SI SK TR

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: CH

Ref legal event code: EP

REG Reference to a national code

Ref country code: AT

Ref legal event code: REF

Ref document number: 1039270

Country of ref document: AT

Kind code of ref document: T

Effective date: 20180915

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 602005054571

Country of ref document: DE

REG Reference to a national code

Ref country code: NL

Ref legal event code: FP

REG Reference to a national code

Ref country code: LT

Ref legal event code: MG4D

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20180905

Ref country code: BG

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20181205

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20180905

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20181206

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20180905

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: NL

Payment date: 20181213

Year of fee payment: 14

REG Reference to a national code

Ref country code: AT

Ref legal event code: MK05

Ref document number: 1039270

Country of ref document: AT

Kind code of ref document: T

Effective date: 20180905

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LV

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20180905

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20180905

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20181212

Year of fee payment: 14

Ref country code: FR

Payment date: 20181127

Year of fee payment: 14

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: RO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20180905

Ref country code: IT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20180905

Ref country code: PL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20180905

Ref country code: EE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20180905

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190105

Ref country code: AT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20180905

Ref country code: CZ

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20180905

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: PT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190105

Ref country code: SK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20180905

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 602005054571

Country of ref document: DE

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20180905

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

26N No opposition filed

Effective date: 20190606

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MC

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20180905

Ref country code: LU

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20181213

Ref country code: SI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20180905

REG Reference to a national code

Ref country code: IE

Ref legal event code: MM4A

REG Reference to a national code

Ref country code: BE

Ref legal event code: MM

Effective date: 20181231

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20181213

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: BE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20181231

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20181231

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20181231

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: TR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20180905

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CY

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20180905

Ref country code: HU

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT; INVALID AB INITIO

Effective date: 20051213

REG Reference to a national code

Ref country code: NL

Ref legal event code: MM

Effective date: 20200101

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20191213

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20200101

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20191231

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20191213

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20200922

Year of fee payment: 16

REG Reference to a national code

Ref country code: DE

Ref legal event code: R119

Ref document number: 602005054571

Country of ref document: DE

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20220701