EP1780692A2

EP1780692A2 - Plasma display apparatus and method of driving the same

Info

Publication number: EP1780692A2
Application number: EP06255457A
Authority: EP
Inventors: Kyu Choon Cho
Original assignee: LG Electronics Inc
Current assignee: LG Electronics Inc
Priority date: 2005-10-25
Filing date: 2006-10-24
Publication date: 2007-05-02
Also published as: JP2007122052A; CN1956038A; US20070103402A1; KR100765511B1; KR20070044746A

Abstract

A plasma display apparatus includes a plasma display panel including a scan electrode, and a scan driver. The scan driver supplies a setup pulse to the scan electrode through resonance between equivalent capacitance of the plasma display panel and a setup inductor. The method of driving the plasma display apparatus includes supplying a first voltage to the scan electrode during a reset period, and supplying a pulse gradually rising from the first voltage to a second voltage to the scan electrode during the reset period through resonance between the plasma display panel and the inductor.

Description

This invention relates to a display apparatus. It particularly relates to a plasma display apparatus and a method of driving the same.
A plasma display apparatus is a type of display apparatus comprising a plasma display panel and a driver for driving the plasma display panel.
The plasma display panel comprises a front panel, a rear panel and barrier ribs formed between the front panel and the rear panel. The barrier ribs forms unit discharge cell or discharge cells. Each of discharge cells is filled with a main discharge gas such as neon (Ne), helium (He) and a mixture of Ne and He, and an inert gas containing a small amount of xenon (Xe).
A plurality of discharge cells form one pixel. For example, a red (R) discharge cell, a green (G) discharge cell and a blue (B) discharge cell form one pixel.
When the plasma display panel is discharged using a high frequency voltage, the inert gas generates vacuum ultraviolet light, which thereby causes phosphors formed between the barrier ribs to emit visible light, thus displaying an image. Since the plasma display panel can be manufactured to be thin and light, it has attracted attention as a next generation display device.
The present invention seeks to provide an improved plasma display apparatus and method of driving same.
In accordance with a first aspect of the invention, a plasma display apparatus comprises a plasma display panel comprising a scan electrode, and a scan driver arranged to supply a setup pulse to the scan electrode through resonance between the plasma display panel and a setup inductor.
The scan driver may comprise a setup capacitor arranged to be charged to a setup voltage supplied from a setup voltage source, a setup switch, connected between the setup voltage source and the scan electrode, and arranged to control the supplying of the setup voltage to the scan electrode, and the setup inductor connected between the setup switch and the scan electrode.
The magnitude of the highest voltage of the setup pulse may lie in the range from the sum of the magnitude of a sustain voltage and the magnitude of a setup voltage, to the sum of the magnitude of the sustain voltage and two times the magnitude of the setup voltage.
In accordance with another aspect of the invention, a plasma display apparatus comprises a plasma display panel comprising a scan electrode, a sustain pulse supply unit arranged to supply a first voltage to the scan electrode, and a setup pulse supply unit arranged to supply to the scan electrode a setup pulse that gradually rises from the first voltage to a second voltage through resonance between the plasma display panel and an inductor.
The first voltage may be equal to a sustain voltage level.
The setup pulse supply unit may comprise a setup capacitor arranged to be charged to a setup voltage supplied from a setup voltage source, a setup switch, connected between the setup voltage source and the scan electrode and arranged to control the supplying of the setup voltage to the scan electrode, and a setup inductor, connected between the setup switch and the scan electrode and arranged to supply a charge voltage to the setup capacitor and to the scan electrode through resonance between the capacitance of plasma display panel and the setup inductor.
The magnitude of the difference between the second voltage and the first voltage may lie in the range from the magnitude of the setup voltage to two times the magnitude of the setup voltage.
The sustain pulse supply unit may comprise a sustain voltage supply controller, connected between the scan electrode and a sustain voltage source, and arranged to control the supplying of the sustain voltage to the scan electrode, and a ground level voltage supply controller, connected between the scan electrode and a ground level voltage source, and arranged to control the supplying of a ground level voltage to the scan electrode.
A current path for charging the setup capacitor to the setup voltage may pass through the setup voltage source, the setup capacitor, the ground level voltage supply controller and the ground level voltage source.
A current path for supplying a charge voltage to the setup capacitor to the scan electrode through the resonance between the plasma display panel and the setup inductor may pass through the setup capacitor, the setup switch, the setup inductor and the plasma display panel.
One terminal of the setup capacitor may be connected to the setup voltage source, and the other terminal of the setup capacitor may be connected to a drain terminal of the ground level voltage supply controller. A drain terminal of the setup switch may be commonly connected to one terminal of the setup capacitor and the setup voltage source, and a source terminal of the setup switch may be connected to one terminal of the setup inductor. The other terminal of the setup inductor may be connected to the scan electrode.
The setup pulse supply unit may comprise an inductor.
In accordance with another aspect of the invention, a method of driving the plasma display apparatus comprises supplying a first voltage to a scan electrode during a reset period, and supplying a pulse which gradually rises from the first voltage to a second voltage to the scan electrode during the reset period through resonance between the capacitance of a plasma display panel and an inductor.
The first voltage may be equal to a sustain voltage level.
The supplying of the pulse which gradually rises from the first voltage to the second voltage may comprise charging a setup capacitor to a setup voltage, and supplying a charge voltage to a setup capacitor to the scan electrode through the resonance between the plasma display panel and the inductor.
The magnitude of the difference between the second voltage and the first voltage may lie in the range from a magnitude of the setup voltage to two times the magnitude of the setup voltage.
Embodiments of the invention will now be described, by way of non-limiting example only, with reference to the drawings, in which
FIG. 1 illustrates a general plasma display apparatus according to an embodiment;
FIG. 2 illustrates an example of the structure of a plasma display panel of the plasma display apparatus;
FIG. 3 illustrates a driving waveform produced by the plasma display apparatus according to the embodiment;
FIG. 4 illustrates a scan driver of the plasma display apparatus according to the embodiment;
FIGs. 5 to 7 illustrate a current path for producing a setup pulse of the driving waveform produced by the plasma display apparatus according to the embodiment;
FIG. 8 illustrates an equivalent circuit of a closed loop formed by the current path illustrated in FIG. 7; and
FIG. 9 illustrates a voltage supplied to a panel capacitor of FIG. 8.
As illustrated in FIG. 1, a plasma display apparatus comprises a plasma display panel 100 and a driver arrangement for supplying a predetermined driving voltage to electrodes of the plasma display panel 100, which in the present embodiment comprises a data driver 101, a scan driver 102 and a sustain driver 103.
In the following, the scan driver 102 and the sustain driver 103 will be called a first driver, and the data driver 101 will be called a second driver.
A front panel (not illustrated) and a rear panel (not illustrated) of the plasma display panel 100 are coalesced with each other spaced apart by a predetermined distance. A plurality of electrodes, which in the present example comprise a plurality of scan electrodes Y and a plurality of sustain electrodes, are formed in the plasma display panel 100.
A detailed description of the structure of the plasma display panel 100, will now be given with reference to FIG. 2.
As illustrated in FIG. 2, the plasma display panel 100 of the plasma display apparatus comprises a front panel 200 and a rear panel 210 which are joined together in parallel opposite each other with a predetermined distance therebetween. The front panel 200 comprises a front substrate 201 which is a display surface. The rear panel 210 comprises a rear substrate 211 constituting a rear surface. A plurality of scan electrodes 202 and a plurality of sustain electrodes 203 are formed in pairs on the front substrate 201, on which an image is displayed. A plurality of address electrodes 213 are arranged on the rear substrate 111 to intersect the scan electrodes 202 and the sustain electrodes 203.
The scan electrode 202 and the sustain electrode 203 each comprise transparent electrodes 202a and 203a made of transparent indium-tin-oxide (ITO) material and bus electrodes 202b and 203b made of a metal material. The scan electrode 202 and the sustain electrode 203 generate a mutual discharge therebetween in a selected discharge cell and maintain light-emissions of the discharge cells.
The scan electrode 202 and the sustain electrode 203 are covered with one or more upper dielectric layers 204 to limit the discharge current and to provide insulation between respective scan electrodes 202 and sustain electrodes 203. A protective layer 205 with a deposit of Mg0 is formed on an upper surface of the upper dielectric layer 204 to facilitate discharge conditions.
A plurality of stripe-type (or well-type) barrier ribs 212 are formed in parallel on the rear substrate 211 of the rear panel 210 to form a plurality of discharge spaces (i.e., a plurality of discharge cells). The plurality of address electrodes 213 for performing an address discharge to generate vacuum ultraviolet radiation are arranged in parallel to the barrier ribs 212.
An upper surface of the rear pane 210 is coated with Red (R), green (G) and blue (B) phosphors 214 for emitting visible light for an image display when an address discharge is performed. A lower dielectric layer 215 is formed between the address electrodes 213 and the phosphors 214 to protect the address electrodes 213.
The plasma display panel applicable to the embodiment of the present invention was illustrated in FIG. 2 by way of example only. Accordingly, the invention is not limited to plasma display panels having the structure of the plasma display panel illustrated in FIG. 2.
For example, in FIG. 2, the scan electrode 202 and the sustain electrode 203 each comprise the transparent electrode and the bus electrode. However, in a modification, not shown, at least one of the scan electrode 202 and the sustain electrode 203 may comprise either the bus electrode or the transparent electrode.
Further, a structure of the plasma display panel, in which the front panel 200 comprises the scan electrode 202 and the sustain electrode 203 and the rear panel 210 comprises the address electrode 213, is illustrated in FIG. 2. However, in a modification the front panel 200 may comprise all the scan electrode 202, the sustain electrode 203 and the address electrode 213. At least one of the scan electrode 202, the sustain electrode 203 and the address electrode 213 may be formed on the barrier rib 212.
Considering the structure of the plasma display panel 100 of FIG. 2, a plasma display panel 100 applicable to the embodiment needs only to comprise the scan electrode 202, the sustain electrode 203 and the address electrode 210. The plasma display panel 100 may have various structures except for the above-described structural characteristic.
Returning to FIG. 1, the scan driver 102 supplies a setup pulse and a set-down pulse to the scan electrode Y of the plasma display panel 100 during a reset period. Further, the scan driver 102 supplies a scan pulse to the scan electrode Y during an address period, and supplies a sustain pulse to the scan electrode Y during a sustain period.
The setup pulse is supplied to the scan electrode Y during the reset period through resonance between the plasma display panel 100 and an inductor. This will be described later.
The sustain driver 103 supplies a sustain pulse to the sustain electrode Z during the sustain period when an image is displayed. The scan driver 102 and the sustain driver 103 operate alternately.
The data driver 101 supplies a data pulse Vd to the address electrode X during the address period.
As illustrated in FIG. 3, each subfield comprises a reset period RP for initializing discharge cells of the whole screen, an address period AP for selecting cells to be discharged, and a sustain period SP for maintaining a discharge of the selected discharge cells.
The reset period RP is further divided into a setup period SU and a set-down period SD. During the setup period SU, a setup pulse gradually rising from a first voltage Vs to a second voltage (Vs+2Vst) is simultaneously supplied to all the scan electrodes Y, thereby generating a weak discharge (i.e., a setup discharge) within the discharge cells of the whole screen. This results in the forming of wall charges within the discharge cells.
The setup pulse of the driving waveform produced by the plasma display apparatus according to the embodiment illustrated in FIG. 3 is formed through resonance unlike the prior art. The forming of the setup pulse will be described later.
During the set-down period SD, a set-down pulse, which falls from a positive sustain voltage Vs lower than the highest voltage of the setup pulse to a scan voltage -Vy of a negative polarity with a predetermined slope, is simultaneously supplied to the scan electrodes Y, thereby generating a weak erase discharge within the discharge cells. Accordingly, unnecessary wall charges and space charges produced by the setup discharge are erased such that the remaining wall charges are uniform inside the discharge cells to the extent that the address discharge can be stably performed.
During the address period AP, a scan pulse SCNP of a negative polarity is sequentially supplied to the scan electrodes Y and, at the same time, a data pulse DP of a positive polarity is supplied to the address electrodes X. As the voltage difference between the scan pulse SCNP and the data pulse DP is added to the wall voltage generated during the reset period RP, the address discharge occurs within the discharge cells to which the data pulse DP is supplied. Wall charges are formed inside the discharge cells selected by performing the address discharge. The positive sustain voltage Vs is supplied to the sustain electrodes Z during the set-down period SD and the address period AP.
During the sustain period SP, a sustain pulse SUSP is alternately supplied to the scan electrodes Y and the sustain electrodes Z. As the wall voltage within the discharge cells selected by performing the address discharge is added to the sustain pulse SUSP, every time the sustain pulse SUSP is supplied, a sustain discharge of a surface discharge type occurs between the scan electrodes Y and the sustain electrodes Z.
A detailed description of the scan driver of the plasma display apparatus for supplying the above driving waveform of FIG. 3, will now be described with reference to FIG. 4.
As illustrated in FIG. 4, a plasma display apparatus comprises a scan driver 40 for driving the scan electrode Y of a panel capacitor Cp and a sustain driver 50 for driving the sustain electrode Z of the panel capacitor Cp.
The panel capacitor Cp indicates the equivalent capacitance formed between the scan electrode Y and the sustain electrode Z of the plasma display panel.
The scan driver 40 comprises a sustain pulse supply unit 41, a first switch Q1, a setup pulse supply unit 45, a second switch Q2, a set-down pulse supply unit 46, a scan pulse supply unit 47, a scan reference voltage supply unit 48 and a scan integrated circuit 49.
The sustain pulse supply unit 41 supplies a sustain pulse having the first voltage (i.e., the sustain voltage Vs) and a ground level voltage GND to the scan electrode Y of the panel capacitor Cp during the sustain period.
The sustain pulse supply unit 41 comprises a sustain voltage supply controller 42 and a ground level voltage supply controller 43. The sustain voltage supply controller 42 is connected between a sustain voltage source (not illustrated) and the scan electrode Y to control the supplying of the sustain voltage Vs to the scan electrode Y. The ground level voltage supply controller 43 is connected between a ground level voltage source (not illustrated) and the scan electrode Y to control the supplying of the ground level voltage GND to the scan electrode Y.
The sustain voltage supply controller 42 is connected between the sustain voltage source and a first node N1 to supply the sustain voltage Vs to the scan electrode Y of the panel capacitor Cp during the setup period and the sustain period.
The sustain voltage supply controller 42 electrically connects the sustain voltage source to the first node N1 in response to a switching control signal supplied by a timing controller (not illustrated). As a result, the sustain voltage Vs is supplied to the first node N1 during the setup period and the sustain period.
The ground level voltage supply controller 43 is connected between the ground level voltage source and the first node N1 to supply the ground level voltage GND to the scan electrode Y of the panel capacitor Cp during the sustain period. The sustain voltage supply controller 42 and the ground level voltage supply controller 43 alternately operate during the sustain period.
The ground level voltage supply controller 43 electrically connects the ground level voltage source to the first node N1 in response to a switching control signal supplied by the timing controller.
The sustain voltage supply controller 42 and the ground level voltage supply controller 43 operate alternately during the sustain period such that the sustain voltage Vs and the ground level voltage GND are alternately supplied to the first node N1 during the sustain period.
In the present non-limiting embodiment, the sustain voltage supply controller 42 and the ground level voltage supply controller 43 each comprise a respective field effect transistor. A drain terminal of the sustain voltage supply controller 42 is connected to the sustain voltage source, and a source terminal of the sustain voltage supply controller 42 is connected to a drain terminal of the ground level voltage supply controller 43. A source terminal of the ground level voltage supply controller 43 is connected to the ground level voltage source.
As illustrated in FIG. 5, with the above configuration of the sustain pulse supply unit 41, a current path passing through the sustain voltage source, the sustain voltage supply controller 42, the first switch Q1, the second switch Q2, an eighth switch Q8 and the panel capacitor Cp is formed during the setup period such that the sustain voltage Vs is supplied to the scan electrode Y of the panel capacitor Cp.
The setup pulse supply unit 45 is connected between the sustain pulse supply unit 41 and the scan electrode Y of the panel capacitor Cp to supply a setup pulse to the scan electrode Y during the setup period. The setup pulse supply unit 45 comprises a setup voltage source (not illustrated), a setup capacitor Cst, a setup switch Qst and a setup inductor Lst.
The setup voltage source supplies a setup voltage Vst to the scan electrode Y during the setup period.
The setup capacitor Cst is connected between the setup voltage source and the sustain pulse supply unit 41 such that the setup capacitor Cst is charged to the setup voltage Vst supplied from the setup voltage source.
The setup switch Qst is connected between the setup voltage source and the scan electrode Y to control the supplying of the setup voltage Vst to the scan electrode Y in response to a switching control signal supplied by the timing controller. The setup switch Qst may, as shown, comprise a field effect transistor.
The setup inductor Lst is connected between the setup switch Qst and the scan electrode Y such that a charge voltage to the setup capacitor Cst is supplied to the scan electrode Y using series resonance between the setup inductor Lst and the panel capacitor Cp.
One terminal of the setup capacitor Cst is connected to the setup voltage source, and the other terminal of the setup capacitor Cst is connected to the drain terminal of the ground level voltage supply controller 43. A drain terminal of the setup switch Qst is commonly connected to one terminal of the setup capacitor Cst and the setup voltage source, and a source terminal of the setup switch Qst is connected to one terminal of the setup inductor Lst. The other terminal of the setup inductor Lst is connected to the scan electrode Y.
As illustrated in FIG. 6, since one terminal of the setup capacitor Cst is connected to the setup voltage source and the other terminal of the setup capacitor Cst is connected to the first node N1 being a common node of the source terminal of the sustain voltage supply controller 42 and the drain terminal of the ground level voltage supply controller 43, a current path passing through the setup voltage source, the setup capacitor Cst, the ground level voltage supply controller 43 and the ground level voltage is formed such that the setup capacitor Cst is charged to the setup voltage level Vst.
As illustrated in FIG. 7, since the drain terminal of the setup switch Qst is commonly connected to one terminal of the setup capacitor Cst and the setup voltage source, the source terminal of the setup switch Qst is connected to one terminal of the setup inductor Lst, and the other terminal of the setup inductor Lst is connected to the scan electrode Y, a current path passing through the setup capacitor Cst, the setup switch Qst, the setup inductor Lst, the second switch Q2 and the panel capacitor Cp is formed such that the setup pulse gradually rising from the first voltage Vs to the second voltage (Vs+2Vst) is supplied to the scan electrode Y of the panel capacitor Cp using the charge voltage to the setup capacitor Cst through LC resonance between the setup inductor Lst and the panel capacitor Cp.
A detailed description of the current path which is an equivalent circuit of a closed loop formed by the current path illustrated in FIG. 7, will now be described with reference to FIGs. 8 and 9.
As illustrated in FIG. 8, a closed loop formed by the current path illustrated in FIG. 7 can be considered as an equivalent series circuit, being the connection of the setup capacitor Cst, the setup inductor Ist, the panel capacitor Cp and the setup capacitor Cst.
The setup capacitor Cst, as described above, remains in a state charged to the setup voltage Vst.
The equivalent circuit generates Lst-Cp series resonance between the setup inductor Lst and the panel capacitor Cp. A voltage waveform illustrated in FIG. 9 is supplied to the terminals of the panel capacitor Cp.
The resonance period of the waveform of the voltage supplied to the terminals of the panel capacitor Cp is represented by the following Equation 1.
$\begin{array}{l} [Equation 1] \\ Ts = 2 π \sqrt{LstCp} \end{array}$
In the above Equation 1, Ts indicates the resonance period of the closed loop illustrated in FIG. 8, Lst indicates the inductance of the setup inductor, and Cp indicates the equivalent capacitance of the panel capacitor.
While not essential to the invention in its broadest aspect, it is preferable that the setup switch Qst operates in the saturation region. Since the setup switch Qst operates in the saturation region, power consumption in a driving operation of the plasma display panel is reduced and the stable driving of the plasma display panel is ensured.
While not essential to the invention in its broadest aspect, it is preferable to control the highest voltage of the setup pulse by controlling turn-on time of the setup switch Qst. It is also preferable, but not essential, to control the turn-on time of the setup switch Qst in the range of one quarter to one half of the resonance period Ts.
As illustrated in FIGs. 8 and 9, by controlling the turn-on time of the setup switch Qst in consideration of the resonance period Ts of the Lst-Cp series resonance, the highest voltage (i.e., the second voltage) of the setup pulse may selected to lie in the range of a voltage of Vs+Vst to a voltage of Vs+2Vst in accordance with the driving environment.
Referring again to FIGs. 3 and 4, the setup pulse supply unit 45 may further comprise a reverse blocking diode D1, whose an anode terminal is connected to the setup voltage source and a cathode terminal is commonly connected to one terminal of the setup capacitor Cst and the drain terminal of the setup switch Qst. The reverse blocking diode D 1 prevents the flowing of inverse current from the setup capacitor Cst to the setup voltage source.
The set-down pulse supply unit 46 is connected between a third node N3 and the scan pulse supply unit 47. The set-down pulse supply unit 46 supplies a falling pulse falling from the ground level voltage GND to a scan voltage-Vy of a negative polarity with a predetermined slope to the scan electrode Y of the panel capacitor Cp during the reset period.
The set-down pulse supply unit 46 comprises a third switch Q3, a first variable resistance R1 and a first capacitor C1. The third switch Q3 is connected between the third node N3 and a scan voltage source. The first variable resistance R1 is connected to a gate terminal of the third switch Q3. The first capacitor C1 is connected between a common terminal of the gate terminal of the third switch Q3 and the first variable resistance R1 and the third node N3.
The third switch Q3 electrically connects the scan voltage source to the third node N3 in response to a switching control signal supplied by the timing controller.
Accordingly, the set-down pulse having the scan voltage level -Vy of the negative polarity is supplied to the third node N3 during the reset period. The set-down pulse supplied to the third node N3 has a predetermined slope.
The first variable resistance R1 and the first capacitor C1 are connected to the gate terminal of the third switch Q3 to control the predetermined slope of the set-down pulse. Accordingly, the set-down pulse with a negative slope is supplied to the third node N3 during the reset period.
The scan pulse supply unit 47 is connected to the third node N3 to supply a scan pulse SCNP having the scan voltage level -Vy of the negative polarity to the scan electrode Y of the panel capacitor Cp during the address period. The scan pulse supply unit 47 comprises the scan voltage source and a fourth switch Q4 connected between the scan voltage source and the third node N3.
The fourth switch Q4 transmits the scan voltage level -Vy of the negative polarity supplied from the scan voltage source to the third node N3 in response to a switching control signal supplied by the timing controller. Accordingly, the scan voltage level -Vy of the negative polarity is transmitted to the third node N3 during the address period.
The scan reference voltage supply unit 48 is connected between the third node N3 and the scan integrated circuit 49 to supply the scan reference voltage Vsc to the scan electrode Y of the panel capacitor Cp during the address period.
The scan reference voltage supply unit 48 comprises a scan reference voltage source, a fifth switch Q5 and a sixth switch Q6 which are connected in series between the scan reference voltage source and the third node N3.
The fifth switch Q5 is connected between the scan reference voltage source and the scan integrated circuit 49. The fifth switch Q5 electrically connects the scan reference voltage source to a fourth node N4 in response to a switching control signal supplied by the timing controller.
Accordingly, the scan reference voltage Vsc is transmitted to the fourth node N4 during the address period. The fourth node N4 is a common node of the fifth switch Q5, the sixth switch Q6 and the scan integrated circuit 49.
The sixth switch Q6 is connected between the third node N3 and the fourth node N4. The sixth switch Q6 electrically connects the third node N3 to the fourth node N4 in response to a switching control signal supplied by the timing controller.
Accordingly, the voltage supplied to the third node N3 is transmitted to the fourth node N4, and the voltage supplied to the fourth node N4 is transmitted to the third node N3.
The scan integrated circuit 49 comprises a seventh switch Q7 and an eighth switch Q8 which are connected between the third node N3 and the fourth node N4 in a push-pull form. A common node of the seventh switch Q7 and the eighth switch Q8 is connected to the scan electrode Y of the panel capacitor Cp.
The seventh switch Q7 supplies the voltage supplied to the fourth node N4 to the scan electrode Y of the panel capacitor Cp through a body diode of the seventh switch Q7.
In other words, the seventh switch Q7 electrically connects to the scan electrode Y of the panel capacitor Cp to the fourth node N4 through the body diode of the seventh switch Q7 such that when a voltage of a negative polarity is supplied to the fourth node N4, the voltage supplied to the fourth node N4 is supplied to the scan electrode Y of the panel capacitor Cp.
Accordingly, the voltage of the negative polarity supplied to the fourth node N4 is supplied to the scan electrode Y of the panel capacitor Cp.
The eighth switch Q8 supplies the voltage supplied to the third node N3 to the scan electrode Y of the panel capacitor Cp through a body diode of the eighth switch Q8.
In other words, the eighth switch Q8 electrically connects to the scan electrode Y of the panel capacitor Cp to the third node N3 through the body diode of the eighth switch Q8 such that when a voltage of a positive polarity is supplied to the third node N3, the voltage supplied to the third node N3 is supplied to the scan electrode Y of the panel capacitor Cp.
Accordingly, the voltage of the positive polarity supplied to the third node N3 is supplied to the scan electrode Y of the panel capacitor Cp.
The sustain driver 50 supplies a bias voltage of a positive polarity having the sustain voltage level Vs to the sustain electrode Z of the panel capacitor Cp during the set-down period and the address period. Further, the sustain driver 50 supplies the sustain pulse having the ground level voltage GND and the sustain voltage level Vs to the sustain electrode Z of the panel capacitor Cp during the sustain period.
As described above, since the plasma display apparatus generates the setup pulse using the saturation region of the setup switch Qst during the setup period, less heat is dissipated in the process of driving the plasma display panel, thereby securing a stable driving of the plasma display panel. Further, the configuration of the circuit components is simple, thereby reducing the manufacturing cost of the plasma display panel.
The foregoing embodiments and advantages are merely exemplary and are not to be construed as limiting the present invention. The present teaching can be readily applied to other types of apparatuses. The description of the foregoing embodiments is intended to be illustrative, and not to limit the scope of the claims. Many alternatives, modifications, and variations will be apparent to those skilled in the art.

Claims

A plasma display apparatus comprising:
a plasma display panel comprising a scan electrode; and

a scan driver arranged to supply a setup pulse to the scan electrode through resonance between the plasma display panel and a setup inductor.
The plasma display apparatus of claim 1, wherein the scan driver comprises
a setup capacitor arranged to be charged to a setup voltage supplied from a setup voltage source,
a setup switch, connected between the setup voltage source and the scan electrode, and arranged to control the supplying of the setup voltage to the scan electrode, and
the setup inductor is connected between the setup switch and the scan electrode.
The plasma display apparatus of claim 1, wherein the magnitude of the highest voltage of the setup pulse lies in the range from the sum of the magnitude of a sustain voltage and the magnitude of a setup voltage, to a sum of the magnitude of the sustain voltage and two times the magnitude of the setup voltage.
A plasma display apparatus comprising:
a plasma display panel comprising a scan electrode;

a sustain pulse supply unit arranged to supply a first voltage to the scan electrode; and

a setup pulse supply unit arranged to supply a setup pulse which gradually rises from the first voltage to a second voltage to the scan electrode through resonance between the plasma display panel and an inductor.
The plasma display apparatus of claim 4, wherein the first voltage is equal to a sustain voltage level.
The plasma display apparatus of claim 5, wherein the setup pulse supply unit comprises
a setup capacitor arranged to be charged to a setup voltage supplied from a setup voltage source,
a setup switch, connected between the setup voltage source and the scan electrode, and arranged to control the supplying of the setup voltage to the scan electrode, and
a setup inductor, connected between the setup switch and the scan electrode, and arranged to supply a charge voltage to the setup capacitor and to the scan electrode through resonance between the plasma display panel and the setup inductor.
The plasma display apparatus of claim 6, wherein the magnitude of the difference between the second voltage and the first voltage lies in the range from the magnitude of the setup voltage to two times the magnitude of the setup voltage.
The plasma display apparatus of claim 6, wherein the sustain pulse supply unit comprises
a sustain voltage supply controller, connected between the scan electrode and a sustain voltage source, arranged to control the supplying of the sustain voltage to the scan electrode, and
a ground level voltage supply controller, connected between the scan electrode and a ground level voltage source and arranged to control the supplying of a ground level voltage to the scan electrode.
The plasma display apparatus of claim 8, wherein a current path for charging the setup capacitor to the setup voltage passes through the setup voltage source, the setup capacitor, the ground level voltage supply controller and the ground level voltage source.
The plasma display apparatus of claim 8, wherein a current path for supplying a charge voltage to the setup capacitor to the scan electrode through the resonance between the plasma display panel and the setup inductor passes through the setup capacitor, the setup switch, the setup inductor and the plasma display panel.
The plasma display apparatus of any one of claims 8 to 10, wherein one terminal of the setup capacitor is connected to the setup voltage source, and the other terminal of the setup capacitor is connected to a drain terminal of the ground level voltage supply controller,
a drain terminal of the setup switch is commonly connected to one terminal of the setup capacitor and the setup voltage source, and a source terminal of the setup switch is connected to one terminal of the setup inductor, and
the other terminal of the setup inductor is connected to the scan electrode.
The plasma display apparatus of claim 4 or 5, wherein the setup pulse supply unit comprises an inductor.
A method of driving the plasma display apparatus comprising:
supplying a first voltage to a scan electrode during a reset period; and

supplying a pulse gradually rising from the first voltage to a second voltage to the scan electrode during the reset period through resonance between a plasma display panel and an inductor.
The method of claim 13, wherein the first voltage is equal to a sustain voltage level.
The method of claim 13 or 14, wherein the supplying of the pulse gradually rising from the first voltage to the second voltage comprises charging a setup capacitor to a setup voltage, and supplying a charge voltage to a setup capacitor and to the scan electrode through resonance between the capacitance of the plasma display panel and the inductor.
The method of claim 15, wherein the magnitude of the difference between the second voltage and the first voltage lies in the range from the magnitude of the setup voltage to two times the magnitude of the setup voltage.